diff options
| author | Claudiu Zissulescu <claziss@synopsys.com> | 2017-12-18 16:26:47 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2017-12-18 16:26:47 +0100 |
| commit | 0cf0bc67f6fad8653edb7656080f7f61394c92b4 (patch) | |
| tree | b35c509aaca11819cc286ad05ee419d65418b7a9 /gcc/config | |
| parent | 2bd36ebab737f4bd3f5d306b269ffdff22eace4f (diff) | |
| download | gcc-0cf0bc67f6fad8653edb7656080f7f61394c92b4.zip gcc-0cf0bc67f6fad8653edb7656080f7f61394c92b4.tar.gz gcc-0cf0bc67f6fad8653edb7656080f7f61394c92b4.tar.bz2 | |
[ARC] Update (u)maddsidi patterns.
The accumulator registers are freely used by the compiler. However,
there are a number of instructions which are having an intrinsic use
of these registers. Update patterns to inform the compiler which ones.
gcc/
2017-09-19 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
(umaddsidi4,umaddsidi4): Likewise.
gcc/testsuite
2017-09-19 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tumaddsidi4.c: New test.
From-SVN: r255779
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arc/arc.md | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 880327c..575852e 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6155,13 +6155,25 @@ [(set_attr "length" "0")]) ;; MAC and DMPY instructions -(define_insn_and_split "maddsidi4" +(define_expand "maddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "maddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" @@ -6243,13 +6255,25 @@ (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn_and_split "umaddsidi4" +(define_expand "umaddsidi4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "extend_operand" "") + (match_operand:DI 3 "register_operand" "")] + "TARGET_PLUS_DMPY" + "{ + emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3])); + DONE; + }") + +(define_insn_and_split "umaddsidi4_split" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri"))) - (match_operand:DI 3 "register_operand" "r")))] + (match_operand:DI 3 "register_operand" "r"))) + (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" "#" "TARGET_PLUS_DMPY && reload_completed" |