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| author | Edmar Wienskoski <edmar@freescale.com> | 2012-06-04 18:44:53 +0000 |
|---|---|---|
| committer | Edmar Wienskoski <edmarwjr@gcc.gnu.org> | 2012-06-04 18:44:53 +0000 |
| commit | fbc932e72cff3eb14122acb92415bbc0def82d74 (patch) | |
| tree | 08595c9e0a80a0c62939ac42b7d76ea4814831d7 /gcc/config | |
| parent | 165f639ceabc15665a5afe65b07a50fd0c18ce58 (diff) | |
| download | gcc-fbc932e72cff3eb14122acb92415bbc0def82d74.zip gcc-fbc932e72cff3eb14122acb92415bbc0def82d74.tar.gz gcc-fbc932e72cff3eb14122acb92415bbc0def82d74.tar.bz2 | |
re PR target/53559 (ICE on altivec builtins stv[l|r]x[l])
2012-06-04 Edmar Wienskoski <edmar@freescale.com>
PR target/53559
* config/rs6000/altivec.md (altivec_stvlx): Change machine mode of
operands.
(altivec_stvlxl): Ditto.
(altivec_stvrx): Ditto.
(altivec_stvrxl): Ditto.
gcc/testsuite
2012-06-04 Edmar Wienskoski <edmar@freescale.com>
PR target/53559
* gcc.target/powerpc/cell_builtin_1.c: New test case.
* gcc.target/powerpc/cell_builtin_2.c: Ditto.
* gcc.target/powerpc/cell_builtin_3.c: Ditto.
* gcc.target/powerpc/cell_builtin_4.c: Ditto.
* gcc.target/powerpc/cell_builtin_5.c: Ditto.
* gcc.target/powerpc/cell_builtin_6.c: Ditto.
* gcc.target/powerpc/cell_builtin_7.c: Ditto.
* gcc.target/powerpc/cell_builtin_8.c: Ditto.
From-SVN: r188200
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 42e8dd6..fd4bc9d 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2380,8 +2380,8 @@ (define_insn "altivec_stvlx" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVLX)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvlx %1,%y0" @@ -2389,8 +2389,8 @@ (define_insn "altivec_stvlxl" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVLXL)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvlxl %1,%y0" @@ -2398,8 +2398,8 @@ (define_insn "altivec_stvrx" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVRX)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvrx %1,%y0" @@ -2407,8 +2407,8 @@ (define_insn "altivec_stvrxl" [(parallel - [(set (match_operand:V4SI 0 "memory_operand" "=Z") - (match_operand:V4SI 1 "register_operand" "v")) + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "register_operand" "v")) (unspec [(const_int 0)] UNSPEC_STVRXL)])] "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL" "stvrxl %1,%y0" |