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| author | Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com> | 2024-01-12 11:20:29 +0800 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2024-01-18 15:32:49 +0100 |
| commit | d05b5265110709996fa19af1267c6669b7992879 (patch) | |
| tree | e0a6ccaed1e0bf44071359cdd6ec945802c963ca /gcc/config | |
| parent | 60f58d0630805e8dce79f5489658fd83e42fa8f1 (diff) | |
| download | gcc-d05b5265110709996fa19af1267c6669b7992879.zip gcc-d05b5265110709996fa19af1267c6669b7992879.tar.gz gcc-d05b5265110709996fa19af1267c6669b7992879.tar.bz2 | |
RISC-V: Introduce XTheadVector as a subset of V1.0.0
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt: Add new mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.
Co-authored-by: Jin Ma <jinma@linux.alibaba.com>
Co-authored-by: Xianmiao Qu <cooper.qu@linux.alibaba.com>
Co-authored-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv-c.cc | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 2 |
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index ba60cd8..422ddc2 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) riscv_ext_version_value (0, 11)); } + if (TARGET_XTHEADVECTOR) + builtin_define_with_int_value ("__riscv_th_v_intrinsic", + riscv_ext_version_value (0, 11)); + /* Define architecture extension test macros. */ builtin_define_with_int_value ("__riscv_arch_test", 1); @@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *) { if (!TARGET_VECTOR) { - error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension " - "enabled", + error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or " + "'XTHEADVECTOR' extension enabled", name); return; } diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 27e2f31..65c6562 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) Mask(XTHEADSYNC) Var(riscv_xthead_subext) +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) + TargetVariable int riscv_xventana_subext |