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authorChung-Lin Tang <cltang@codesourcery.com>2011-01-26 03:01:44 +0000
committerChung-Lin Tang <cltang@gcc.gnu.org>2011-01-26 03:01:44 +0000
commitbff9926229ee486205f66e0434fecb26846df590 (patch)
treef2095a0bd1a83bd7813461fad725197e20e9faf6 /gcc/config
parent82c039077c746cbc331044b48ef9a83754d0de31 (diff)
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re PR target/47246 (Invalid immediate offset for Thumb VFP store regression)
2011-01-26 Chung-Lin Tang <cltang@codesourcery.com> PR target/47246 * config/arm/arm.c (thumb2_legitimate_index_p): Change the lower bound of the allowed Thumb-2 coprocessor load/store index range to -256. Add explaining comment. From-SVN: r169271
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/arm/arm.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index be09282..b93756a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -5786,7 +5786,11 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
&& (mode == SFmode || mode == DFmode
|| (TARGET_MAVERICK && mode == DImode)))
return (code == CONST_INT && INTVAL (index) < 1024
- && INTVAL (index) > -1024
+ /* Thumb-2 allows only > -256 index range for it's core register
+ load/stores. Since we allow SF/DF in core registers, we have
+ to use the intersection between -256~4096 (core) and -1024~1024
+ (coprocessor). */
+ && INTVAL (index) > -256
&& (INTVAL (index) & 3) == 0);
if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))