diff options
| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-01-14 17:48:52 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-01-14 17:48:52 +0000 |
| commit | a50344cbf3ba75fd3ff5b089b46f58e7050290ee (patch) | |
| tree | a31593ca724cb447cd76efe385df1feb7021c59e /gcc/config | |
| parent | e6f0e05240317c022d19de26508730b9b7d81299 (diff) | |
| download | gcc-a50344cbf3ba75fd3ff5b089b46f58e7050290ee.zip gcc-a50344cbf3ba75fd3ff5b089b46f58e7050290ee.tar.gz gcc-a50344cbf3ba75fd3ff5b089b46f58e7050290ee.tar.bz2 | |
aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
2013-01-14 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
* config/aarch64/iterators.md (VALLDI): New.
testsuite/
* gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
* gcc.target/aarch64/vect-ld1r-compile.c: New.
* gcc.target/aarch64/vect-ld1r-fp.c: New.
* gcc.target/aarch64/vect-ld1r.c: New.
* gcc.target/aarch64/vect-ld1r.x: New.
From-SVN: r195158
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 3 |
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index fb12195..50297a9 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3559,3 +3559,11 @@ DONE; }) +(define_insn "*aarch64_simd_ld1r<mode>" + [(set (match_operand:VALLDI 0 "register_operand" "=w") + (vec_duplicate:VALLDI + (match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))] + "TARGET_SIMD" + "ld1r\\t{%0.<Vtype>}, %1" + [(set_attr "simd_type" "simd_load1r") + (set_attr "simd_mode" "<MODE>")]) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index f23403f..3a57494 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -89,6 +89,9 @@ ;; All modes. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) +;; All vector modes and DI. +(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) + ;; Vector modes for Integer reduction across lanes. (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI]) |