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| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2007-09-16 09:45:36 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2007-09-16 09:45:36 +0000 |
| commit | 7ed67b7abae8aaed529137bad7a3c5ec3200160c (patch) | |
| tree | 18aebc9c7d43f35fba7f765611aa3325b381a6a4 /gcc/config | |
| parent | 0dc3178264d389a4b65b9b9def5e7ff308ac086c (diff) | |
| download | gcc-7ed67b7abae8aaed529137bad7a3c5ec3200160c.zip gcc-7ed67b7abae8aaed529137bad7a3c5ec3200160c.tar.gz gcc-7ed67b7abae8aaed529137bad7a3c5ec3200160c.tar.bz2 | |
mips.md (SHORT): Fix long line.
gcc/
* config/mips/mips.md (SHORT): Fix long line.
(SUBDI): New mode iterator. Extend the shift-and-truncate insns
to QImode and HImoe.
gcc/testsuite/
* gcc.target/mips/truncate-1.c: New test.
From-SVN: r128525
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips.md | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 842fa08..32a401c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -481,10 +481,13 @@ ;; conditional-move-type condition is needed. (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")]) -;; This mode iterator allows the QI and HI extension patterns to be defined from -;; the same template. +;; This mode iterator allows the QI and HI extension patterns to be +;; defined from the same template. (define_mode_iterator SHORT [QI HI]) +;; Likewise the 64-bit truncate-and-shift patterns. +(define_mode_iterator SUBDI [QI HI SI]) + ;; This mode iterator allows :ANYF to be used wherever a scalar or vector ;; floating-point mode is allowed. (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") @@ -2314,19 +2317,20 @@ ;; Combiner patterns to optimize shift/truncate combinations. (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (truncate:SI + [(set (match_operand:SUBDI 0 "register_operand" "=d") + (truncate:SUBDI (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "const_arith_operand" ""))))] + (match_operand:DI 2 "const_arith_operand" ""))))] "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32" "dsra\t%0,%1,%2" [(set_attr "type" "shift") (set_attr "mode" "SI")]) (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") - (const_int 32))))] + [(set (match_operand:SUBDI 0 "register_operand" "=d") + (truncate:SUBDI + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") + (const_int 32))))] "TARGET_64BIT && !TARGET_MIPS16" "dsra\t%0,%1,32" [(set_attr "type" "shift") |