Reapply reverted change:

gcc/ada/
	Reapply reverted change:

        2007-09-06  Eric Botcazou  <ebotcazou@adacore.com>

        * trans.c (convert_with_check): Update call to real_2expN.

gcc/
	config/m68k/m68k.c (floating_exact_log2): Update call to real_2expN.
	config/s390/s390.md (fixuns_trunc<BFP:mode><GPR:mode>2): Ditto.

	Reapply reverted changes:

 	2007-09-06  Jan Hubicka  <jh@suse.cz>
 
	* config/i386.c (ix86_expand_lround, ix86_expand_round): Update call of
	real_2expN.

	2007-09-06  Richard Sandiford  <richard@codesourcery.com>

	* config/mips/mips.md (fixuns_truncdfsi2, fixuns_truncdfdi2)
	(fixuns_truncsfsi2, fixuns_truncsfdi2): Update calls to real_2expN.

	2007-09-05  Janis Johnson  <janis187@us.ibm.com>

	* optabs.c (expand_float): Convert unsigned integer as signed only
	if it provides sufficient accuracy; add mode argument to real_2expN.
	(expand_fix): Fix comment typos; extend binary float into mode
	wider than destination for converion to unsigned integer; add mode
	argument to real_2expN.
	* real.c (real_2expN): Add mode argument to special-case decimal
	float values.
	* real.h (real_2expN): Ditto.
	* fixed-value.c (check_real_for_fixed_mode): Add mode argument to
	real_2expN.
	(fixed_from_string): Ditto.
	(fixed_to_decimal): Ditto.
	(fixed_convert_from_real): Ditto.
	(real_convert_from_fixed): Ditto.
	* config/rs6000/rs6000.md (FP): Include DD and TD modes.
	* config/rs6000/dfp.md (extendddtd2, adddd3, addtd3, subdd3, subtd3,
	muldd3, multd3, divdd3, divtd3, cmpdd_internal1, cmptd_internal1,
	floatditd2, ftruncdd2, fixdddi2, ftrunctd2, fixddi2): New.

From-SVN: r128247

6 files changed, 160 insertions, 10 deletions

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index dba72df..f6f80a0 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -23144,7 +23144,7 @@ ix86_expand_lround (rtx op0, rtx op1)
 
   /* load nextafter (0.5, 0.0) */
   fmt = REAL_MODE_FORMAT (mode);
-  real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
+  real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
   REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
 
   /* adj = copysign (0.5, op1) */
@@ -23555,7 +23555,7 @@ ix86_expand_round (rtx operand0, rtx operand1)
 
   /* load nextafter (0.5, 0.0) */
   fmt = REAL_MODE_FORMAT (mode);
-  real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
+  real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
   REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
 
   /* xa = xa + 0.5 */
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 76d765e..cd7f493 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -3571,7 +3571,7 @@ floating_exact_log2 (rtx x)
     return 0;
 
   exp = real_exponent (&r);
-  real_2expN (&r1, exp);
+  real_2expN (&r1, exp, DFmode);
   if (REAL_VALUES_EQUAL (r1, r))
     return exp;
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 2006f92..76dde25 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2805,7 +2805,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 31);
+  real_2expN (&offset, 31, DFmode);
 
   if (reg1)			/* Turn off complaints about unreached code.  */
     {
@@ -2850,7 +2850,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 63);
+  real_2expN (&offset, 63, DFmode);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
   do_pending_stack_adjust ();
@@ -2892,7 +2892,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 31);
+  real_2expN (&offset, 31, SFmode);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
   do_pending_stack_adjust ();
@@ -2934,7 +2934,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 63);
+  real_2expN (&offset, 63, SFmode);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
   do_pending_stack_adjust ();
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 0bc405a..fa20f7d 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -405,3 +405,151 @@
 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
   [(set_attr "length" "8,8,8,20,20,16")])
 
+;; Hardware support for decimal floating point operations.
+
+(define_insn "extendddtd2"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dctqpq %0,%1"
+  [(set_attr "type" "fp")])
+
+;; The result of drdpq is an even/odd register pair with the converted
+;; value in the even register and zero in the odd register.
+;; FIXME: Avoid the register move by using a reload constraint to ensure
+;; that the result is the first of the pair receiving the result of drdpq.
+
+(define_insn "trunctddd2"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f")))
+   (clobber (match_scratch:TD 2 "=f"))]
+  "TARGET_DFP"
+  "drdpq %2,%1\;fmr %0,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "adddd3"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
+		 (match_operand:DD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dadd %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "addtd3"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
+		 (match_operand:TD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "daddq %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "subdd3"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(minus:DD (match_operand:DD 1 "gpc_reg_operand" "f")
+		  (match_operand:DD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dsub %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "subtd3"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(minus:TD (match_operand:TD 1 "gpc_reg_operand" "f")
+		  (match_operand:TD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dsubq %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "muldd3"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
+		 (match_operand:DD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dmul %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "multd3"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
+		 (match_operand:TD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dmulq %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "divdd3"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(div:DD (match_operand:DD 1 "gpc_reg_operand" "f")
+		(match_operand:DD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "ddiv %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "divtd3"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(div:TD (match_operand:TD 1 "gpc_reg_operand" "f")
+		(match_operand:TD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "ddivq %0,%1,%2"
+  [(set_attr "type" "fp")])
+
+(define_insn "*cmpdd_internal1"
+  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+	(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f")
+		      (match_operand:DD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dcmpu %0,%1,%2"
+  [(set_attr "type" "fpcompare")])
+
+(define_insn "*cmptd_internal1"
+  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+	(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f")
+		      (match_operand:TD 2 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dcmpuq %0,%1,%2"
+  [(set_attr "type" "fpcompare")])
+
+(define_insn "floatditd2"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dcffixq %0,%1"
+  [(set_attr "type" "fp")])
+
+;; Convert a decimal64 to a decimal64 whose value is an integer.
+;; This is the first stage of converting it to an integer type.
+
+(define_insn "ftruncdd2"
+  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
+	(fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "drintn. 0,%0,%1,1"
+  [(set_attr "type" "fp")])
+
+;; Convert a decimal64 whose value is an integer to an actual integer.
+;; This is the second stage of converting decimal float to integer type.
+
+(define_insn "fixdddi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+	(fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dctfix %0,%1"
+  [(set_attr "type" "fp")])
+
+;; Convert a decimal128 to a decimal128 whose value is an integer.
+;; This is the first stage of converting it to an integer type.
+
+(define_insn "ftrunctd2"
+  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
+	(fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "drintnq. 0,%0,%1,1"
+  [(set_attr "type" "fp")])
+
+;; Convert a decimal128 whose value is an integer to an actual integer.
+;; This is the second stage of converting decimal float to integer type.
+
+(define_insn "fixtddi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+	(fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))]
+  "TARGET_DFP"
+  "dctfixq %0,%1"
+  [(set_attr "type" "fp")])
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e3505d1..debacdc 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -204,7 +204,9 @@
   (TF "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT
    && (TARGET_FPRS || TARGET_E500_DOUBLE)
-   && TARGET_LONG_DOUBLE_128")])
+   && TARGET_LONG_DOUBLE_128")
+  (DD "TARGET_DFP")
+  (TD "TARGET_DFP")])
 
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 66cf561..b135033 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3295,8 +3295,8 @@
   REAL_VALUE_TYPE cmp, sub;
   
   operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
-  real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
-  real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
+  real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:mode>mode);
+  real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:mode>mode);
   
   emit_insn (gen_cmp<BFP:mode> (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));