re PR target/56766 (Fails to combine (vec_select (vec_concat ...)) to (vec_merge ...))

	PR target/56776
	* config/i386/sse.md (*avx_addsubv4df3_1): New insn pattern.
	(*avx_addsubv4df3_1s): Ditto.
	(*sse3_addsubv2df3_1): Ditto.
	(*sse3_addsubv2df3_1s): Ditto.
	(*avx_addsubv8sf3_1): Ditto.
	(*avx_addsubv8sf3_1s): Ditto.
	(*sse3_addsubv4sf3_1): Ditto.
	(*sse3_addsubv4sf3_1s): Ditto.

testsuite/ChangeLog:

	PR target/56776
	* gcc.target/i386/pr56776-1.c: New test.
	* gcc.target/i386/pr56776-2.c: Ditto.

From-SVN: r224527

1 files changed, 146 insertions, 0 deletions

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4ef51d6..d1277ca 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2032,6 +2032,38 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4DF")])
 
+(define_insn "*avx_addsubv4df3_1"
+  [(set (match_operand:V4DF 0 "register_operand" "=x")
+  	(vec_select:V4DF
+	  (vec_concat:V8DF
+	    (minus:V4DF
+	      (match_operand:V4DF 1 "register_operand" "x")
+	      (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
+	    (plus:V4DF (match_dup 1) (match_dup 2)))
+	  (parallel [(const_int 0) (const_int 5)
+		     (const_int 2) (const_int 7)])))]
+  "TARGET_AVX"
+  "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V4DF")])
+
+(define_insn "*avx_addsubv4df3_1s"
+  [(set (match_operand:V4DF 0 "register_operand" "=x")
+  	(vec_select:V4DF
+	  (vec_concat:V8DF
+	    (minus:V4DF
+	      (match_operand:V4DF 1 "register_operand" "x")
+	      (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
+	    (plus:V4DF (match_dup 2) (match_dup 1)))
+	  (parallel [(const_int 0) (const_int 5)
+		     (const_int 2) (const_int 7)])))]
+  "TARGET_AVX"
+  "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V4DF")])
+
 (define_insn "sse3_addsubv2df3"
   [(set (match_operand:V2DF 0 "register_operand" "=x,x")
 	(vec_merge:V2DF
@@ -2050,6 +2082,44 @@
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "V2DF")])
 
+(define_insn "*sse3_addsubv2df3_1"
+  [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+	(vec_select:V2DF
+	  (vec_concat:V4DF
+	    (minus:V2DF
+	      (match_operand:V2DF 1 "register_operand" "0,x")
+	      (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm"))
+	    (plus:V2DF (match_dup 1) (match_dup 2)))
+	  (parallel [(const_int 0) (const_int 3)])))]
+  "TARGET_SSE3"
+  "@
+   addsubpd\t{%2, %0|%0, %2}
+   vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseadd")
+   (set_attr "atom_unit" "complex")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "V2DF")])
+
+(define_insn "*sse3_addsubv2df3_1s"
+  [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+	(vec_select:V2DF
+	  (vec_concat:V4DF
+	    (minus:V2DF
+	      (match_operand:V2DF 1 "register_operand" "0,x")
+	      (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm"))
+	    (plus:V2DF (match_dup 2) (match_dup 1)))
+	  (parallel [(const_int 0) (const_int 3)])))]
+  "TARGET_SSE3"
+  "@
+   addsubpd\t{%2, %0|%0, %2}
+   vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseadd")
+   (set_attr "atom_unit" "complex")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "V2DF")])
+
 (define_insn "avx_addsubv8sf3"
   [(set (match_operand:V8SF 0 "register_operand" "=x")
 	(vec_merge:V8SF
@@ -2064,6 +2134,42 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
+(define_insn "*avx_addsubv8sf3_1"
+  [(set (match_operand:V8SF 0 "register_operand" "=x")
+	(vec_select:V8SF
+	  (vec_concat:V16SF
+	    (minus:V8SF
+	      (match_operand:V8SF 1 "register_operand" "x")
+	      (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
+	    (plus:V8SF (match_dup 1) (match_dup 2)))
+	  (parallel [(const_int 0) (const_int 9)
+		     (const_int 2) (const_int 11)
+		     (const_int 4) (const_int 13)
+		     (const_int 6) (const_int 15)])))]
+  "TARGET_AVX"
+  "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V8SF")])
+
+(define_insn "*avx_addsubv8sf3_1s"
+  [(set (match_operand:V8SF 0 "register_operand" "=x")
+	(vec_select:V8SF
+	  (vec_concat:V16SF
+	    (minus:V8SF
+	      (match_operand:V8SF 1 "register_operand" "x")
+	      (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
+	    (plus:V8SF (match_dup 2) (match_dup 1)))
+	  (parallel [(const_int 0) (const_int 9)
+		     (const_int 2) (const_int 11)
+		     (const_int 4) (const_int 13)
+		     (const_int 6) (const_int 15)])))]
+  "TARGET_AVX"
+  "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "type" "sseadd")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V8SF")])
+
 (define_insn "sse3_addsubv4sf3"
   [(set (match_operand:V4SF 0 "register_operand" "=x,x")
 	(vec_merge:V4SF
@@ -2082,6 +2188,46 @@
    (set_attr "prefix_rep" "1,*")
    (set_attr "mode" "V4SF")])
 
+(define_insn "*sse3_addsubv4sf3_1"
+  [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+	(vec_select:V4SF
+	  (vec_concat:V8SF
+	    (minus:V4SF
+	      (match_operand:V4SF 1 "register_operand" "0,x")
+	      (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
+	    (plus:V4SF (match_dup 1) (match_dup 2)))
+	  (parallel [(const_int 0) (const_int 5)
+		     (const_int 2) (const_int 7)])))]
+  "TARGET_SSE3"
+  "@
+   addsubps\t{%2, %0|%0, %2}
+   vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseadd")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_rep" "1,*")
+   (set_attr "mode" "V4SF")])
+
+(define_insn "*sse3_addsubv4sf3_1s"
+  [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+	(vec_select:V4SF
+	  (vec_concat:V8SF
+	    (minus:V4SF
+	      (match_operand:V4SF 1 "register_operand" "0,x")
+	      (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm"))
+	    (plus:V4SF (match_dup 2) (match_dup 1)))
+	  (parallel [(const_int 0) (const_int 5)
+		     (const_int 2) (const_int 7)])))]
+  "TARGET_SSE3"
+  "@
+   addsubps\t{%2, %0|%0, %2}
+   vaddsubps\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseadd")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_rep" "1,*")
+   (set_attr "mode" "V4SF")])
+
 (define_insn "avx_h<plusminus_insn>v4df3"
   [(set (match_operand:V4DF 0 "register_operand" "=x")
 	(vec_concat:V4DF