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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2014-09-09 11:20:02 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2014-09-09 11:20:02 +0000 |
| commit | 436c249d4410d7a0fe6be16d7cedf0826856ded8 (patch) | |
| tree | 32e09a82b61f38f6219a860cc9034393defa2490 /gcc/config | |
| parent | 35cb3e53878eefd7ea817613ffbe6ab84502f92e (diff) | |
| download | gcc-436c249d4410d7a0fe6be16d7cedf0826856ded8.zip gcc-436c249d4410d7a0fe6be16d7cedf0826856ded8.tar.gz gcc-436c249d4410d7a0fe6be16d7cedf0826856ded8.tar.bz2 | |
[ARM][2/7] Convert FP mnemonics to UAL | add/sub/div/abs patterns.
* config/arm/vfp.md (*abssf2_vfp): Use UAL assembly syntax.
(*absdf2_vfp): Likewise.
(*negsf2_vfp): Likewise.
(*negdf2_vfp): Likewise.
(*addsf3_vfp): Likewise.
(*adddf3_vfp): Likewise.
(*subsf3_vfp): Likewise.
(*subdf3_vfp): Likewise.
(*divsf3_vfp): Likewise.
(*divdf3_vfp): Likewise.
* gcc.target/arm/vfp-1.c: Updated expected assembly.
From-SVN: r215051
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/vfp.md | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index c14f8e4..755229c 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -588,7 +588,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=t") (abs:SF (match_operand:SF 1 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fabss%?\\t%0, %1" + "vabs%?.f32\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "ffariths")] @@ -598,7 +598,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=w") (abs:DF (match_operand:DF 1 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fabsd%?\\t%P0, %P1" + "vabs%?.f64\\t%P0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "ffarithd")] @@ -609,7 +609,7 @@ (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" "@ - fnegs%?\\t%0, %1 + vneg%?.f32\\t%0, %1 eor%?\\t%0, %1, #-2147483648" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") @@ -621,7 +621,7 @@ (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "@ - fnegd%?\\t%P0, %P1 + vneg%?.f64\\t%P0, %P1 # #" "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed @@ -671,7 +671,7 @@ (plus:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fadds%?\\t%0, %1, %2" + "vadd%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] @@ -682,7 +682,7 @@ (plus:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "faddd%?\\t%P0, %P1, %P2" + "vadd%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] @@ -694,7 +694,7 @@ (minus:SF (match_operand:SF 1 "s_register_operand" "t") (match_operand:SF 2 "s_register_operand" "t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fsubs%?\\t%0, %1, %2" + "vsub%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] @@ -705,7 +705,7 @@ (minus:DF (match_operand:DF 1 "s_register_operand" "w") (match_operand:DF 2 "s_register_operand" "w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fsubd%?\\t%P0, %P1, %P2" + "vsub%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] @@ -722,7 +722,7 @@ (div:SF (match_operand:SF 1 "s_register_operand" "t,t") (match_operand:SF 2 "s_register_operand" "t,t")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" - "fdivs%?\\t%0, %1, %2" + "vdiv%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") @@ -734,7 +734,7 @@ (div:DF (match_operand:DF 1 "s_register_operand" "w,w") (match_operand:DF 2 "s_register_operand" "w,w")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" - "fdivd%?\\t%P0, %P1, %P2" + "vdiv%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") |