md.texi (Iterators): Renamed from Macros.

	* doc/md.texi (Iterators): Renamed from Macros.  All contents
	changed to reflect rename of respectively define_code_macro and
	define_mode_macro to define_code_iterator and define_mode_iterator.
	(Mode Iterators, Code Iterators): Similar.
	* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
	(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
	(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
	(initialize_iterators, find_iterator, check_code_iterator)
	(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
	(read_mapping, read_rtx_1): Similar.
	* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
	config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
	config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
	config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
	config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
	config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
	config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
	config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
	config/rs6000/sync.md, config/rs6000/rs6000.md,
	config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
	config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
	config/vax/vax.md, config/bfin/bfin.md: Similar.

From-SVN: r127715

34 files changed, 244 insertions, 245 deletions

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index c743e71..f381dde 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -88,12 +88,12 @@
 
 ;; On non-BWX targets, CQImode must be handled the similarly to HImode
 ;; when generating reloads.
-(define_mode_macro RELOAD12 [QI HI CQI])
+(define_mode_iterator RELOAD12 [QI HI CQI])
 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
 
-;; Other mode macros
-(define_mode_macro I12MODE [QI HI])
-(define_mode_macro I48MODE [SI DI])
+;; Other mode iterators
+(define_mode_iterator I12MODE [QI HI])
+(define_mode_iterator I48MODE [SI DI])
 (define_mode_attr modesuffix [(SI "l") (DI "q")])
 
 ;; Where necessary, the suffixes _le and _be are used to distinguish between
@@ -6253,7 +6253,7 @@
 
 ;; Vector operations
 
-(define_mode_macro VEC [V8QI V4HI V2SI])
+(define_mode_iterator VEC [V8QI V4HI V2SI])
 
 (define_expand "mov<mode>"
   [(set (match_operand:VEC 0 "nonimmediate_operand" "")
diff --git a/gcc/config/alpha/sync.md b/gcc/config/alpha/sync.md
index b9ed6a0..5c0d284 100644
--- a/gcc/config/alpha/sync.md
+++ b/gcc/config/alpha/sync.md
@@ -17,7 +17,7 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_code_macro FETCHOP [plus minus ior xor and])
+(define_code_iterator FETCHOP [plus minus ior xor and])
 (define_code_attr fetchop_name
   [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
 (define_code_attr fetchop_pred
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 88c3ac4..4a63cfe 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -309,12 +309,12 @@
 (define_attr "ce_count" "" (const_int 1))
 
 ;;---------------------------------------------------------------------------
-;; Mode macros
+;; Mode iterators
 
 ; A list of modes that are exactly 64 bits in size.  We use this to expand
 ; some splits that are the same for all modes when operating on ARM 
 ; registers.
-(define_mode_macro ANY64 [DI DF V8QI V4HI V2SI V2SF])
+(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
 
 ;;---------------------------------------------------------------------------
 ;; Predicates
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
index 31aaf0f..1118873 100644
--- a/gcc/config/arm/iwmmxt.md
+++ b/gcc/config/arm/iwmmxt.md
@@ -20,10 +20,10 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;; Integer element sizes implemented by IWMMXT.
-(define_mode_macro VMMX [V2SI V4HI V8QI])
+(define_mode_iterator VMMX [V2SI V4HI V8QI])
 
 ;; Integer element sizes for shifts.
-(define_mode_macro VSHFT [V4HI V2SI DI])
+(define_mode_iterator VSHFT [V4HI V2SI DI])
 
 ;; Determine element size suffix from vector mode.
 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index fa5b16f..167367c 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -162,97 +162,97 @@
    (UNSPEC_VZIP2		204)])
 
 ;; Double-width vector modes.
-(define_mode_macro VD [V8QI V4HI V2SI V2SF])
+(define_mode_iterator VD [V8QI V4HI V2SI V2SF])
 
 ;; Double-width vector modes plus 64-bit elements.
-(define_mode_macro VDX [V8QI V4HI V2SI V2SF DI])
+(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI])
 
 ;; Same, without floating-point elements.
-(define_mode_macro VDI [V8QI V4HI V2SI])
+(define_mode_iterator VDI [V8QI V4HI V2SI])
 
 ;; Quad-width vector modes.
-(define_mode_macro VQ [V16QI V8HI V4SI V4SF])
+(define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
 
 ;; Quad-width vector modes plus 64-bit elements.
-(define_mode_macro VQX [V16QI V8HI V4SI V4SF V2DI])
+(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI])
 
 ;; Same, without floating-point elements.
-(define_mode_macro VQI [V16QI V8HI V4SI])
+(define_mode_iterator VQI [V16QI V8HI V4SI])
 
 ;; Same, with TImode added, for moves.
-(define_mode_macro VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
+(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI])
 
 ;; Opaque structure types wider than TImode.
-(define_mode_macro VSTRUCT [EI OI CI XI])
+(define_mode_iterator VSTRUCT [EI OI CI XI])
 
 ;; Number of instructions needed to load/store struct elements. FIXME!
 (define_mode_attr V_slen [(EI "2") (OI "2") (CI "3") (XI "4")])
 
 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
-(define_mode_macro VTAB [TI EI OI])
+(define_mode_iterator VTAB [TI EI OI])
 
 ;; vtbl<n> suffix for above modes.
 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
 
 ;; Widenable modes.
-(define_mode_macro VW [V8QI V4HI V2SI])
+(define_mode_iterator VW [V8QI V4HI V2SI])
 
 ;; Narrowable modes.
-(define_mode_macro VN [V8HI V4SI V2DI])
+(define_mode_iterator VN [V8HI V4SI V2DI])
 
 ;; All supported vector modes (except singleton DImode).
-(define_mode_macro VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
+(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI])
 
 ;; All supported vector modes (except those with 64-bit integer elements).
-(define_mode_macro VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
+(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
 
 ;; Supported integer vector modes (not 64 bit elements).
-(define_mode_macro VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
+(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
 
 ;; Supported integer vector modes (not singleton DI)
-(define_mode_macro VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
+(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
 
 ;; Vector modes, including 64-bit integer elements.
-(define_mode_macro VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
+(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI])
 
 ;; Vector modes including 64-bit integer elements, but no floats.
-(define_mode_macro VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
+(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
 
 ;; Vector modes for float->int conversions.
-(define_mode_macro VCVTF [V2SF V4SF])
+(define_mode_iterator VCVTF [V2SF V4SF])
 
 ;; Vector modes form int->float conversions.
-(define_mode_macro VCVTI [V2SI V4SI])
+(define_mode_iterator VCVTI [V2SI V4SI])
 
 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
-(define_mode_macro VMD [V4HI V2SI V2SF])
+(define_mode_iterator VMD [V4HI V2SI V2SF])
 
 ;; Vector modes for quadword multiply-accumulate, etc. insns.
-(define_mode_macro VMQ [V8HI V4SI V4SF])
+(define_mode_iterator VMQ [V8HI V4SI V4SF])
 
 ;; Above modes combined.
-(define_mode_macro VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
+(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
 
 ;; As VMD, but integer modes only.
-(define_mode_macro VMDI [V4HI V2SI])
+(define_mode_iterator VMDI [V4HI V2SI])
 
 ;; As VMQ, but integer modes only.
-(define_mode_macro VMQI [V8HI V4SI])
+(define_mode_iterator VMQI [V8HI V4SI])
 
 ;; Above modes combined.
-(define_mode_macro VMDQI [V4HI V2SI V8HI V4SI])
+(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
 
 ;; Modes with 8-bit and 16-bit elements.
-(define_mode_macro VX [V8QI V4HI V16QI V8HI])
+(define_mode_iterator VX [V8QI V4HI V16QI V8HI])
 
 ;; Modes with 8-bit elements.
-(define_mode_macro VE [V8QI V16QI])
+(define_mode_iterator VE [V8QI V16QI])
 
 ;; Modes with 64-bit elements only.
-(define_mode_macro V64 [DI V2DI])
+(define_mode_iterator V64 [DI V2DI])
 
 ;; Modes with 32-bit elements only.
-(define_mode_macro V32 [V2SI V2SF V4SI V4SF])
+(define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
 
 ;; (Opposite) mode to convert to/from for above conversions.
 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
@@ -394,10 +394,10 @@
                           (DI   "ti") (V2DI  "oi")])
 
 ;; Operations on two halves of a quadword vector.
-(define_code_macro vqh_ops [plus smin smax umin umax])
+(define_code_iterator vqh_ops [plus smin smax umin umax])
 
 ;; Same, without unsigned variants (for use with *SFmode pattern).
-(define_code_macro vqhs_ops [plus smin smax])
+(define_code_iterator vqhs_ops [plus smin smax])
 
 ;; Assembler mnemonics for above codes.
 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index f963472..858d381 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -21,16 +21,16 @@
 ;; Vector Moves
 
 ;; All integer and float modes supported by Neon and IWMMXT.
-(define_mode_macro VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
+(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
 
 ;; All integer and float modes supported by Neon and IWMMXT, except V2DI.
-(define_mode_macro VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
+(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
 
 ;; All integer modes supported by Neon and IWMMXT
-(define_mode_macro VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
+(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
 
 ;; All integer modes supported by Neon and IWMMXT, except V2DI
-(define_mode_macro VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
+(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
 
 (define_expand "mov<mode>"
   [(set (match_operand:VALL 0 "nonimmediate_operand" "")
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 44ee683..e465cd5 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -875,7 +875,7 @@
 
 ;; DImode logical operations
 
-(define_code_macro any_logical [and ior xor])
+(define_code_iterator any_logical [and ior xor])
 (define_code_attr optab [(and "and")
 			 (ior "ior")
 			 (xor "xor")])
@@ -3544,7 +3544,7 @@
   [(set_attr "type" "dsp32")])
 
 
-(define_code_macro s_or_u [sign_extend zero_extend])
+(define_code_iterator s_or_u [sign_extend zero_extend])
 (define_code_attr su_optab [(sign_extend "mul")
 			    (zero_extend "umul")])
 (define_code_attr su_modifier [(sign_extend "IS")
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 4b3eddf..99003db 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -870,9 +870,8 @@ cris_print_operand (FILE *file, rtx x, int code)
 
     case 'e':
       /* Like 'E', but ignore state set by 'x'.  FIXME: Use code
-	 iterators ("code macros") and attributes in cris.md to avoid
-	 the need for %x and %E (and %e) and state passed between
-	 those modifiers.  */
+	 iterators and attributes in cris.md to avoid the need for %x
+	 and %E (and %e) and state passed between those modifiers.  */
       cris_output_insn_is_bound = 0;
       /* FALL THROUGH.  */
     case 'E':
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 3f414d7..f9b0e92 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -150,9 +150,9 @@
 ;; Iterator definitions.
 
 ;; For the "usual" pattern size alternatives.
-(define_mode_macro BWD [SI HI QI])
-(define_mode_macro WD [SI HI])
-(define_mode_macro BW [HI QI])
+(define_mode_iterator BWD [SI HI QI])
+(define_mode_iterator WD [SI HI])
+(define_mode_iterator BW [HI QI])
 (define_mode_attr S [(SI "HI") (HI "QI")])
 (define_mode_attr s [(SI "hi") (HI "qi")])
 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
@@ -160,19 +160,19 @@
 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
 
 ;; For the sign_extend+zero_extend variants.
-(define_code_macro szext [sign_extend zero_extend])
+(define_code_iterator szext [sign_extend zero_extend])
 (define_code_attr u [(sign_extend "") (zero_extend "u")])
 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
 
 ;; For the shift variants.
-(define_code_macro shift [ashiftrt lshiftrt ashift])
-(define_code_macro shiftrt [ashiftrt lshiftrt])
+(define_code_iterator shift [ashiftrt lshiftrt ashift])
+(define_code_iterator shiftrt [ashiftrt lshiftrt])
 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
 
-(define_code_macro ncond [eq ne gtu ltu geu leu])
-(define_code_macro ocond [gt le])
-(define_code_macro rcond [lt ge])
+(define_code_iterator ncond [eq ne gtu ltu geu leu])
+(define_code_iterator ocond [gt le])
+(define_code_iterator rcond [lt ge])
 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
 		      (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
diff --git a/gcc/config/crx/crx.md b/gcc/config/crx/crx.md
index 89c344e..b965554 100644
--- a/gcc/config/crx/crx.md
+++ b/gcc/config/crx/crx.md
@@ -73,12 +73,12 @@
 
 ;;  Mode Macro Definitions
 
-(define_mode_macro ALLMT [QI HI SI SF DI DF])
-(define_mode_macro CRXMM [QI HI SI SF])
-(define_mode_macro CRXIM [QI HI SI])
-(define_mode_macro DIDFM [DI DF])
-(define_mode_macro SISFM [SI SF])
-(define_mode_macro SHORT [QI HI])
+(define_mode_iterator ALLMT [QI HI SI SF DI DF])
+(define_mode_iterator CRXMM [QI HI SI SF])
+(define_mode_iterator CRXIM [QI HI SI])
+(define_mode_iterator DIDFM [DI DF])
+(define_mode_iterator SISFM [SI SF])
+(define_mode_iterator SHORT [QI HI])
 
 (define_mode_attr tIsa [(QI "b") (HI "w") (SI "d") (SF "d")])
 (define_mode_attr lImmArith [(QI "4") (HI "4") (SI "6")])
@@ -94,20 +94,20 @@
 
 ;;  Code Macro Definitions
 
-(define_code_macro sz_xtnd [sign_extend zero_extend])
+(define_code_iterator sz_xtnd [sign_extend zero_extend])
 (define_code_attr sIsa [(sign_extend "") (zero_extend "u")])
 (define_code_attr sPat [(sign_extend "s") (zero_extend "u")])
 (define_code_attr szPat [(sign_extend "") (zero_extend "zero_")])
 (define_code_attr szIsa [(sign_extend "s") (zero_extend "z")])
 
-(define_code_macro sh_oprnd [ashift ashiftrt lshiftrt])
+(define_code_iterator sh_oprnd [ashift ashiftrt lshiftrt])
 (define_code_attr shIsa [(ashift "ll") (ashiftrt "ra") (lshiftrt "rl")])
 (define_code_attr shPat [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
 
-(define_code_macro mima_oprnd [smax umax smin umin])
+(define_code_iterator mima_oprnd [smax umax smin umin])
 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")])
 
-(define_code_macro any_cond [eq ne gt gtu lt ltu ge geu le leu])
+(define_code_iterator any_cond [eq ne gt gtu lt ltu ge geu le leu])
 
 ;;  Addition Instructions
 
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index 7c16293..f845174 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -86,7 +86,7 @@
    (FDPIC_REG			15)
    ])
 
-(define_mode_macro IMODE [QI HI SI DI])
+(define_mode_iterator IMODE [QI HI SI DI])
 (define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])
 (define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 751d46b..609e6d6 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -488,7 +488,7 @@
   [(set_attr "length" "128")
    (set_attr "type" "multi")])
 
-(define_code_macro plusminus [plus minus])
+(define_code_iterator plusminus [plus minus])
 
 ;; Base name for define_insn and insn mnemonic.
 (define_code_attr addsub [(plus "add") (minus "sub")])
@@ -497,7 +497,7 @@
 (define_code_attr comm [(plus "%") (minus "")])
 
 ;; All single word integer modes.
-(define_mode_macro SWI [QI HI SI (DI "TARGET_64BIT")])
+(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Instruction suffix for integer modes.
 (define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
@@ -516,22 +516,22 @@
 	 (DI "x86_64_general_operand")])
 
 ;; All x87 floating point modes
-(define_mode_macro X87MODEF [SF DF XF])
+(define_mode_iterator X87MODEF [SF DF XF])
 
 ;; x87 SFmode and DFMode floating point modes
-(define_mode_macro X87MODEF12 [SF DF])
+(define_mode_iterator X87MODEF12 [SF DF])
 
 ;; All integer modes handled by x87 fisttp operator.
-(define_mode_macro X87MODEI [HI SI DI])
+(define_mode_iterator X87MODEI [HI SI DI])
 
 ;; All integer modes handled by integer x87 operators.
-(define_mode_macro X87MODEI12 [HI SI])
+(define_mode_iterator X87MODEI12 [HI SI])
 
 ;; All SSE floating point modes
-(define_mode_macro SSEMODEF [SF DF])
+(define_mode_iterator SSEMODEF [SF DF])
 
 ;; All integer modes handled by SSE cvtts?2si* operators.
-(define_mode_macro SSEMODEI24 [SI DI])
+(define_mode_iterator SSEMODEI24 [SI DI])
 
 ;; SSE asm suffix for floating point modes
 (define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])
@@ -10085,7 +10085,7 @@
 
 ;; Copysign instructions
 
-(define_mode_macro CSGNMODE [SF DF TF])
+(define_mode_iterator CSGNMODE [SF DF TF])
 (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
 
 (define_expand "copysign<mode>3"
@@ -21009,7 +21009,7 @@
   }
   [(set_attr "type" "multi")])
 
-(define_mode_macro CRC32MODE [QI HI SI])
+(define_mode_iterator CRC32MODE [QI HI SI])
 (define_mode_attr crc32modesuffix [(QI "b") (HI "w") (SI "l")])
 (define_mode_attr crc32modeconstraint [(QI "qm") (HI "rm") (SI "rm")])
 
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6268d8f..70073de 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -31,14 +31,14 @@
 ;; direction of the user via a builtin.
 
 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
-(define_mode_macro MMXMODEI [V8QI V4HI V2SI])
+(define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
 
 ;; All 8-byte vector modes handled by MMX
-(define_mode_macro MMXMODE [V8QI V4HI V2SI V2SF])
+(define_mode_iterator MMXMODE [V8QI V4HI V2SI V2SF])
 
 ;; Mix-n-match
-(define_mode_macro MMXMODE12 [V8QI V4HI])
-(define_mode_macro MMXMODE24 [V4HI V2SI])
+(define_mode_iterator MMXMODE12 [V8QI V4HI])
+(define_mode_iterator MMXMODE24 [V4HI V2SI])
 
 ;; Mapping from integer vector mode to mnemonic suffix
 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (DI "q")])
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 72048ad..31fd293 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -21,17 +21,17 @@
 
 ;; 16 byte integral modes handled by SSE, minus TImode, which gets
 ;; special-cased for TARGET_64BIT.
-(define_mode_macro SSEMODEI [V16QI V8HI V4SI V2DI])
+(define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
 
 ;; All 16-byte vector modes handled by SSE
-(define_mode_macro SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
+(define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
 
 ;; Mix-n-match
-(define_mode_macro SSEMODE12 [V16QI V8HI])
-(define_mode_macro SSEMODE24 [V8HI V4SI])
-(define_mode_macro SSEMODE14 [V16QI V4SI])
-(define_mode_macro SSEMODE124 [V16QI V8HI V4SI])
-(define_mode_macro SSEMODE248 [V8HI V4SI V2DI])
+(define_mode_iterator SSEMODE12 [V16QI V8HI])
+(define_mode_iterator SSEMODE24 [V8HI V4SI])
+(define_mode_iterator SSEMODE14 [V16QI V4SI])
+(define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
+(define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
 
 ;; Mapping from integer vector mode to mnemonic suffix
 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 7282381..7530ab5 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -18,14 +18,14 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_mode_macro IMODE [QI HI SI (DI "TARGET_64BIT")])
+(define_mode_iterator IMODE [QI HI SI (DI "TARGET_64BIT")])
 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
 (define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
 (define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
 
-(define_mode_macro CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
+(define_mode_iterator CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
 			   (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
-(define_mode_macro DCASMODE
+(define_mode_iterator DCASMODE
   [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
    (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
 (define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md
index d26954b..a6547a6 100644
--- a/gcc/config/ia64/div.md
+++ b/gcc/config/ia64/div.md
@@ -158,7 +158,7 @@
 ;; to be written for RFmode only and to not have to handle multiple
 ;; modes or to have to handle a register in more than one mode.
 
-(define_mode_macro SDX_F [SF DF XF])
+(define_mode_iterator SDX_F [SF DF XF])
 
 (define_insn "extend<mode>rf2"
   [(set (match_operand:RF 0 "fr_register_operand" "=f")
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 2cbec72..52f26aa 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -385,8 +385,8 @@
 }
   [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
 
-(define_mode_macro MODE [BI QI HI SI DI SF DF XF TI])
-(define_mode_macro MODE_FOR_EXTEND [QI HI SI])
+(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
+(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
 
 (define_mode_attr output_a [
   (BI "ld1.a %0 = %1%P1")
diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md
index 9d99577..c467b0d 100644
--- a/gcc/config/ia64/sync.md
+++ b/gcc/config/ia64/sync.md
@@ -18,12 +18,12 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_mode_macro IMODE [QI HI SI DI])
-(define_mode_macro I124MODE [QI HI SI])
-(define_mode_macro I48MODE [SI DI])
+(define_mode_iterator IMODE [QI HI SI DI])
+(define_mode_iterator I124MODE [QI HI SI])
+(define_mode_iterator I48MODE [SI DI])
 (define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
 
-(define_code_macro FETCHOP [plus minus ior xor and])
+(define_code_iterator FETCHOP [plus minus ior xor and])
 (define_code_attr fetchop_name
   [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
 
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index bca5d8c..994ec90 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -20,9 +20,9 @@
 
 ;; Integer vector operations
 
-(define_mode_macro VECINT [V8QI V4HI V2SI])
-(define_mode_macro VECINT12 [V8QI V4HI])
-(define_mode_macro VECINT24 [V4HI V2SI])
+(define_mode_iterator VECINT [V8QI V4HI V2SI])
+(define_mode_iterator VECINT12 [V8QI V4HI])
+(define_mode_iterator VECINT24 [V4HI V2SI])
 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
 
 (define_expand "mov<mode>"
diff --git a/gcc/config/m32c/blkmov.md b/gcc/config/m32c/blkmov.md
index 17076b2..a734f71 100644
--- a/gcc/config/m32c/blkmov.md
+++ b/gcc/config/m32c/blkmov.md
@@ -51,7 +51,7 @@
   "if (m32c_expand_movmemhi(operands)) DONE; FAIL;"
   )
 
-;; We can't use mode macros for these because M16C uses r1h to extend
+;; We can't use mode iterators for these because M16C uses r1h to extend
 ;; the source address, for copying data from ROM to RAM.  We don't yet
 ;; support that, but we need to zero our r1h, so the patterns differ.
 
diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md
index 8110c0a..4bc4d05 100644
--- a/gcc/config/m32c/m32c.md
+++ b/gcc/config/m32c/m32c.md
@@ -54,15 +54,15 @@
 (define_attr "flags" "x,c,z,zc,s,sc,sz,szc,o,oc,oz,ozc,os,osc,osz,oszc,n" (const_string "n"))
 (define_asm_attributes [(set_attr "flags" "x")])
 
-(define_mode_macro QHI [QI HI])
-(define_mode_macro HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
-(define_mode_macro QHPSI [QI HI (PSI "TARGET_A24")])
-(define_mode_macro QHSI [QI HI (SI "TARGET_A24")])
+(define_mode_iterator QHI [QI HI])
+(define_mode_iterator HPSI [(HI "TARGET_A16") (PSI "TARGET_A24")])
+(define_mode_iterator QHPSI [QI HI (PSI "TARGET_A24")])
+(define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
 (define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
 
-(define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu])
-(define_code_macro eqne_cond [eq ne])
-(define_code_macro gl_cond [gt ge lt le gtu geu ltu leu])
+(define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu])
+(define_code_iterator eqne_cond [eq ne])
+(define_code_iterator gl_cond [gt ge lt le gtu geu ltu leu])
 
 
 
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 03f14fc..99ee142 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -138,7 +138,7 @@
 
 ;; Mode macros for floating point operations.
 ;; Valid floating point modes
-(define_mode_macro FP [SF DF (XF "TARGET_68881")])
+(define_mode_iterator FP [SF DF (XF "TARGET_68881")])
 ;; Mnemonic infix to round result
 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
 ;; Mnemonic infix to round result for mul or div instruction
diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md
index 3fdcc59..60b3a94 100644
--- a/gcc/config/mips/mips-dsp.md
+++ b/gcc/config/mips/mips-dsp.md
@@ -6,18 +6,18 @@
    (CCDSP_CC_REGNUM	186)
    (CCDSP_EF_REGNUM	187)])
 
-;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE.
-(define_mode_macro DSP [(SI "TARGET_DSP")
-			(V2HI "TARGET_DSP")
-		 	(V4QI "TARGET_DSP")])
-
-;; This mode macro allows v2hi, v4qi for vector/SIMD data.
-(define_mode_macro DSPV [(V2HI "TARGET_DSP")
-			 (V4QI "TARGET_DSP")])
-
-;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data.
-(define_mode_macro DSPQ [(SI "TARGET_DSP")
-		         (V2HI "TARGET_DSP")])
+;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
+(define_mode_iterator DSP [(SI "TARGET_DSP")
+			   (V2HI "TARGET_DSP")
+		 	   (V4QI "TARGET_DSP")])
+
+;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
+(define_mode_iterator DSPV [(V2HI "TARGET_DSP")
+			    (V4QI "TARGET_DSP")])
+
+;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
+(define_mode_iterator DSPQ [(SI "TARGET_DSP")
+			    (V2HI "TARGET_DSP")])
 
 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index bac479f..44c3c9c 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -464,31 +464,31 @@
   [(set_attr "type" "multi")
    (set_attr "can_delay" "no")])
 
-;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
+;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
 ;; from the same template.
-(define_mode_macro GPR [SI (DI "TARGET_64BIT")])
+(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
 
-;; This mode macro allows :P to be used for patterns that operate on
+;; This mode iterator allows :P to be used for patterns that operate on
 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
 
-;; This mode macro allows :MOVECC to be used anywhere that a
+;; This mode iterator allows :MOVECC to be used anywhere that a
 ;; conditional-move-type condition is needed.
-(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
 
-;; This mode macro allows the QI and HI extension patterns to be defined from
+;; This mode iterator allows the QI and HI extension patterns to be defined from
 ;; the same template.
-(define_mode_macro SHORT [QI HI])
+(define_mode_iterator SHORT [QI HI])
 
-;; This mode macro allows :ANYF to be used wherever a scalar or vector
+;; This mode iterator allows :ANYF to be used wherever a scalar or vector
 ;; floating-point mode is allowed.
-(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
-			 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
-			 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
+			    (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+			    (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
 
 ;; Like ANYF, but only applies to scalar modes.
-(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
-			    (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
+			       (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
 
 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
 ;; 32-bit version and "dsubu" in the 64-bit version.
@@ -545,26 +545,26 @@
 (define_mode_attr recip_condition
   [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
 
-;; This code macro allows all branch instructions to be generated from
+;; This code iterator allows all branch instructions to be generated from
 ;; a single define_expand template.
-(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
-			     eq ne gt ge lt le gtu geu ltu leu])
+(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
+			        eq ne gt ge lt le gtu geu ltu leu])
 
-;; This code macro allows signed and unsigned widening multiplications
+;; This code iterator allows signed and unsigned widening multiplications
 ;; to use the same template.
-(define_code_macro any_extend [sign_extend zero_extend])
+(define_code_iterator any_extend [sign_extend zero_extend])
 
-;; This code macro allows the three shift instructions to be generated
+;; This code iterator allows the three shift instructions to be generated
 ;; from the same template.
-(define_code_macro any_shift [ashift ashiftrt lshiftrt])
+(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
 
-;; This code macro allows all native floating-point comparisons to be
+;; This code iterator allows all native floating-point comparisons to be
 ;; generated from the same template.
-(define_code_macro fcond [unordered uneq unlt unle eq lt le])
+(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
 
-;; This code macro is used for comparisons that can be implemented
+;; This code iterator is used for comparisons that can be implemented
 ;; by swapping the operands.
-(define_code_macro swapped_fcond [ge gt unge ungt])
+(define_code_iterator swapped_fcond [ge gt unge ungt])
 
 ;; <u> expands to an empty string when doing a signed operation and
 ;; "u" when doing an unsigned operation.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 029874d..2261a93 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -162,13 +162,13 @@
   ])
 
 ;; Vec int modes
-(define_mode_macro VI [V4SI V8HI V16QI])
+(define_mode_iterator VI [V4SI V8HI V16QI])
 ;; Short vec in modes
-(define_mode_macro VIshort [V8HI V16QI])
+(define_mode_iterator VIshort [V8HI V16QI])
 ;; Vec float modes
-(define_mode_macro VF [V4SF])
-;; Vec modes, pity mode macros are not composable
-(define_mode_macro V [V4SI V8HI V16QI V4SF])
+(define_mode_iterator VF [V4SF])
+;; Vec modes, pity mode iterators are not composable
+(define_mode_iterator V [V4SI V8HI V16QI V4SF])
 
 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index be682c6..c9eccdd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -176,30 +176,30 @@
 (include "darwin.md")
 
 
-;; Mode macros
+;; Mode iterators
 
-; This mode macro allows :GPR to be used to indicate the allowable size
+; This mode iterator allows :GPR to be used to indicate the allowable size
 ; of whole values in GPRs.
-(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
+(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
 
 ; Any supported integer mode.
-(define_mode_macro INT [QI HI SI DI TI])
+(define_mode_iterator INT [QI HI SI DI TI])
 
 ; Any supported integer mode that fits in one register.
-(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
+(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
 
 ; extend modes for DImode
-(define_mode_macro QHSI [QI HI SI])
+(define_mode_iterator QHSI [QI HI SI])
 
 ; SImode or DImode, even if DImode doesn't fit in GPRs.
-(define_mode_macro SDI [SI DI])
+(define_mode_iterator SDI [SI DI])
 
 ; The size of a pointer.  Also, the size of the value that a record-condition
 ; (one with a '.') will compare.
-(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
+(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
 
 ; Any hardware-supported floating-point mode
-(define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
+(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
   (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
   (TF "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index d49c126..b7b2fef 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -36,13 +36,13 @@
    ])
 
 ;; Modes using a 64-bit register.
-(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
+(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
 
 ;; Likewise, but allow TFmode (two registers) as well.
-(define_mode_macro SPE64TF [DF V4HI V2SF V1DI V2SI TF])
+(define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
 
 ;; DImode and TImode.
-(define_mode_macro DITI [DI TI])
+(define_mode_iterator DITI [DI TI])
 
 (define_insn "*negsf2_gpr"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index 4573509..5839715 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -21,7 +21,7 @@
 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
 
-(define_code_macro FETCHOP [plus minus ior xor and])
+(define_code_iterator FETCHOP [plus minus ior xor and])
 (define_code_attr fetchop_name
   [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
 (define_code_attr fetchop_pred
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 3e5610b..e0e9edc 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -246,54 +246,54 @@
 ;; Other includes
 (include "tpf.md")
 
-;; Macros
+;; Iterators
 
-;; This mode macro allows floating point patterns to be generated from the
+;; These mode iterators allow floating point patterns to be generated from the
 ;; same template.
-(define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
-(define_mode_macro BFP [TF DF SF])
-(define_mode_macro DFP [TD DD])
-(define_mode_macro DFP_ALL [TD DD SD])
-(define_mode_macro DSF [DF SF])
-(define_mode_macro SD_SF [SF SD])
-(define_mode_macro DD_DF [DF DD])
-(define_mode_macro TD_TF [TF TD])
-
-;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
+(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
+(define_mode_iterator BFP [TF DF SF])
+(define_mode_iterator DFP [TD DD])
+(define_mode_iterator DFP_ALL [TD DD SD])
+(define_mode_iterator DSF [DF SF])
+(define_mode_iterator SD_SF [SF SD])
+(define_mode_iterator DD_DF [DF DD])
+(define_mode_iterator TD_TF [TF TD])
+
+;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
 ;; from the same template.
-(define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
+(define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
 
-;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
+;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
 ;; from the same template.
-(define_mode_macro GPR [(DI "TARGET_64BIT") SI])
-(define_mode_macro DSI [DI SI])
+(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator DSI [DI SI])
 
-;; This mode macro allows :P to be used for patterns that operate on
+;; These mode iterators allow :P to be used for patterns that operate on
 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
-(define_mode_macro DP  [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
-(define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+(define_mode_iterator DP  [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
+(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
 
-;; This mode macro allows the QI and HI patterns to be defined from
+;; This mode iterator allows the QI and HI patterns to be defined from
 ;; the same template.
-(define_mode_macro HQI [HI QI])
+(define_mode_iterator HQI [HI QI])
 
-;; This mode macro allows the integer patterns to be defined from the
+;; This mode iterator allows the integer patterns to be defined from the
 ;; same template.
-(define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
 
-;; This macro allows to unify all 'bCOND' expander patterns.
-(define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered 
+;; This iterator allows to unify all 'bCOND' expander patterns.
+(define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered 
 		            ordered uneq unlt ungt unle unge ltgt])
 
-;; This macro allows to unify all 'sCOND' patterns.
-(define_code_macro SCOND [ltu gtu leu geu])
+;; This iterator allows to unify all 'sCOND' patterns.
+(define_code_iterator SCOND [ltu gtu leu geu])
 
-;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
+;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
 ;; the same template.
-(define_code_macro SHIFT [ashift lshiftrt])
+(define_code_iterator SHIFT [ashift lshiftrt])
 
-;; These macros allow to combine most atomic operations.
-(define_code_macro ATOMIC [and ior xor plus minus mult])
+;; This iterator and attribute allow to combine most atomic operations.
+(define_code_iterator ATOMIC [and ior xor plus minus mult])
 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") 
 			  (plus "add") (minus "sub") (mult "nand")])
 
@@ -312,18 +312,18 @@
 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 
 ;; The decimal floating point variants of add, sub, div and mul support 3
-;; fp register operands.  The following macros allow to merge the bfp and
+;; fp register operands.  The following attributes allow to merge the bfp and
 ;; dfp variants in a single insn definition.
 
-;; This macro is used to set op_type accordingly.
+;; This attribute is used to set op_type accordingly.
 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") 
                         (DD "RRR") (SD "RRR")])
 
-;; This macro is used in the operand constraint list in order to have the 
+;; This attribute is used in the operand constraint list in order to have the 
 ;; first and the second operand match for bfp modes.
 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
 
-;; This macro is used in the operand list of the instruction to have an 
+;; This attribute is used in the operand list of the instruction to have an 
 ;; additional operand for the dfp instructions.
 (define_mode_attr op1 [(TF "") (DF "") (SF "")
                        (TD "%1,") (DD "%1,") (SD "%1,")])
@@ -341,7 +341,7 @@
 ;; This is used to disable the memory alternative in TFmode patterns.
 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
 
-;; This macro adds b for bfp instructions and t for dfp instructions and is used
+;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 ;; within instruction mnemonics.
 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
 
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 05370fc..329dd1a 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1701,7 +1701,7 @@
    (set_attr "branch_type" "reg")])
 
 
-(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
 
 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
 ;; value subject to a PC-relative relocation.  Operand 2 is a helper function
@@ -2340,7 +2340,7 @@
 ;; Floating point and vector move instructions
 
 ;; We don't define V1SI because SI should work just fine.
-(define_mode_macro V32 [SF V2HI V4QI])
+(define_mode_iterator V32 [SF V2HI V4QI])
 
 ;; Yes, you guessed it right, the former movsf expander.
 (define_expand "mov<V32:mode>"
@@ -2476,7 +2476,7 @@
   [(set (match_dup 0) (high:SF (match_dup 1)))
    (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
 
-(define_mode_macro V64 [DF V2SI V4HI V8QI])
+(define_mode_iterator V64 [DF V2SI V4HI V8QI])
 
 ;; Yes, you again guessed it right, the former movdf expander.
 (define_expand "mov<V64:mode>"
@@ -5276,8 +5276,8 @@
 ;; We define DImode `and' so with DImode `not' we can get
 ;; DImode `andn'.  Other combinations are possible.
 
-(define_mode_macro V64I [DI V2SI V4HI V8QI])
-(define_mode_macro V32I [SI V2HI V4QI])
+(define_mode_iterator V64I [DI V2SI V4HI V8QI])
+(define_mode_iterator V32I [SI V2HI V4QI])
 
 (define_expand "and<V64I:mode>3"
   [(set (match_operand:V64I 0 "register_operand" "")
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 05c85d9..17cf691 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -18,9 +18,9 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_mode_macro I12MODE [QI HI])
-(define_mode_macro I24MODE [HI SI])
-(define_mode_macro I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
+(define_mode_iterator I12MODE [QI HI])
+(define_mode_iterator I24MODE [HI SI])
+(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
 (define_mode_attr modesuffix [(SI "") (DI "x")])
 
 (define_expand "memory_barrier"
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 4f2c41a..5dcc45e 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -159,9 +159,9 @@
 (include "constraints.md")
 
 
-;; Mode macros
+;; Mode iterators
 
-(define_mode_macro ALL [QI V16QI
+(define_mode_iterator ALL [QI V16QI
 			HI V8HI
 			SI V4SI
 			DI V2DI
@@ -171,43 +171,43 @@
 
 ; Everything except DI and TI which are handled separately because
 ; they need different constraints to correctly test VOIDmode constants
-(define_mode_macro MOV [QI V16QI
+(define_mode_iterator MOV [QI V16QI
 			HI V8HI
 			SI V4SI
 			V2DI
                         SF V4SF
                         DF V2DF])
 
-(define_mode_macro DTI  [DI TI])
+(define_mode_iterator DTI  [DI TI])
 
-(define_mode_macro VINT [QI V16QI
+(define_mode_iterator VINT [QI V16QI
 			 HI V8HI
 			 SI V4SI
 			 DI V2DI
 			 TI])
 
-(define_mode_macro VQHSI [QI V16QI
+(define_mode_iterator VQHSI [QI V16QI
 			  HI V8HI
 			  SI V4SI])
 
-(define_mode_macro VHSI [HI V8HI
+(define_mode_iterator VHSI [HI V8HI
 			 SI V4SI])
 
-(define_mode_macro VSDF [SF V4SF
+(define_mode_iterator VSDF [SF V4SF
                          DF V2DF])
 
-(define_mode_macro VSI [SI V4SI])
-(define_mode_macro VDI [DI V2DI])
-(define_mode_macro VSF [SF V4SF])
-(define_mode_macro VDF [DF V2DF])
+(define_mode_iterator VSI [SI V4SI])
+(define_mode_iterator VDI [DI V2DI])
+(define_mode_iterator VSF [SF V4SF])
+(define_mode_iterator VDF [DF V2DF])
 
-(define_mode_macro VCMP [V16QI
+(define_mode_iterator VCMP [V16QI
 			 V8HI
 			 V4SI
                          V4SF
                          V2DF])
 
-(define_mode_macro VCMPU [V16QI
+(define_mode_iterator VCMPU [V16QI
 			  V8HI
 			  V4SI])
 
@@ -233,10 +233,10 @@
 		          (SI "G")  (V4SI "G")])
 
 ;; Used for carry and borrow instructions.
-(define_mode_macro CBOP  [SI DI V4SI V2DI])
+(define_mode_iterator CBOP  [SI DI V4SI V2DI])
 
 ;; Used in vec_set and vec_extract
-(define_mode_macro V [V2DI V4SI V8HI V16QI V2DF V4SF])
+(define_mode_iterator V [V2DI V4SI V8HI V16QI V2DF V4SF])
 (define_mode_attr inner  [(V16QI "QI")
 			  (V8HI  "HI")
 			  (V4SI  "SI")
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
index fd0597b..0bc05b4 100644
--- a/gcc/config/vax/vax.md
+++ b/gcc/config/vax/vax.md
@@ -42,11 +42,11 @@
 
 ;; Integer modes supported on VAX, with a mapping from machine mode
 ;; to mnemonic suffix.  DImode is always a special case.
-(define_mode_macro VAXint [QI HI SI])
+(define_mode_iterator VAXint [QI HI SI])
 (define_mode_attr  isfx [(QI "b") (HI "w") (SI "l")])
 
 ;; Similar for float modes supported on VAX.
-(define_mode_macro VAXfp [SF DF])
+(define_mode_iterator VAXfp [SF DF])
 (define_mode_attr  fsfx [(SF "f") (DF "%#")])
 
 ;; Some output patterns want integer immediates with a prefix...
@@ -1012,7 +1012,7 @@
   "jbr %l0")
 
 ;; Conditional jumps
-(define_code_macro any_cond [eq ne gt lt gtu ltu ge le geu leu])
+(define_code_iterator any_cond [eq ne gt lt gtu ltu ge le geu leu])
 
 (define_insn "b<code>"
   [(set (pc)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 2dd6843..2f47540 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -37,9 +37,9 @@
   (UNSPECV_S32C1I	5)
 ])
 
-;; This code macro allows signed and unsigned widening multiplications
+;; This code iterator allows signed and unsigned widening multiplications
 ;; to use the same template.
-(define_code_macro any_extend [sign_extend zero_extend])
+(define_code_iterator any_extend [sign_extend zero_extend])
 
 ;; <u> expands to an empty string when doing a signed operation and
 ;; "u" when doing an unsigned operation.
@@ -48,32 +48,32 @@
 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
 
-;; This code macro allows four integer min/max operations to be
+;; This code iterator allows four integer min/max operations to be
 ;; generated from one template.
-(define_code_macro any_minmax [smin umin smax umax])
+(define_code_iterator any_minmax [smin umin smax umax])
 
 ;; <minmax> expands to the opcode name for any_minmax operations.
 (define_code_attr minmax [(smin "min") (umin "minu")
 			  (smax "max") (umax "maxu")])
 
-;; This code macro allows all branch instructions to be generated from
+;; This code iterator allows all branch instructions to be generated from
 ;; a single define_expand template.
-(define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu])
+(define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu])
 
-;; This code macro is for setting a register from a comparison.
-(define_code_macro any_scc [eq ne gt ge lt le])
+;; This code iterator is for setting a register from a comparison.
+(define_code_iterator any_scc [eq ne gt ge lt le])
 
-;; This code macro is for floating-point comparisons.
-(define_code_macro any_scc_sf [eq lt le])
+;; This code iterator is for floating-point comparisons.
+(define_code_iterator any_scc_sf [eq lt le])
 
-;; These macros allow to combine most atomic operations.
-(define_code_macro ATOMIC [and ior xor plus minus mult])
+;; This iterator and attribute allow to combine most atomic operations.
+(define_code_iterator ATOMIC [and ior xor plus minus mult])
 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") 
 			  (plus "add") (minus "sub") (mult "nand")])
 
-;; These mode macros allow the HI and QI patterns to be defined from
+;; This mode iterator allows the HI and QI patterns to be defined from
 ;; the same template.
-(define_mode_macro HQI [HI QI])
+(define_mode_iterator HQI [HI QI])
 
 
 ;; Attributes.