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authorH.J. Lu <hongjiu.lu@intel.com>2010-09-14 17:02:10 +0000
committerH.J. Lu <hjl@gcc.gnu.org>2010-09-14 10:02:10 -0700
commit26983c22532f0119ef77c5ad53e622a38a8de81f (patch)
tree234df070889197d6478e55b7ed00545077288920 /gcc/config
parentb93cf3427d41c321829356996b89836ad0dbe58b (diff)
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Turn UNITS_PER_SIMD_WORD into a target hook.
2010-09-14 H.J. Lu <hongjiu.lu@intel.com> * defaults.h (UNITS_PER_SIMD_WORD): Removed. * config/arm/arm.h (UNITS_PER_SIMD_WORD): Likewise. * config/i386/i386.h (UNITS_PER_SIMD_WORD): Likewise. * config/mips/mips.h (UNITS_PER_SIMD_WORD): Likewise. * config/rs6000/rs6000.h (UNITS_PER_SIMD_WORD): Likewise. * config/sparc/sparc.h (UNITS_PER_SIMD_WORD): Likewise. * target.def: Add units_per_simd_word to vectorize. * targhooks.c (default_units_per_simd_word): New. * targhooks.h (default_units_per_simd_word): Likewise. * config/arm/arm.c (arm_units_per_simd_word): Likewise. (TARGET_VECTORIZE_UNITS_PER_SIMD_WORD): Likewise. * config/mips/mips.c (mips_units_per_simd_word): Likewise. (TARGET_VECTORIZE_UNITS_PER_SIMD_WORD): Likewise. * config/rs6000/rs6000.c (rs6000_units_per_simd_word): Likewise. (TARGET_VECTORIZE_UNITS_PER_SIMD_WORD): Likewise. * config/sparc/sparc.c (sparc_units_per_simd_word): Likewise. (TARGET_VECTORIZE_UNITS_PER_SIMD_WORD): Likewise. * tree-vect-loop.c: Replace UNITS_PER_SIMD_WORD with TARGET_VECTORIZE_UNITS_PER_SIMD_WORD in comments. * tree-vect-stmts.c (get_vectype_for_scalar_type): Replace UNITS_PER_SIMD_WORD with targetm.vectorize.units_per_simd_word. * system.h (UNITS_PER_SIMD_WORD): Poisoned. * config/i386/i386-protos.h (ix86_units_per_simd_word): Removed. * config/i386/i386.c (ix86_units_per_simd_word): Make it static. (TARGET_VECTORIZE_UNITS_PER_SIMD_WORD): New. * doc/tm.texi.in: Remove UNITS_PER_SIMD_WORD. Add TARGET_VECTORIZE_UNITS_PER_SIMD_WORD. * doc/tm.texi: Regenerated. From-SVN: r164285
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/arm/arm.c14
-rw-r--r--gcc/config/arm/arm.h6
-rw-r--r--gcc/config/i386/i386-protos.h2
-rw-r--r--gcc/config/i386/i386.c5
-rw-r--r--gcc/config/i386/i386.h2
-rw-r--r--gcc/config/mips/mips.c11
-rw-r--r--gcc/config/mips/mips.h3
-rw-r--r--gcc/config/rs6000/rs6000.c12
-rw-r--r--gcc/config/rs6000/rs6000.h7
-rw-r--r--gcc/config/sparc/sparc.c12
-rw-r--r--gcc/config/sparc/sparc.h2
11 files changed, 53 insertions, 23 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 1d547b0..6f260ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -236,6 +236,7 @@ static rtx arm_trampoline_adjust_address (rtx);
static rtx arm_pic_static_addr (rtx orig, rtx reg);
static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
+static unsigned int arm_units_per_simd_word (enum machine_mode);
/* Table of machine attributes. */
@@ -363,6 +364,8 @@ static const struct attribute_spec arm_attribute_table[] =
#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
+#undef TARGET_VECTORIZE_UNITS_PER_SIMD_WORD
+#define TARGET_VECTORIZE_UNITS_PER_SIMD_WORD arm_units_per_simd_word
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
@@ -21869,6 +21872,17 @@ arm_vector_mode_supported_p (enum machine_mode mode)
return false;
}
+/* Use the option -mvectorize-with-neon-quad to override the use of doubleword
+ registers when autovectorizing for Neon, at least until multiple vector
+ widths are supported properly by the middle-end. */
+
+static unsigned int
+arm_units_per_simd_word (enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (TARGET_NEON
+ ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD);
+}
+
/* Implements target hook small_register_classes_for_mode_p. */
bool
arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 5b66510..36b618a 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -580,12 +580,6 @@ extern int arm_arch_hwdiv;
#define UNITS_PER_WORD 4
-/* Use the option -mvectorize-with-neon-quad to override the use of doubleword
- registers when autovectorizing for Neon, at least until multiple vector
- widths are supported properly by the middle-end. */
-#define UNITS_PER_SIMD_WORD(MODE) \
- (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
-
/* True if natural alignment is used for doubleword types. */
#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index fa88134..900b424 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -38,8 +38,6 @@ extern void ix86_output_addr_diff_elt (FILE *, int, int);
extern enum calling_abi ix86_cfun_abi (void);
extern enum calling_abi ix86_function_type_abi (const_tree);
-extern unsigned int ix86_units_per_simd_word (enum machine_mode);
-
#ifdef RTX_CODE
extern int standard_80387_constant_p (rtx);
extern const char *standard_80387_constant_opcode (rtx);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a1bc205..1d4e4ae 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -32341,7 +32341,7 @@ has_dispatch (rtx insn, int action)
/* ??? No autovectorization into MMX or 3DNOW until we can reliably
place emms and femms instructions. */
-unsigned int
+static unsigned int
ix86_units_per_simd_word (enum machine_mode mode)
{
/* Disable double precision vectorizer if needed. */
@@ -32609,6 +32609,9 @@ ix86_units_per_simd_word (enum machine_mode mode)
#undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
#define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
ix86_vectorize_builtin_vec_perm_ok
+#undef TARGET_VECTORIZE_UNITS_PER_SIMD_WORD
+#define TARGET_VECTORIZE_UNITS_PER_SIMD_WORD \
+ ix86_units_per_simd_word
#undef TARGET_SET_CURRENT_FUNCTION
#define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 6fc2249..fe48efd 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1033,8 +1033,6 @@ enum target_cpu_default
|| (MODE) == V2SImode || (MODE) == SImode \
|| (MODE) == V4HImode || (MODE) == V8QImode)
-#define UNITS_PER_SIMD_WORD(MODE) ix86_units_per_simd_word (MODE)
-
#define VALID_DFP_MODE_P(MODE) \
((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 20b63c7..945ee42 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -11140,6 +11140,14 @@ mips_scalar_mode_supported_p (enum machine_mode mode)
return default_scalar_mode_supported_p (mode);
}
+/* Implement TARGET_VECTORIZE_UNITS_PER_SIMD_WORD. */
+
+static bool
+mips_units_per_simd_word (enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD;
+}
+
/* Implement TARGET_INIT_LIBFUNCS. */
#include "config/gofast.h"
@@ -16506,6 +16514,9 @@ mips_shift_truncation_mask (enum machine_mode mode)
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
+#undef TARGET_VECTORIZE_UNITS_PER_SIMD_WORD
+#define TARGET_VECTORIZE_UNITS_PER_SIMD_WORD mips_units_per_simd_word
+
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS mips_init_builtins
#undef TARGET_EXPAND_BUILTIN
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 74bf3d25..4f44130 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1328,9 +1328,6 @@ enum mips_code_readable_setting {
/* The number of bytes in a double. */
#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
-#define UNITS_PER_SIMD_WORD(MODE) \
- (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
-
/* Set the sizes of the core types. */
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ab5da58..2ebe484 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3570,6 +3570,18 @@ rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
}
}
+/* Implement targetm.vectorize.units_per_simd_word. */
+
+static int
+rs6000_units_per_simd_word (enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return (TARGET_VSX ? UNITS_PER_VSX_WORD
+ : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD
+ : (TARGET_SPE ? UNITS_PER_SPE_WORD
+ : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD
+ : UNITS_PER_WORD))));
+}
+
/* Handle generic options of the form -mfoo=yes/no.
NAME is the option name.
VALUE is the option value.
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 63f1bba..5b0e4c7 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1150,13 +1150,6 @@ extern unsigned rs6000_pointer_size;
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
-#define UNITS_PER_SIMD_WORD(MODE) \
- (TARGET_VSX ? UNITS_PER_VSX_WORD \
- : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
- : (TARGET_SPE ? UNITS_PER_SPE_WORD \
- : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
- : UNITS_PER_WORD))))
-
/* Value is TRUE if hard register REGNO can hold a value of
machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index ba034e6..71c94e1 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -434,6 +434,7 @@ static bool sparc_can_eliminate (const int, const int);
static const char *sparc_mangle_type (const_tree);
#endif
static void sparc_trampoline_init (rtx, tree, rtx);
+static bool sparc_units_per_simd_word (enum machine_mode);
#ifdef SUBTARGET_ATTRIBUTE_TABLE
/* Table of valid machine attributes. */
@@ -571,6 +572,9 @@ static bool fpu_option_set = false;
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
+#undef TARGET_VECTORIZE_UNITS_PER_SIMD_WORD
+#define TARGET_VECTORIZE_UNITS_PER_SIMD_WORD sparc_units_per_simd_word
+
#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec
@@ -6233,6 +6237,14 @@ sparc_vector_mode_supported_p (enum machine_mode mode)
return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
}
+/* Implement the TARGET_VECTORIZE_UNITS_PER_SIMD_WORD target hook. */
+
+static bool
+sparc_units_per_simd_word (enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return TARGET_VIS ? 8 : UNITS_PER_WORD;
+}
+
/* Return the string to output an unconditional branch to LABEL, which is
the operand number of the label.
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index eae3959..21694eb 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -607,8 +607,6 @@ extern struct sparc_cpu_select sparc_select[];
#define MIN_UNITS_PER_WORD 4
#endif
-#define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD)
-
/* Now define the sizes of the C data types. */
#define SHORT_TYPE_SIZE 16