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| author | Eric Botcazou <ebotcazou@libertysurf.fr> | 2004-01-27 14:29:26 +0100 |
|---|---|---|
| committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2004-01-27 13:29:26 +0000 |
| commit | 1b4bda70e5c1fecb9fea6e2fc985f1dc61318f61 (patch) | |
| tree | 8612898897c739a2f1db954d9170d5f3ca646417 /gcc/config | |
| parent | 1194fc79773b7e3abcf36123c58995e1129315e2 (diff) | |
| download | gcc-1b4bda70e5c1fecb9fea6e2fc985f1dc61318f61.zip gcc-1b4bda70e5c1fecb9fea6e2fc985f1dc61318f61.tar.gz gcc-1b4bda70e5c1fecb9fea6e2fc985f1dc61318f61.tar.bz2 | |
re PR target/10904 (invalid (misaligned) FP register at -O2)
PR target/10904
PR target/13058
* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): New.
Forbid mode changes from SImode for lower FP regs if ARCH64.
From-SVN: r76702
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/sparc/sparc.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 06fd5ee..eeab3c6 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1264,6 +1264,20 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ {-1, -1, -1, 0x3f}} /* ALL_REGS */ +/* Defines invalid mode changes. Borrowed from pa64-regs.h. + + SImode loads to floating-point registers are not zero-extended. + The definition for LOAD_EXTEND_OP specifies that integer loads + narrower than BITS_PER_WORD will be zero-extended. As a result, + we inhibit changes from SImode unless they are to a mode that is + identical in size. */ + +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (TARGET_ARCH64 \ + && (FROM) == SImode \ + && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) + /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression |