bb-reorder.c, [...]: Fix comment typos.

	* bb-reorder.c, c-opts.c, cfglayout.c, cgraph.c, cgraphunit.c,
	cppfiles.c, fold-const.c, ggc-zone.c, loop-doloop.c, optabs.c,
	reg-stack.c, varasm.c, config/alpha/ev4.md,
	config/alpha/ev5.md, config/alpha/ev6.md, config/arm/arm.c,
	config/c4x/c4x.c, config/c4x/c4x.md, config/cris/cris.c,
	config/cris/cris.h, config/fr30/fr30.h, config/frv/frv.c,
	config/frv/frv.h, config/frv/frv.md, config/h8300/h8300.c,
	config/i386/i386.c, config/i386/i386.md, config/i386/winnt.c,
	config/ia64/itanium2.md, config/ip2k/ip2k.c,
	config/mips/mips.c, config/mips/mips.h, config/mips/sr71k.md,
	config/pa/pa.c, config/s390/s390.c, config/sh/sh.c: Fix
	comment typos.

From-SVN: r81345

24 files changed, 29 insertions, 29 deletions

diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md
index cee3ae6..5056fa1 100644
--- a/gcc/config/alpha/ev4.md
+++ b/gcc/config/alpha/ev4.md
@@ -98,7 +98,7 @@
   "ev4_ist"
   "store_data_bypass_p")
 
-; Multiplies use a non-piplined imul unit.  Also, "no [ebox] insn can
+; Multiplies use a non-pipelined imul unit.  Also, "no [ebox] insn can
 ; be issued exactly three cycles before an integer multiply completes".
 
 (define_insn_reservation "ev4_imulsi" 21
diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md
index 20757e1..ece25d7 100644
--- a/gcc/config/alpha/ev5.md
+++ b/gcc/config/alpha/ev5.md
@@ -18,7 +18,7 @@
 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
 ;; Boston, MA 02111-1307, USA.
 
-;; EV5 has two asymetric integer units, E0 and E1, plus separate
+;; EV5 has two asymmetric integer units, E0 and E1, plus separate
 ;; FP add and multiply units.
 
 (define_automaton "ev5_0,ev5_1")
@@ -97,7 +97,7 @@
 ; Conditional move and branch can issue the same cycle as the test.
 (define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p")
 
-; Multiplies use a non-piplined imul unit.  Also, "no insn can be issued
+; Multiplies use a non-pipelined imul unit.  Also, "no insn can be issued
 ; to E0 exactly two cycles before an integer multiply completes".
 
 (define_insn_reservation "ev5_imull" 8
@@ -136,7 +136,7 @@
 (define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh")
 (define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh")
 
-; Similarly for the FPU we have two asymetric units.
+; Similarly for the FPU we have two asymmetric units.
 
 (define_insn_reservation "ev5_fadd" 4
   (and (eq_attr "cpu" "ev5")
diff --git a/gcc/config/alpha/ev6.md b/gcc/config/alpha/ev6.md
index 23a09b0..561ca70 100644
--- a/gcc/config/alpha/ev6.md
+++ b/gcc/config/alpha/ev6.md
@@ -22,7 +22,7 @@
 ; expected to help over-much, but a precise description can be important
 ; for software pipelining.
 ;
-; EV6 has two symmetric pairs ("clusters") of two asymetric integer
+; EV6 has two symmetric pairs ("clusters") of two asymmetric integer
 ; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
 ;
 ; ??? The clusters have independent register files that are re-synced
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a8007c9..02864fb 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7875,7 +7875,7 @@ print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
 
   /* Add a ^ character for the 26-bit ABI, but only if we were loading
      the PC.  Otherwise we would generate an UNPREDICTABLE instruction.
-     Strictly speaking the instruction would be unpredicatble only if
+     Strictly speaking the instruction would be unpredictable only if
      we were writing back the base register as well, but since we never
      want to generate an LDM type 2 instruction (register bank switching)
      which is what you get if the PC is not being loaded, we do not need
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index 7500526..0dad6a4 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -1244,7 +1244,7 @@ c4x_emit_move_sequence (rtx *operands, enum machine_mode mode)
       && dp_reg_operand (XEXP (op1, 0), mode))
     {
       /* expand_increment will sometimes create a LO_SUM immediate
-	 address.  Undo this sillyness.  */
+	 address.  Undo this silliness.  */
       op1 = XEXP (op1, 1);
     }
   
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 0999adc..1ea954a 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -154,7 +154,7 @@
 ;  not for 'c'.
 
 ;  The 'f' constraint is only for float register operands---when 
-;  a register satisying the 'f' constraint is used as a dst operand,
+;  a register satisfying the 'f' constraint is used as a dst operand,
 ;  the CC gets clobbered (except for LDFcond).
 
 ;  The ! in front of the 'b' constraint says to GCC to disparage the
@@ -190,7 +190,7 @@
 ;  didn't allow it to move the CC around.
 
 ;  Note that fundamental operations, such as moves, must not clobber the
-;  CC.  Thus movqi choses a move instruction that doesn't clobber the CC.
+;  CC.  Thus movqi chooses a move instruction that doesn't clobber the CC.
 ;  If GCC wants to combine a move with a compare, it is smart enough to
 ;  chose the move instruction that sets the CC.
 
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 86795af..a975f0b 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -2947,7 +2947,7 @@ cris_split_movdx (rtx *operands)
 	  int reverse
 	    = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
 
-	  /* The original code imples that we can't do
+	  /* The original code implies that we can't do
 	     move.x [rN+],rM  move.x [rN],rM+1
 	     when rN is dead, because of REG_NOTES damage.  That is
 	     consistent with what I've seen, so don't try it.
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 7b028e0..a4a08fe 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -337,7 +337,7 @@ extern int target_flags;
 /* Whether or not to work around multiplication instruction hardware bug
    when generating code for models where it may be present.  From the
    trouble report for Etrax 100 LX: "A multiply operation may cause
-   incorrect cache behaviour under some specific circumstances. The
+   incorrect cache behavior under some specific circumstances. The
    problem can occur if the instruction following the multiply instruction
    causes a cache miss, and multiply operand 1 (source operand) bits
    [31:27] matches the logical mapping of the mode register address
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index c7459f8..81b5f1f 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -1208,7 +1208,7 @@ extern struct rtx_def * fr30_compare_op0;
 extern struct rtx_def * fr30_compare_op1;
 
 /*}}}*/ 
-/*{{{  PERDICATE_CODES.  */ 
+/*{{{  PREDICATE_CODES.  */ 
 
 #define PREDICATE_CODES					\
   { "stack_add_operand",	{ CONST_INT }},		\
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 242dfcd..d5808bf 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -6627,7 +6627,7 @@ frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
 }
 
 
-/* Internal function to add a potenial insn to the list of insns to be inserted
+/* Internal function to add a potential insn to the list of insns to be inserted
    if the conditional execution conversion is successful.  */
 
 static void
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index d1f3082..1e89210 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -931,7 +931,7 @@ extern int target_flags;
 #define LAST_ARG_REGNUM		(FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1)
 
 /* Registers used by the exception handling functions.  These should be
-   registers that are not otherwised used by the calling sequence.  */
+   registers that are not otherwise used by the calling sequence.  */
 #define FIRST_EH_REGNUM		14
 #define LAST_EH_REGNUM		15
 
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index ef2b49d..20170bd 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -2788,7 +2788,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "multi")])
 
-;; Patterns for addsi3/subdi3 after spliting
+;; Patterns for addsi3/subdi3 after splitting
 (define_insn "adddi3_lower"
   [(set (match_operand:SI 0 "integer_register_operand" "=d")
 	(plus:SI (match_operand:SI 1 "integer_register_operand" "d")
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 6bf3bfc..789bb00 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -4671,7 +4671,7 @@ same_cmp_following_p (rtx i1)
 }
 
 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
-   (or pops) N registers.  OPERANDS are asssumed to be an array of
+   (or pops) N registers.  OPERANDS are assumed to be an array of
    registers.  */
 
 int
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 615f2ee..5a6832d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15817,7 +15817,7 @@ ix86_expand_vector_init (rtx target, rtx vals)
     }
 
   /* ... values where only first field is non-constant are best loaded
-     from the pool and overwriten via move later.  */
+     from the pool and overwritten via move later.  */
   if (!i)
     {
       rtx op = simplify_gen_subreg (mode, XVECEXP (vals, 0, 0),
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3a87e71..e258559 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14937,7 +14937,7 @@
 ;; With sincos pattern defined, sin and cos builtin function will be
 ;; expanded to sincos pattern with one of its outputs left unused. 
 ;; Cse pass  will detected, if two sincos patterns can be combined,
-;; otherwise sincos pattern will be splitted back to sin or cos pattern,
+;; otherwise sincos pattern will be split back to sin or cos pattern,
 ;; depending on the unused output.
 
 (define_insn "sincosdf3"
diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c
index c4326f0..b97810a 100644
--- a/gcc/config/i386/winnt.c
+++ b/gcc/config/i386/winnt.c
@@ -672,7 +672,7 @@ i386_pe_section_type_flags (tree decl, const char *name, int reloc)
   unsigned int **slot;
 
   /* The names we put in the hashtable will always be the unique
-     versions gived to us by the stringtable, so we can just use
+     versions given to us by the stringtable, so we can just use
      their addresses as the keys.  */
   if (!htab)
     htab = htab_create (31, htab_hash_pointer, htab_eq_pointer, NULL);
diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md
index 0cdb070..6e71f5b 100644
--- a/gcc/config/ia64/itanium2.md
+++ b/gcc/config/ia64/itanium2.md
@@ -484,7 +484,7 @@
 (define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")
 
 ;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use.  Remeber about possible splitting.
+;; not already in use.  Remember about possible splitting.
 (define_reservation "2_I0"
   "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
    |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
@@ -1335,7 +1335,7 @@
    +(2b_um2|2b_um3)")
 
 ;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use.  Remeber about possible splitting.
+;; not already in use.  Remember about possible splitting.
 (define_reservation "2b_I"
   "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
    |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\
diff --git a/gcc/config/ip2k/ip2k.c b/gcc/config/ip2k/ip2k.c
index c6fd0d1..05ccb61 100644
--- a/gcc/config/ip2k/ip2k.c
+++ b/gcc/config/ip2k/ip2k.c
@@ -2730,7 +2730,7 @@ ip2k_gen_unsigned_comp_branch (rtx insn, enum rtx_code code, rtx label)
 	case GTU:
 	  if (imm_sub)
 	    {
-	      /* > 0xffffffffffffffff never suceeds!  */
+	      /* > 0xffffffffffffffff never succeeds!  */
 	      if (((const_high & 0xffffffff) != 0xffffffff)
 		  || ((const_low & 0xffffffff) != 0xffffffff))
 		{
@@ -2948,7 +2948,7 @@ ip2k_gen_unsigned_comp_branch (rtx insn, enum rtx_code code, rtx label)
 	      if (((const_high & 0xffffffff) == 0xffffffff)
 		  && ((const_low & 0xffffffff) == 0xffffffff))
 	        {
-		  /* <= 0xffffffffffffffff always suceeds.  */
+		  /* <= 0xffffffffffffffff always succeeds.  */
 		  OUT_AS1 (page, %2);
 	          OUT_AS1 (jmp, %2);
 		}
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index bbb664e..ccb2b3f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4762,7 +4762,7 @@ override_options (void)
 
        (1) The value of an R_MIPS_GOT16 relocation depends on whether
 	   the symbol is local or global.  We therefore need to know
-	   a symbol's binding before refering to it using %got().
+	   a symbol's binding before referring to it using %got().
 
        (2) R_MIPS_CALL16 can only be applied to global symbols.
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e678ba9..3c3936d 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -2076,7 +2076,7 @@ extern enum reg_class mips_char_to_class[256];
    `T' is for constant move_operands that cannot be safely loaded into $25.
    `U' is for constant move_operands that can be safely loaded into $25.
    `W' is for memory references that are based on a member of BASE_REG_CLASS.
-	 This is true for all non-mips16 references (although it can somtimes
+	 This is true for all non-mips16 references (although it can sometimes
 	 be indirect if !TARGET_EXPLICIT_RELOCS).  For mips16, it excludes
 	 stack and constant-pool references.  */
 
diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md
index ef7e650..f1ce973 100644
--- a/gcc/config/mips/sr71k.md
+++ b/gcc/config/mips/sr71k.md
@@ -17,7 +17,7 @@
 ;;  contrived to support published timings.
 ;;
 ;; Reference:
-;;   "SR3 Microporocessor Specification, System development information,"
+;;   "SR3 Microprocessor Specification, System development information,"
 ;;   Revision 1.0, 13 December 2000.
 ;;
 ;;
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index d9dea93..d4a286d 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -8419,7 +8419,7 @@ pa_reorg (void)
 	 markers disables output of the branch table to readonly memory,
 	 and any alignment directives that might be needed.  Possibly,
 	 the begin_brtab insn should be output before the label for the
-	 table.  This doesn matter at the moment since the tables are
+	 table.  This doesn't matter at the moment since the tables are
 	 always output in the text section.  */
       for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
 	{
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 63fc3e5..ed277ad 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -5219,7 +5219,7 @@ s390_return_addr_rtx (int count, rtx frame)
   return gen_rtx_MEM (Pmode, addr);
 }
 
-/* Find first call clobbered register unsused in a function.
+/* Find first call clobbered register unused in a function.
    This could be used as base register in a leaf function
    or for holding the return address before epilogue.  */
 
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 66a7da4..ed4b714 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -338,7 +338,7 @@ static tree sh_build_builtin_va_list (void);
    TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
    scheduler; it is called inside the sched_init function just after
    find_insn_reg_weights function call. It is used to calculate the SImode
-   and SFmode weights of insns of basic blocks; much similiar to what
+   and SFmode weights of insns of basic blocks; much similar to what
    find_insn_reg_weights does. 
    TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.