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authorUros Bizjak <uros@gcc.gnu.org>2011-03-18 21:54:25 +0100
committerUros Bizjak <uros@gcc.gnu.org>2011-03-18 21:54:25 +0100
commit16cc44407fe40e3411e206eeec60a14d20769ade (patch)
treefb631932e8019654ce883f5f06071216d35dc929 /gcc/config
parentf2c779bb053da67c12af0c91371ce13b5cdf8a7a (diff)
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i386.md (float<SSEMODEI24:mode><X87MODEF:mode>2): Rewrite using indirect functions.
* config/i386/i386.md (float<SSEMODEI24:mode><X87MODEF:mode>2): Rewrite using indirect functions. (lwp_slwpcb): Ditto. * config/i386/sse.md (avx_vextractf128<mode>): Ditto. (avx_vinsertf128<mode>): Ditto. From-SVN: r171169
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/i386/i386.md19
-rw-r--r--gcc/config/i386/sse.md18
2 files changed, 23 insertions, 14 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 12470ea..c9761a4 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4959,18 +4959,18 @@
&& !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode))
{
rtx reg = gen_reg_rtx (XFmode);
- rtx insn;
+ rtx (*insn)(rtx, rtx);
emit_insn (gen_float<SSEMODEI24:mode>xf2 (reg, operands[1]));
if (<X87MODEF:MODE>mode == SFmode)
- insn = gen_truncxfsf2 (operands[0], reg);
+ insn = gen_truncxfsf2;
else if (<X87MODEF:MODE>mode == DFmode)
- insn = gen_truncxfdf2 (operands[0], reg);
+ insn = gen_truncxfdf2;
else
gcc_unreachable ();
- emit_insn (insn);
+ emit_insn (insn (operands[0], reg));
DONE;
}
})
@@ -18216,10 +18216,13 @@
(unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
"TARGET_LWP"
{
- if (TARGET_64BIT)
- emit_insn (gen_lwp_slwpcbdi (operands[0]));
- else
- emit_insn (gen_lwp_slwpcbsi (operands[0]));
+ rtx (*insn)(rtx);
+
+ insn = (TARGET_64BIT
+ ? gen_lwp_slwpcbdi
+ : gen_lwp_slwpcbsi);
+
+ emit_insn (insn (operands[0]));
DONE;
})
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ba2bf24..6200419 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4122,17 +4122,21 @@
(match_operand:SI 2 "const_0_to_1_operand" "")]
"TARGET_AVX"
{
+ rtx (*insn)(rtx, rtx);
+
switch (INTVAL (operands[2]))
{
case 0:
- emit_insn (gen_vec_extract_lo_<mode> (operands[0], operands[1]));
+ insn = gen_vec_extract_lo_<mode>;
break;
case 1:
- emit_insn (gen_vec_extract_hi_<mode> (operands[0], operands[1]));
+ insn = gen_vec_extract_hi_<mode>;
break;
default:
gcc_unreachable ();
}
+
+ emit_insn (insn (operands[0], operands[1]));
DONE;
})
@@ -11776,19 +11780,21 @@
(match_operand:SI 3 "const_0_to_1_operand" "")]
"TARGET_AVX"
{
+ rtx (*insn)(rtx, rtx, rtx);
+
switch (INTVAL (operands[3]))
{
case 0:
- emit_insn (gen_vec_set_lo_<mode> (operands[0], operands[1],
- operands[2]));
+ insn = gen_vec_set_lo_<mode>;
break;
case 1:
- emit_insn (gen_vec_set_hi_<mode> (operands[0], operands[1],
- operands[2]));
+ insn = gen_vec_set_hi_<mode>;
break;
default:
gcc_unreachable ();
}
+
+ emit_insn (insn (operands[0], operands[1], operands[2]));
DONE;
})