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| author | Daniel Gutson <dgutson@codesourcery.com> | 2009-09-04 02:52:08 +0000 |
|---|---|---|
| committer | Daniel Gutson <dgutson@gcc.gnu.org> | 2009-09-04 02:52:08 +0000 |
| commit | ca96ed43b2666f3552806f84ff1229e76fb042d2 (patch) | |
| tree | c42128928f5a992274cc7e584fea7e404deb3a4b /gcc/config | |
| parent | 9af43ec7a23b80c4fa17681245303ebdb1262fb5 (diff) | |
| download | gcc-ca96ed43b2666f3552806f84ff1229e76fb042d2.zip gcc-ca96ed43b2666f3552806f84ff1229e76fb042d2.tar.gz gcc-ca96ed43b2666f3552806f84ff1229e76fb042d2.tar.bz2 | |
arm.md (UNSPEC_RBIT): New constant.
2009-09-03 Daniel Gutson <dgutson@codesourcery.com>
* config/arm/arm.md (UNSPEC_RBIT): New constant.
(rbitsi2): New insn.
(ctzsi2): New expand.
* config/arm/arm.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.
testsuite/
* gcc.target/arm/ctz.c: New test case.
From-SVN: r151402
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm.h | 1 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 21 |
2 files changed, 22 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ae32da5..215c9fb 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2368,6 +2368,7 @@ extern int making_const_table; /* The arm5 clz instruction returns 32. */ #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) #undef ASM_APP_OFF #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 09a1b08..fd00c70 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -100,6 +100,7 @@ (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a ; a given symbolic address. (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call. + (UNSPEC_RBIT 26) ; rbit operation. ] ) @@ -10955,6 +10956,26 @@ [(set_attr "predicable" "yes") (set_attr "insn" "clz")]) +(define_insn "rbitsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))] + "TARGET_32BIT && arm_arch_thumb2" + "rbit%?\\t%0, %1" + [(set_attr "predicable" "yes") + (set_attr "insn" "clz")]) + +(define_expand "ctzsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (ctz:SI (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_32BIT && arm_arch_thumb2" + " + rtx tmp = gen_reg_rtx (SImode); + emit_insn (gen_rbitsi2 (tmp, operands[1])); + emit_insn (gen_clzsi2 (operands[0], tmp)); + DONE; + " +) + ;; V5E instructions. (define_insn "prefetch" |