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| author | Julia Koval <julia.koval@intel.com> | 2017-12-15 06:04:33 +0100 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2017-12-15 05:04:33 +0000 |
| commit | 549fa5843dd13df696920b030f54eed1dcfbfe73 (patch) | |
| tree | 1de9a2cf6b4d31885515b4dfd9dd6d625ef098eb /gcc/config | |
| parent | 5a5d179739d7d3deaaf3d9788e8ddbd50ca35f00 (diff) | |
| download | gcc-549fa5843dd13df696920b030f54eed1dcfbfe73.zip gcc-549fa5843dd13df696920b030f54eed1dcfbfe73.tar.gz gcc-549fa5843dd13df696920b030f54eed1dcfbfe73.tar.bz2 | |
Enable VAES support [5/5]
gcc/
* config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi,
__builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New.
* config/i386/sse.md (vaesenclast_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesenclast_epi128,
_mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics.
gcc/testsuite/
* gcc.target/i386/avx512f-aesenclast-2.c: New test.
* gcc.target/i386/avx512vl-aesenclast-2.c: Ditto.
* gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics.
From-SVN: r255676
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386-builtin.def | 3 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 11 | ||||
| -rw-r--r-- | gcc/config/i386/vaesintrin.h | 24 |
3 files changed, 38 insertions, 0 deletions
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 1fe9bdf..e3b12bd 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2773,6 +2773,9 @@ BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdec BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) BDESC_END (ARGS2, SPECIAL_ARGS2) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ac37939..c1469f4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -177,6 +177,7 @@ UNSPEC_VAESDEC UNSPEC_VAESDECLAST UNSPEC_VAESENC + UNSPEC_VAESENCLAST ]) (define_c_enum "unspecv" [ @@ -20487,3 +20488,13 @@ "TARGET_VAES" "vaesenc\t{%2, %1, %0|%0, %1, %2}" ) + +(define_insn "vaesenclast_<mode>" + [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v") + (unspec:VI1_AVX512VL_F + [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v") + (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")] + UNSPEC_VAESENCLAST))] + "TARGET_VAES" + "vaesenclast\t{%2, %1, %0|%0, %1, %2}" +) diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h index 3bbfb39..510a36e 100644 --- a/gcc/config/i386/vaesintrin.h +++ b/gcc/config/i386/vaesintrin.h @@ -29,6 +29,14 @@ _mm256_aesenc_epi128 (__m256i __A, __m256i __B) return (__m256i)__builtin_ia32_vaesenc_v32qi ((__v32qi) __A, (__v32qi) __B); } +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_aesenclast_epi128 (__m256i __A, __m256i __B) +{ + return (__m256i)__builtin_ia32_vaesenclast_v32qi ((__v32qi) __A, + (__v32qi) __B); +} + #ifdef __DISABLE_VAES__ #undef __DISABLE_VAES__ #pragma GCC pop_options @@ -64,6 +72,14 @@ _mm512_aesenc_epi128 (__m512i __A, __m512i __B) return (__m512i)__builtin_ia32_vaesenc_v64qi ((__v64qi) __A, (__v64qi) __B); } +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_aesenclast_epi128 (__m512i __A, __m512i __B) +{ + return (__m512i)__builtin_ia32_vaesenclast_v64qi ((__v64qi) __A, + (__v64qi) __B); +} + #ifdef __DISABLE_VAESF__ #undef __DISABLE_VAESF__ #pragma GCC pop_options @@ -97,6 +113,14 @@ _mm_aesenc_epi128 (__m128i __A, __m128i __B) return (__m128i)__builtin_ia32_vaesenc_v16qi ((__v16qi) __A, (__v16qi) __B); } +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_aesenclast_epi128 (__m128i __A, __m128i __B) +{ + return (__m128i)__builtin_ia32_vaesenclast_v16qi ((__v16qi) __A, + (__v16qi) __B); +} + #ifdef __DISABLE_VAESVL__ #undef __DISABLE_VAESVL__ #pragma GCC pop_options |