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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-04-11 08:58:34 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-04-11 08:58:34 +0000 |
| commit | d07458be3e41c069c0eaf627a371ac7d297c782d (patch) | |
| tree | 6a3a34a69243fe5d1a1d77ded71e1292680d2ae6 /gcc/config | |
| parent | 146b8692e33b78872476435d084d5062a243a200 (diff) | |
| download | gcc-d07458be3e41c069c0eaf627a371ac7d297c782d.zip gcc-d07458be3e41c069c0eaf627a371ac7d297c782d.tar.gz gcc-d07458be3e41c069c0eaf627a371ac7d297c782d.tar.bz2 | |
[PATCH, AARCH64] Fix unrecognizable insn issue with vcond against 0.0f
gcc/
* config/aarch64/aarch64-simd.md (aarch64_vcond_internal): Fix
floating-point vector comparisons against 0.
gcc/testsuite/
* gcc.target/aarch64/vect-fcm.x: Add check for zero forms of
inverse operands.
* gcc.target/aarch64/vect-fcm-eq-d.c: Check that new zero form
loop is vectorized.
* gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-ge-d.c: Check that new zero form
loop is vectorized and that the correct instruction is generated.
* gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
* gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
From-SVN: r197741
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 92dcfc0..f72a2e2 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1622,6 +1622,7 @@ "TARGET_SIMD" { int inverse = 0; + int use_zero_form = 0; int swap_bsl_operands = 0; rtx mask = gen_reg_rtx (<V_cmp_result>mode); rtx tmp = gen_reg_rtx (<V_cmp_result>mode); @@ -1632,12 +1633,16 @@ switch (GET_CODE (operands[3])) { case GE: + case GT: case LE: + case LT: case EQ: - if (!REG_P (operands[5]) - && (operands[5] != CONST0_RTX (<MODE>mode))) - operands[5] = force_reg (<MODE>mode, operands[5]); - break; + if (operands[5] == CONST0_RTX (<MODE>mode)) + { + use_zero_form = 1; + break; + } + /* Fall through. */ default: if (!REG_P (operands[5])) operands[5] = force_reg (<MODE>mode, operands[5]); @@ -1688,7 +1693,26 @@ a GT b -> a GT b a LE b -> b GE a a LT b -> b GT a - a EQ b -> a EQ b */ + a EQ b -> a EQ b + Note that there also exist direct comparison against 0 forms, + so catch those as a special case. */ + if (use_zero_form) + { + inverse = 0; + switch (GET_CODE (operands[3])) + { + case LT: + base_comparison = gen_aarch64_cmlt<mode>; + break; + case LE: + base_comparison = gen_aarch64_cmle<mode>; + break; + default: + /* Do nothing, other zero form cases already have the correct + base_comparison. */ + break; + } + } if (!inverse) emit_insn (base_comparison (mask, operands[4], operands[5])); |