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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-04-29 16:10:27 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-04-29 16:10:27 +0000 |
| commit | aaf3de7ab2aac4b0b4c5a4fb260ca1955350a360 (patch) | |
| tree | 4a55b5ba8775e74dd0346cc6baae9a5658bb9ef2 /gcc/config | |
| parent | 952bc7a64cd257de733fddaec64e320f973c6350 (diff) | |
| download | gcc-aaf3de7ab2aac4b0b4c5a4fb260ca1955350a360.zip gcc-aaf3de7ab2aac4b0b4c5a4fb260ca1955350a360.tar.gz gcc-aaf3de7ab2aac4b0b4c5a4fb260ca1955350a360.tar.bz2 | |
[AArch64] Fix PR/65770 vstN_lane on bigendian
gcc/:
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>,
vec_store_lanesci_lane<mode>, vec_store_lanesxi_lane<mode>):
Flip lane index back at assembly time for bigendian.
gcc/testsuite/:
* gcc.target/aarch64/vstN_lane_1.c: New file.
From-SVN: r222582
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0557570..b843744 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3954,6 +3954,7 @@ [(set_attr "type" "neon_store2_2reg<q>")] ) +;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "vec_store_lanesoi_lane<mode>" [(set (match_operand:<V_TWO_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_TWO_ELEM> [(match_operand:OI 1 "register_operand" "w") @@ -3961,7 +3962,10 @@ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST2_LANE))] "TARGET_SIMD" - "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); + return "st2\\t{%S1.<Vetype> - %T1.<Vetype>}[%2], %0"; + } [(set_attr "type" "neon_store3_one_lane<q>")] ) @@ -4045,6 +4049,7 @@ [(set_attr "type" "neon_store3_3reg<q>")] ) +;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "vec_store_lanesci_lane<mode>" [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w") @@ -4052,7 +4057,10 @@ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST3_LANE))] "TARGET_SIMD" - "st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); + return "st3\\t{%S1.<Vetype> - %U1.<Vetype>}[%2], %0"; + } [(set_attr "type" "neon_store3_one_lane<q>")] ) @@ -4136,6 +4144,7 @@ [(set_attr "type" "neon_store4_4reg<q>")] ) +;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "vec_store_lanesxi_lane<mode>" [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") (unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w") @@ -4143,7 +4152,10 @@ (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST4_LANE))] "TARGET_SIMD" - "st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); + return "st4\\t{%S1.<Vetype> - %V1.<Vetype>}[%2], %0"; + } [(set_attr "type" "neon_store4_one_lane<q>")] ) |