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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-05-08 11:49:02 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-05-08 11:49:02 +0000 |
| commit | 8b5190aba09f9f1af9f655b543faee2b58f746ef (patch) | |
| tree | 26f2bc28f6119fb38a97eed85b3220bc000397bc /gcc/config | |
| parent | 938fb83d2ce3c27a1b23c2a992bce3767179b73d (diff) | |
| download | gcc-8b5190aba09f9f1af9f655b543faee2b58f746ef.zip gcc-8b5190aba09f9f1af9f655b543faee2b58f746ef.tar.gz gcc-8b5190aba09f9f1af9f655b543faee2b58f746ef.tar.bz2 | |
[AArch64] Add vcond(u?)didi pattern
* config/aarch64/aarch64-simd.md (aarch64_vcond_internal<mode><mode>,
vcond<mode><mode>, vcondu<mode><mode>): Add DImode variant.
From-SVN: r222908
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5342c3d..b90f938 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2057,13 +2057,13 @@ }) (define_expand "aarch64_vcond_internal<mode><mode>" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { rtx op1 = operands[1]; @@ -2365,13 +2365,13 @@ }) (define_expand "vcond<mode><mode>" - [(set (match_operand:VALL 0 "register_operand") - (if_then_else:VALL + [(set (match_operand:VALLDI 0 "register_operand") + (if_then_else:VALLDI (match_operator 3 "comparison_operator" - [(match_operand:VALL 4 "register_operand") - (match_operand:VALL 5 "nonmemory_operand")]) - (match_operand:VALL 1 "nonmemory_operand") - (match_operand:VALL 2 "nonmemory_operand")))] + [(match_operand:VALLDI 4 "register_operand") + (match_operand:VALLDI 5 "nonmemory_operand")]) + (match_operand:VALLDI 1 "nonmemory_operand") + (match_operand:VALLDI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1], @@ -2398,13 +2398,13 @@ }) (define_expand "vcondu<mode><mode>" - [(set (match_operand:VDQ_I 0 "register_operand") - (if_then_else:VDQ_I + [(set (match_operand:VSDQ_I_DI 0 "register_operand") + (if_then_else:VSDQ_I_DI (match_operator 3 "comparison_operator" - [(match_operand:VDQ_I 4 "register_operand") - (match_operand:VDQ_I 5 "nonmemory_operand")]) - (match_operand:VDQ_I 1 "nonmemory_operand") - (match_operand:VDQ_I 2 "nonmemory_operand")))] + [(match_operand:VSDQ_I_DI 4 "register_operand") + (match_operand:VSDQ_I_DI 5 "nonmemory_operand")]) + (match_operand:VSDQ_I_DI 1 "nonmemory_operand") + (match_operand:VSDQ_I_DI 2 "nonmemory_operand")))] "TARGET_SIMD" { emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1], |