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| author | Jakub Jelinek <jakub@gcc.gnu.org> | 2004-07-08 17:58:22 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2004-07-08 17:58:22 +0200 |
| commit | c618c6ec7e797b5aa69218b86cd643bb65c0c48a (patch) | |
| tree | ceb3967dbf08a732475f57723332634514a7ec6a /gcc/config | |
| parent | 75f29cdded521da42f6b3a8d790371203d833664 (diff) | |
| download | gcc-c618c6ec7e797b5aa69218b86cd643bb65c0c48a.zip gcc-c618c6ec7e797b5aa69218b86cd643bb65c0c48a.tar.gz gcc-c618c6ec7e797b5aa69218b86cd643bb65c0c48a.tar.bz2 | |
[multiple changes]
2004-07-08 Paolo Bonzini <bonzini@gnu.org>
Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.c (override_options): Enable
SSE prefetches with -mtune, as long as we are
compiling for i686 or higher. All i686 processors
accept SSE prefetches as NOPS, some i586's don't.
2004-07-08 Jakub Jelinek <jakub@redhat.com>
* gcc.mist-tests/i386-prefetch.exp (PREFETCH_SSE): Change all
-march=i386 into -march=i686. Add -march=i686 -mtune=x and
-march=x for pentium3, pentium3m, pentium-m, pentium4m,
prescott and c3-2.
(PREFETCH_3DNOW): Add -march=c3.
From-SVN: r84297
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b51586f..b468e1d 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1306,6 +1306,14 @@ override_options (void) ix86_tune = processor_alias_table[i].processor; if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) error ("CPU you selected does not support x86-64 instruction set"); + + /* Intel CPUs have always interpreted SSE prefetch instructions as + NOPs; so, we can enable SSE prefetch instructions even when + -mtune (rather than -march) points us to a processor that has them. + However, the VIA C3 gives a SIGILL, so we only do that for i686 and + higher processors. */ + if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE)) + x86_prefetch_sse = true; break; } if (i == pta_size) |