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author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-09 20:05:50 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2023-05-10 16:21:59 +0800 |
commit | a2676383adf31a7b4b64b7b1817428f953041d73 (patch) | |
tree | fd74689050c2bdc4a0083b8e2f2ed986fd1babdb /gcc/config | |
parent | 69f3914414a303f0e2c8246e08925f90c207846c (diff) | |
download | gcc-a2676383adf31a7b4b64b7b1817428f953041d73.zip gcc-a2676383adf31a7b4b64b7b1817428f953041d73.tar.gz gcc-a2676383adf31a7b4b64b7b1817428f953041d73.tar.bz2 |
RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.
They let movmisalign<mode> to handle scalable vector of SVE.
For RVV, we should follow the same implementation of ARM SVE.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
incorrect codes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/riscv/riscv.cc | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8684271..ff90c44 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7264,27 +7264,20 @@ riscv_estimated_poly_value (poly_int64 val, return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } +/* Return true if the vector misalignment factor is supported by the + target. */ bool riscv_support_vector_misalignment (machine_mode mode, const_tree type ATTRIBUTE_UNUSED, int misalignment, bool is_packed ATTRIBUTE_UNUSED) { - if (TARGET_VECTOR) - { - if (STRICT_ALIGNMENT) - { - /* Return if movmisalign pattern is not supported for this mode. */ - if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing) - return false; - - /* Misalignment factor is unknown at compile time. */ - if (misalignment == -1) - return false; - } - return true; - } + /* TODO: For RVV scalable vector auto-vectorization, we should allow + movmisalign<mode> pattern to handle misalign data movement to unblock + possible auto-vectorization. + RVV VLS auto-vectorization or SIMD auto-vectorization can be supported here + in the future. */ return default_builtin_support_vector_misalignment (mode, type, misalignment, is_packed); } |