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| author | Ian Lance Taylor <iant@golang.org> | 2020-12-04 14:51:32 -0800 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2020-12-04 14:51:32 -0800 |
| commit | 945ae3ab27757d3261d99446f96105c5ebe70247 (patch) | |
| tree | a8a120ef5393206d3bc9d2b5882bac1562824836 /gcc/config | |
| parent | f012991e2db06cc95f7aac8ecb74a1ac5f51f3d2 (diff) | |
| parent | 918a5b84a2c51dc9d011d39461cc276e6558069d (diff) | |
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Merge from trunk revision 918a5b84a2c51dc9d011d39461cc276e6558069d
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 32 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 6 |
2 files changed, 38 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 76e9499..129d47b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11975,6 +11975,23 @@ (clobber (reg:CC FLAGS_REG))])] "operands[2] = gen_lowpart (QImode, operands[2]);") +(define_split + [(set (match_operand:SWI48 0 "register_operand") + (any_rotate:SWI48 + (match_operand:SWI48 1 "const_int_operand") + (subreg:QI + (and:SI + (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "const_int_operand")) 0)))] + "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode) - 1)) + == GET_MODE_BITSIZE (<MODE>mode) - 1" + [(set (match_dup 4) (match_dup 1)) + (set (match_dup 0) + (any_rotate:SWI48 (match_dup 4) + (subreg:QI + (and:SI (match_dup 2) (match_dup 3)) 0)))] + "operands[4] = gen_reg_rtx (<MODE>mode);") + (define_insn_and_split "*<rotate_insn><mode>3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_rotate:SWI48 @@ -11995,6 +12012,21 @@ (match_dup 2))) (clobber (reg:CC FLAGS_REG))])]) +(define_split + [(set (match_operand:SWI48 0 "register_operand") + (any_rotate:SWI48 + (match_operand:SWI48 1 "const_int_operand") + (and:QI + (match_operand:QI 2 "register_operand") + (match_operand:QI 3 "const_int_operand"))))] + "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode) - 1)) + == GET_MODE_BITSIZE (<MODE>mode) - 1" + [(set (match_dup 4) (match_dup 1)) + (set (match_dup 0) + (any_rotate:SWI48 (match_dup 4) + (and:QI (match_dup 2) (match_dup 3))))] + "operands[4] = gen_reg_rtx (<MODE>mode);") + ;; Implement rotation using two double-precision ;; shift instructions and a scratch register. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c661f7a..f26fc13 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3864,6 +3864,12 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags); +#ifdef XCOFF_DEBUGGING_INFO + /* For AIX default to 64-bit DWARF. */ + if (!global_options_set.x_dwarf_offset_size) + dwarf_offset_size = POINTER_SIZE_UNITS; +#endif + /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn off all of the options that depend on those flags. */ ignore_masks = rs6000_disable_incompatible_switches (); |