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| author | Ian Lance Taylor <iant@golang.org> | 2021-02-02 12:42:10 -0800 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2021-02-02 12:42:10 -0800 |
| commit | 8910f1cd79445bbe2da01f8ccf7c37909349529e (patch) | |
| tree | ba67a346969358fd7cc2b7c12384479de8364cab /gcc/config | |
| parent | 45c32be1f96ace25b66c34a84818dc5e07e9d516 (diff) | |
| parent | 8e4a738d2540ab6aff77506d368bf4e3fa6963bd (diff) | |
| download | gcc-8910f1cd79445bbe2da01f8ccf7c37909349529e.zip gcc-8910f1cd79445bbe2da01f8ccf7c37909349529e.tar.gz gcc-8910f1cd79445bbe2da01f8ccf7c37909349529e.tar.bz2 | |
Merge from trunk revision 8e4a738d2540ab6aff77506d368bf4e3fa6963bd.
Diffstat (limited to 'gcc/config')
1593 files changed, 11914 insertions, 6734 deletions
diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 389084f..b749727 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-bti-insert.c b/gcc/config/aarch64/aarch64-bti-insert.c index 9802669..9366497 100644 --- a/gcc/config/aarch64/aarch64-bti-insert.c +++ b/gcc/config/aarch64/aarch64-bti-insert.c @@ -1,5 +1,5 @@ /* Branch Target Identification for AArch64 architecture. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Arm Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 188fce0..25ab866 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1,5 +1,5 @@ /* Builtins' description for AArch64 SIMD architecture. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -133,6 +133,7 @@ const unsigned int FLAG_FP = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS; const unsigned int FLAG_ALL = FLAG_READ_FPCR | FLAG_RAISE_FP_EXCEPTIONS | FLAG_READ_MEMORY | FLAG_PREFETCH_MEMORY | FLAG_WRITE_MEMORY; const unsigned int FLAG_STORE = FLAG_WRITE_MEMORY | FLAG_AUTO_FP; +const unsigned int FLAG_LOAD = FLAG_READ_MEMORY | FLAG_AUTO_FP; typedef struct { diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 5e23328..f9ddffa 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -1,5 +1,5 @@ /* Target-specific code for C family languages. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-cc-fusion.cc b/gcc/config/aarch64/aarch64-cc-fusion.cc new file mode 100644 index 0000000..09069a2 --- /dev/null +++ b/gcc/config/aarch64/aarch64-cc-fusion.cc @@ -0,0 +1,296 @@ +// Pass to fuse CC operations with other instructions. +// Copyright (C) 2021 Free Software Foundation, Inc. +// +// This file is part of GCC. +// +// GCC is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 3, or (at your option) any later +// version. +// +// GCC is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with GCC; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// This pass looks for sequences of the form: +// +// A: (set (reg R1) X1) +// B: ...instructions that might change the value of X1... +// C: (set (reg CC) X2) // X2 uses R1 +// +// and tries to change them to: +// +// C': [(set (reg CC) X2') +// (set (reg R1) X1)] +// B: ...instructions that might change the value of X1... +// +// where X2' is the result of replacing R1 with X1 in X2. +// +// This sequence occurs in SVE code in two important cases: +// +// (a) Sometimes, to deal correctly with overflow, we need to increment +// an IV after a WHILELO rather than before it. In this case: +// - A is a WHILELO, +// - B includes an IV increment and +// - C is a separate PTEST. +// +// (b) ACLE code of the form: +// +// svbool_t ok = svrdffr (); +// if (svptest_last (pg, ok)) +// ... +// +// must, for performance reasons, be code-generated as: +// +// RDFFRS Pok.B, Pg/Z +// ...branch on flags result... +// +// without a separate PTEST of Pok. In this case: +// - A is an aarch64_rdffr +// - B includes an aarch64_update_ffrt +// - C is a separate PTEST +// +// Combine can handle this optimization if B doesn't exist and if A and +// C are in the same BB. This pass instead handles cases where B does +// exist and cases where A and C are in different BBs of the same EBB. + +#define IN_TARGET_CODE 1 + +#define INCLUDE_ALGORITHM +#define INCLUDE_FUNCTIONAL +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "backend.h" +#include "rtl.h" +#include "df.h" +#include "rtl-ssa.h" +#include "tree-pass.h" + +using namespace rtl_ssa; + +namespace { +const pass_data pass_data_cc_fusion = +{ + RTL_PASS, // type + "cc_fusion", // name + OPTGROUP_NONE, // optinfo_flags + TV_NONE, // tv_id + 0, // properties_required + 0, // properties_provided + 0, // properties_destroyed + 0, // todo_flags_start + TODO_df_finish, // todo_flags_finish +}; + +// Class that represents one run of the pass. +class cc_fusion +{ +public: + cc_fusion () : m_parallel () {} + void execute (); + +private: + rtx optimizable_set (const insn_info *); + bool parallelize_insns (def_info *, rtx, def_info *, rtx); + void optimize_cc_setter (def_info *, rtx); + + // A spare PARALLEL rtx, or null if none. + rtx m_parallel; +}; + +// See whether INSN is a single_set that we can optimize. Return the +// set if so, otherwise return null. +rtx +cc_fusion::optimizable_set (const insn_info *insn) +{ + if (!insn->can_be_optimized () + || insn->is_asm () + || insn->has_volatile_refs () + || insn->has_pre_post_modify ()) + return NULL_RTX; + + return single_set (insn->rtl ()); +} + +// CC_SET is a single_set that sets (only) CC_DEF; OTHER_SET is likewise +// a single_set that sets (only) OTHER_DEF. CC_SET is known to set the +// CC register and the instruction that contains CC_SET is known to use +// OTHER_DEF. Try to do CC_SET and OTHER_SET in parallel. +bool +cc_fusion::parallelize_insns (def_info *cc_def, rtx cc_set, + def_info *other_def, rtx other_set) +{ + auto attempt = crtl->ssa->new_change_attempt (); + + insn_info *cc_insn = cc_def->insn (); + insn_info *other_insn = other_def->insn (); + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "trying to parallelize insn %d and insn %d\n", + other_insn->uid (), cc_insn->uid ()); + + // Try to substitute OTHER_SET into CC_INSN. + insn_change_watermark rtl_watermark; + rtx_insn *cc_rtl = cc_insn->rtl (); + insn_propagation prop (cc_rtl, SET_DEST (other_set), + SET_SRC (other_set)); + if (!prop.apply_to_pattern (&PATTERN (cc_rtl)) + || prop.num_replacements == 0) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "-- failed to substitute all uses of r%d\n", + other_def->regno ()); + return false; + } + + // Restrict the uses to those outside notes. + use_array cc_uses = remove_note_accesses (attempt, cc_insn->uses ()); + use_array other_set_uses = remove_note_accesses (attempt, + other_insn->uses ()); + + // Remove the use of the substituted value. + access_array_builder uses_builder (attempt); + uses_builder.reserve (cc_uses.size ()); + for (use_info *use : cc_uses) + if (use->def () != other_def) + uses_builder.quick_push (use); + cc_uses = use_array (uses_builder.finish ()); + + // Get the list of uses for the new instruction. + insn_change cc_change (cc_insn); + cc_change.new_uses = merge_access_arrays (attempt, other_set_uses, cc_uses); + if (!cc_change.new_uses.is_valid ()) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "-- cannot merge uses\n"); + return false; + } + + // The instruction initially defines just two registers. recog can add + // extra clobbers if necessary. + auto_vec<access_info *, 2> new_defs; + new_defs.quick_push (cc_def); + new_defs.quick_push (other_def); + sort_accesses (new_defs); + cc_change.new_defs = def_array (access_array (new_defs)); + + // Make sure there is somewhere that the new instruction could live. + auto other_change = insn_change::delete_insn (other_insn); + insn_change *changes[] = { &other_change, &cc_change }; + cc_change.move_range = cc_insn->ebb ()->insn_range (); + if (!restrict_movement_ignoring (cc_change, insn_is_changing (changes))) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "-- cannot satisfy all definitions and uses\n"); + return false; + } + + // Tentatively install the new pattern. By convention, the CC set + // must be first. + if (m_parallel) + { + XVECEXP (m_parallel, 0, 0) = cc_set; + XVECEXP (m_parallel, 0, 1) = other_set; + } + else + { + rtvec vec = gen_rtvec (2, cc_set, other_set); + m_parallel = gen_rtx_PARALLEL (VOIDmode, vec); + } + validate_change (cc_rtl, &PATTERN (cc_rtl), m_parallel, 1); + + // These routines report failures themselves. + if (!recog_ignoring (attempt, cc_change, insn_is_changing (changes)) + || !changes_are_worthwhile (changes) + || !crtl->ssa->verify_insn_changes (changes)) + return false; + + remove_reg_equal_equiv_notes (cc_rtl); + confirm_change_group (); + crtl->ssa->change_insns (changes); + m_parallel = NULL_RTX; + return true; +} + +// Try to optimize the instruction that contains CC_DEF, where CC_DEF describes +// a definition of the CC register by CC_SET. +void +cc_fusion::optimize_cc_setter (def_info *cc_def, rtx cc_set) +{ + // Search the registers used by the CC setter for an easily-substitutable + // def-use chain. + for (use_info *other_use : cc_def->insn ()->uses ()) + if (def_info *other_def = other_use->def ()) + if (other_use->regno () != CC_REGNUM + && other_def->ebb () == cc_def->ebb ()) + if (rtx other_set = optimizable_set (other_def->insn ())) + { + rtx dest = SET_DEST (other_set); + if (REG_P (dest) + && REGNO (dest) == other_def->regno () + && REG_NREGS (dest) == 1 + && parallelize_insns (cc_def, cc_set, other_def, other_set)) + return; + } +} + +// Run the pass on the current function. +void +cc_fusion::execute () +{ + // Initialization. + calculate_dominance_info (CDI_DOMINATORS); + df_analyze (); + crtl->ssa = new rtl_ssa::function_info (cfun); + + // Walk through all instructions that set CC. Look for a PTEST instruction + // that we can optimize. + // + // ??? The PTEST test isn't needed for correctness, but it ensures that the + // pass no effect on non-SVE code. + for (def_info *def : crtl->ssa->reg_defs (CC_REGNUM)) + if (rtx cc_set = optimizable_set (def->insn ())) + if (REG_P (SET_DEST (cc_set)) + && REGNO (SET_DEST (cc_set)) == CC_REGNUM + && GET_CODE (SET_SRC (cc_set)) == UNSPEC + && XINT (SET_SRC (cc_set), 1) == UNSPEC_PTEST) + optimize_cc_setter (def, cc_set); + + // Finalization. + crtl->ssa->perform_pending_updates (); + free_dominance_info (CDI_DOMINATORS); +} + +class pass_cc_fusion : public rtl_opt_pass +{ +public: + pass_cc_fusion (gcc::context *ctxt) + : rtl_opt_pass (pass_data_cc_fusion, ctxt) + {} + + // opt_pass methods: + virtual bool gate (function *) { return TARGET_SVE && optimize >= 2; } + virtual unsigned int execute (function *); +}; + +unsigned int +pass_cc_fusion::execute (function *) +{ + cc_fusion ().execute (); + return 0; +} + +} // end namespace + +// Create a new CC fusion pass instance. + +rtl_opt_pass * +make_pass_cc_fusion (gcc::context *ctxt) +{ + return new pass_cc_fusion (ctxt); +} diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 3aa13f6..de8fe9b 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -105,6 +105,7 @@ AARCH64_CORE("cortex-a76ae", cortexa76ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH AARCH64_CORE("cortex-a77", cortexa77, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, neoversen1, 0x41, 0xd0d, -1) AARCH64_CORE("cortex-a78", cortexa78, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd41, -1) AARCH64_CORE("cortex-a78ae", cortexa78ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd42, -1) +AARCH64_CORE("cortex-a78c", cortexa78c, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS | AARCH64_FL_PROFILE | AARCH64_FL_FLAGM | AARCH64_FL_PAUTH, neoversen1, 0x41, 0xd4b, -1) AARCH64_CORE("cortex-a65", cortexa65, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd06, -1) AARCH64_CORE("cortex-a65ae", cortexa65ae, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd43, -1) AARCH64_CORE("cortex-x1", cortexx1, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd44, -1) diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h index 8a98bf4..c309f88 100644 --- a/gcc/config/aarch64/aarch64-cost-tables.h +++ b/gcc/config/aarch64/aarch64-cost-tables.h @@ -1,6 +1,6 @@ /* RTX cost tables for AArch64. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -541,4 +541,107 @@ const struct cpu_cost_table tsv110_extra_costs = } }; +const struct cpu_cost_table a64fx_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + 0, /* shift. */ + 0, /* shift_reg. */ + COSTS_N_INSNS (1), /* arith_shift. */ + COSTS_N_INSNS (1), /* arith_shift_reg. */ + COSTS_N_INSNS (1), /* log_shift. */ + COSTS_N_INSNS (1), /* log_shift_reg. */ + 0, /* extend. */ + COSTS_N_INSNS (1), /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* rev. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (4), /* simple. */ + COSTS_N_INSNS (4), /* flag_setting. */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (5), /* add. */ + COSTS_N_INSNS (5), /* extend_add. */ + COSTS_N_INSNS (18) /* idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (4), /* simple. */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (5), /* add. */ + COSTS_N_INSNS (5), /* extend_add. */ + COSTS_N_INSNS (26) /* idiv. */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (4), /* load. */ + COSTS_N_INSNS (4), /* load_sign_extend. */ + COSTS_N_INSNS (5), /* ldrd. */ + COSTS_N_INSNS (4), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (4), /* loadf. */ + COSTS_N_INSNS (4), /* loadd. */ + COSTS_N_INSNS (5), /* load_unaligned. */ + 0, /* store. */ + 0, /* strd. */ + 0, /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + 0, /* storef. */ + 0, /* stored. */ + 0, /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (6), /* div. */ + COSTS_N_INSNS (1), /* mult. */ + COSTS_N_INSNS (1), /* mult_addsub. */ + COSTS_N_INSNS (2), /* fma. */ + COSTS_N_INSNS (1), /* addsub. */ + COSTS_N_INSNS (1), /* fpconst. */ + COSTS_N_INSNS (1), /* neg. */ + COSTS_N_INSNS (1), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (2), /* toint. */ + COSTS_N_INSNS (2), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (11), /* div. */ + COSTS_N_INSNS (1), /* mult. */ + COSTS_N_INSNS (1), /* mult_addsub. */ + COSTS_N_INSNS (2), /* fma. */ + COSTS_N_INSNS (1), /* addsub. */ + COSTS_N_INSNS (1), /* fpconst. */ + COSTS_N_INSNS (1), /* neg. */ + COSTS_N_INSNS (1), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (2), /* toint. */ + COSTS_N_INSNS (2), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* alu. */ + } +}; + #endif diff --git a/gcc/config/aarch64/aarch64-d.c b/gcc/config/aarch64/aarch64-d.c index 69efd8d..5c9b4fa 100644 --- a/gcc/config/aarch64/aarch64-d.c +++ b/gcc/config/aarch64/aarch64-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the AArch64 architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h index da5872c..e986149 100644 --- a/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc/config/aarch64/aarch64-elf-raw.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-elf.h b/gcc/config/aarch64/aarch64-elf.h index 0768565..60504ef 100644 --- a/gcc/config/aarch64/aarch64-elf.h +++ b/gcc/config/aarch64/aarch64-elf.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-errata.h b/gcc/config/aarch64/aarch64-errata.h index 08f6af0..7c70747 100644 --- a/gcc/config/aarch64/aarch64-errata.h +++ b/gcc/config/aarch64/aarch64-errata.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-freebsd.h b/gcc/config/aarch64/aarch64-freebsd.h index 68cfc44..e2dfe78 100644 --- a/gcc/config/aarch64/aarch64-freebsd.h +++ b/gcc/config/aarch64/aarch64-freebsd.h @@ -1,5 +1,5 @@ /* Definitions for AArch64 running FreeBSD - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index 34d3a57..d6be730 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md index 02d7a5b..b5b8b6d 100644 --- a/gcc/config/aarch64/aarch64-ldpstp.md +++ b/gcc/config/aarch64/aarch64-ldpstp.md @@ -1,5 +1,5 @@ ;; AArch64 ldp/stp peephole optimizations. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h index b1d1f67..7f2529a 100644 --- a/gcc/config/aarch64/aarch64-linux.h +++ b/gcc/config/aarch64/aarch64-linux.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index f304992..1a07bc1 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-netbsd.h b/gcc/config/aarch64/aarch64-netbsd.h index 77fb0f8..76cfc00 100644 --- a/gcc/config/aarch64/aarch64-netbsd.h +++ b/gcc/config/aarch64/aarch64-netbsd.h @@ -1,5 +1,5 @@ /* Definitions for AArch64 running NetBSD - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index ec45301..579328c 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -229,4 +229,7 @@ AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \ /* Enabling/Disabling "flagm" only changes "flagm". */ AARCH64_OPT_EXTENSION("flagm", AARCH64_FL_FLAGM, 0, 0, false, "flagm") +/* Enabling/Disabling "pauth" only changes "pauth". */ +AARCH64_OPT_EXTENSION("pauth", AARCH64_FL_PAUTH, 0, 0, false, "paca pacg") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index ee7bed3..af3b736 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-passes.def b/gcc/config/aarch64/aarch64-passes.def index 223f785..0b773d2 100644 --- a/gcc/config/aarch64/aarch64-passes.def +++ b/gcc/config/aarch64/aarch64-passes.def @@ -1,5 +1,5 @@ /* AArch64-specific passes declarations. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -22,3 +22,4 @@ INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering); INSERT_PASS_BEFORE (pass_reorder_blocks, 1, pass_track_speculation); INSERT_PASS_AFTER (pass_machine_reorg, 1, pass_tag_collision_avoidance); INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_insert_bti); +INSERT_PASS_AFTER (pass_if_after_combine, 1, pass_cc_fusion); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 2aa3f1f..ff87ced 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -192,6 +192,29 @@ struct cpu_regmove_cost const int FP2FP; }; +struct simd_vec_cost +{ + const int int_stmt_cost; /* Cost of any int vector operation, + excluding load, store, permute, + vector-to-scalar and + scalar-to-vector operation. */ + const int fp_stmt_cost; /* Cost of any fp vector operation, + excluding load, store, permute, + vector-to-scalar and + scalar-to-vector operation. */ + const int permute_cost; /* Cost of permute operation. */ + const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ + const int scalar_to_vec_cost; /* Cost of scalar-to-vector + operation. */ + const int align_load_cost; /* Cost of aligned vector load. */ + const int unalign_load_cost; /* Cost of unaligned vector load. */ + const int unalign_store_cost; /* Cost of unaligned vector store. */ + const int store_cost; /* Cost of vector store. */ +}; + +typedef struct simd_vec_cost advsimd_vec_cost; +typedef struct simd_vec_cost sve_vec_cost; + /* Cost for vector insn classes. */ struct cpu_vector_cost { @@ -201,24 +224,10 @@ struct cpu_vector_cost excluding load and store. */ const int scalar_load_cost; /* Cost of scalar load. */ const int scalar_store_cost; /* Cost of scalar store. */ - const int vec_int_stmt_cost; /* Cost of any int vector operation, - excluding load, store, permute, - vector-to-scalar and - scalar-to-vector operation. */ - const int vec_fp_stmt_cost; /* Cost of any fp vector operation, - excluding load, store, permute, - vector-to-scalar and - scalar-to-vector operation. */ - const int vec_permute_cost; /* Cost of permute operation. */ - const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ - const int scalar_to_vec_cost; /* Cost of scalar-to-vector - operation. */ - const int vec_align_load_cost; /* Cost of aligned vector load. */ - const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ - const int vec_unalign_store_cost; /* Cost of unaligned vector store. */ - const int vec_store_cost; /* Cost of vector store. */ const int cond_taken_branch_cost; /* Cost of taken branch. */ const int cond_not_taken_branch_cost; /* Cost of not taken branch. */ + const advsimd_vec_cost *advsimd; /* Cost of Advanced SIMD operations. */ + const sve_vec_cost *sve; /* Cost of SVE operations. */ }; /* Branch costs. */ @@ -781,6 +790,7 @@ rtl_opt_pass *make_pass_fma_steering (gcc::context *); rtl_opt_pass *make_pass_track_speculation (gcc::context *); rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *); rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); +rtl_opt_pass *make_pass_cc_fusion (gcc::context *ctxt); poly_uint64 aarch64_regmode_natural_size (machine_mode); diff --git a/gcc/config/aarch64/aarch64-simd-builtin-types.def b/gcc/config/aarch64/aarch64-simd-builtin-types.def index e885755..21145e8 100644 --- a/gcc/config/aarch64/aarch64-simd-builtin-types.def +++ b/gcc/config/aarch64/aarch64-simd-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin AdvSIMD types. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index b70056a..48e481c 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -43,31 +43,31 @@ help describe the attributes (for example, pure) for the intrinsic function. */ - BUILTIN_VDC (COMBINE, combine, 0, ALL) - VAR1 (COMBINEP, combine, 0, ALL, di) + BUILTIN_VDC (COMBINE, combine, 0, AUTO_FP) + VAR1 (COMBINEP, combine, 0, NONE, di) BUILTIN_VB (BINOP, pmul, 0, NONE) BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, FP) BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP) BUILTIN_VD_BHSI (BINOP, addp, 0, NONE) VAR1 (UNOP, addp, 0, NONE, di) - BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, ALL) - BUILTIN_VDQ_BHSI (UNOP, clz, 2, ALL) - BUILTIN_VS (UNOP, ctz, 2, ALL) - BUILTIN_VB (UNOP, popcount, 2, ALL) + BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, NONE) + BUILTIN_VDQ_BHSI (UNOP, clz, 2, NONE) + BUILTIN_VS (UNOP, ctz, 2, NONE) + BUILTIN_VB (UNOP, popcount, 2, NONE) /* Implemented by aarch64_<sur>q<r>shl<mode>. */ - BUILTIN_VSDQ_I (BINOP, sqshl, 0, ALL) - BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0, ALL) - BUILTIN_VSDQ_I (BINOP, sqrshl, 0, ALL) - BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0, ALL) + BUILTIN_VSDQ_I (BINOP, sqshl, 0, NONE) + BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0, NONE) + BUILTIN_VSDQ_I (BINOP, sqrshl, 0, NONE) + BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0, NONE) /* Implemented by aarch64_<su_optab><optab><mode>. */ - BUILTIN_VSDQ_I (BINOP, sqadd, 0, ALL) - BUILTIN_VSDQ_I (BINOPU, uqadd, 0, ALL) - BUILTIN_VSDQ_I (BINOP, sqsub, 0, ALL) - BUILTIN_VSDQ_I (BINOPU, uqsub, 0, ALL) + BUILTIN_VSDQ_I (BINOP, sqadd, 0, NONE) + BUILTIN_VSDQ_I (BINOPU, uqadd, 0, NONE) + BUILTIN_VSDQ_I (BINOP, sqsub, 0, NONE) + BUILTIN_VSDQ_I (BINOPU, uqsub, 0, NONE) /* Implemented by aarch64_<sur>qadd<mode>. */ - BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0, ALL) - BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, ALL) + BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0, NONE) + BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, NONE) /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ BUILTIN_VDC (GETREG, get_dregoi, 0, AUTO_FP) @@ -91,21 +91,21 @@ VAR1 (SETREGP, set_qregci, 0, AUTO_FP, v2di) VAR1 (SETREGP, set_qregxi, 0, AUTO_FP, v2di) /* Implemented by aarch64_ld1x2<VQ:mode>. */ - BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, ALL) + BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, LOAD) /* Implemented by aarch64_ld1x2<VDC:mode>. */ - BUILTIN_VDC (LOADSTRUCT, ld1x2, 0, ALL) + BUILTIN_VDC (LOADSTRUCT, ld1x2, 0, LOAD) /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ - BUILTIN_VDC (LOADSTRUCT, ld2, 0, ALL) - BUILTIN_VDC (LOADSTRUCT, ld3, 0, ALL) - BUILTIN_VDC (LOADSTRUCT, ld4, 0, ALL) + BUILTIN_VDC (LOADSTRUCT, ld2, 0, LOAD) + BUILTIN_VDC (LOADSTRUCT, ld3, 0, LOAD) + BUILTIN_VDC (LOADSTRUCT, ld4, 0, LOAD) /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ - BUILTIN_VQ (LOADSTRUCT, ld2, 0, ALL) - BUILTIN_VQ (LOADSTRUCT, ld3, 0, ALL) - BUILTIN_VQ (LOADSTRUCT, ld4, 0, ALL) + BUILTIN_VQ (LOADSTRUCT, ld2, 0, LOAD) + BUILTIN_VQ (LOADSTRUCT, ld3, 0, LOAD) + BUILTIN_VQ (LOADSTRUCT, ld4, 0, LOAD) /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */ - BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0, ALL) - BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0, ALL) - BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0, ALL) + BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0, LOAD) + BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0, LOAD) + BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0, LOAD) /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */ BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0, ALL) BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0, ALL) @@ -148,6 +148,38 @@ BUILTIN_VDQ_BHSI (BINOP, uhsub, 0, NONE) BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, NONE) BUILTIN_VDQ_BHSI (BINOP, urhadd, 0, NONE) + + /* Implemented by aarch64_<su>addlv<mode>. */ + BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE) + BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE) + + /* Implemented by aarch64_<su>abd<mode>. */ + BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE) + BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE) + + /* Implemented by aarch64_<su>aba<mode>. */ + BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE) + BUILTIN_VDQ_BHSI (TERNOPU, uaba, 0, NONE) + + BUILTIN_VDQV_S (BINOP, sadalp, 0, NONE) + BUILTIN_VDQV_S (BINOPU, uadalp, 0, NONE) + + /* Implemented by aarch64_<sur>abal<mode>. */ + BUILTIN_VD_BHSI (TERNOP, sabal, 0, NONE) + BUILTIN_VD_BHSI (TERNOPU, uabal, 0, NONE) + + /* Implemented by aarch64_<sur>abal2<mode>. */ + BUILTIN_VQW (TERNOP, sabal2, 0, NONE) + BUILTIN_VQW (TERNOPU, uabal2, 0, NONE) + + /* Implemented by aarch64_<sur>abdl<mode>. */ + BUILTIN_VD_BHSI (BINOP, sabdl, 0, NONE) + BUILTIN_VD_BHSI (BINOPU, uabdl, 0, NONE) + + /* Implemented by aarch64_<sur>abdl2<mode>. */ + BUILTIN_VQW (BINOP, sabdl2, 0, NONE) + BUILTIN_VQW (BINOPU, uabdl2, 0, NONE) + /* Implemented by aarch64_<sur><addsub>hn<mode>. */ BUILTIN_VQN (BINOP, addhn, 0, NONE) BUILTIN_VQN (BINOP, subhn, 0, NONE) @@ -159,35 +191,93 @@ BUILTIN_VQN (TERNOP, raddhn2, 0, NONE) BUILTIN_VQN (TERNOP, rsubhn2, 0, NONE) - BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, ALL) + /* Implemented by aarch64_<us>xtl<mode>. */ + BUILTIN_VQN (UNOP, sxtl, 0, NONE) + BUILTIN_VQN (UNOPU, uxtl, 0, NONE) + + /* Implemented by aarch64_xtn<mode>. */ + BUILTIN_VQN (UNOP, xtn, 0, NONE) + + /* Implemented by aarch64_mla<mode>. */ + BUILTIN_VDQ_BHSI (TERNOP, mla, 0, NONE) + /* Implemented by aarch64_mla_n<mode>. */ + BUILTIN_VDQHS (TERNOP, mla_n, 0, NONE) + + /* Implemented by aarch64_mls<mode>. */ + BUILTIN_VDQ_BHSI (TERNOP, mls, 0, NONE) + /* Implemented by aarch64_mls_n<mode>. */ + BUILTIN_VDQHS (TERNOP, mls_n, 0, NONE) + + /* Implemented by aarch64_shrn<mode>". */ + BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE) + + /* Implemented by aarch64_shrn2<mode>. */ + BUILTIN_VQN (SHIFTACC, shrn2, 0, NONE) + + /* Implemented by aarch64_rshrn<mode>". */ + BUILTIN_VQN (SHIFTIMM, rshrn, 0, NONE) + + /* Implemented by aarch64_rshrn2<mode>. */ + BUILTIN_VQN (SHIFTACC, rshrn2, 0, NONE) + + /* Implemented by aarch64_<su>mlsl<mode>. */ + BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE) + BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE) + + /* Implemented by aarch64_<su>mlsl_n<mode>. */ + BUILTIN_VD_HSI (TERNOP, smlsl_n, 0, NONE) + BUILTIN_VD_HSI (TERNOPU, umlsl_n, 0, NONE) + + /* Implemented by aarch64_<su>mlal<mode>. */ + BUILTIN_VD_BHSI (TERNOP, smlal, 0, NONE) + BUILTIN_VD_BHSI (TERNOPU, umlal, 0, NONE) + + /* Implemented by aarch64_<su>mlal_n<mode>. */ + BUILTIN_VD_HSI (TERNOP, smlal_n, 0, NONE) + BUILTIN_VD_HSI (TERNOPU, umlal_n, 0, NONE) + + /* Implemented by aarch64_<su>mlsl_hi<mode>. */ + BUILTIN_VQW (TERNOP, smlsl_hi, 0, NONE) + BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE) + + BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE) + + /* Implemented by aarch64_sqxtun2<mode>. */ + BUILTIN_VQN (BINOP_UUS, sqxtun2, 0, NONE) + /* Implemented by aarch64_<sur>qmovn<mode>. */ - BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, ALL) - BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0, ALL) + BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, NONE) + BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0, NONE) + + /* Implemented by aarch64_<su>qxtn2<mode>. */ + BUILTIN_VQN (BINOP, sqxtn2, 0, NONE) + BUILTIN_VQN (BINOPU, uqxtn2, 0, NONE) + /* Implemented by aarch64_s<optab><mode>. */ - BUILTIN_VSDQ_I (UNOP, sqabs, 0, ALL) - BUILTIN_VSDQ_I (UNOP, sqneg, 0, ALL) + BUILTIN_VSDQ_I (UNOP, sqabs, 0, NONE) + BUILTIN_VSDQ_I (UNOP, sqneg, 0, NONE) /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ - BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0, ALL) - BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0, ALL) + BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0, NONE) + BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0, NONE) /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */ - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0, ALL) - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0, ALL) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0, NONE) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0, NONE) /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */ - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0, ALL) - BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0, ALL) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0, NONE) + BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0, NONE) /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ - BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0, ALL) - BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0, ALL) - - BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0, ALL) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0, ALL) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0, ALL) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0, ALL) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0, ALL) - BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0, ALL) - BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0, ALL) - BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0, ALL) + BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0, NONE) + BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0, NONE) + + BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0, NONE) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0, NONE) + BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0, NONE) + BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0, NONE) + BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0, NONE) BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0, NONE) BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0, NONE) @@ -195,51 +285,59 @@ BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10, NONE) BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10, NONE) - BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, ALL) - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, ALL) - BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, ALL) - BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, ALL) - BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, ALL) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, ALL) - BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, ALL) - BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, ALL) - - BUILTIN_VSD_HSI (BINOP, sqdmull, 0, ALL) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, ALL) - BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, ALL) - BUILTIN_VD_HSI (BINOP, sqdmull_n, 0, ALL) - BUILTIN_VQ_HSI (BINOP, sqdmull2, 0, ALL) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0, ALL) - BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0, ALL) - BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0, ALL) + BUILTIN_VD_HSI (BINOP, smull_n, 0, NONE) + BUILTIN_VD_HSI (BINOPU, umull_n, 0, NONE) + + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, NONE) + BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, NONE) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, NONE) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, NONE) + BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, NONE) + + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOP_LANE, vec_smlsl_laneq_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_lane_, 0, NONE) + BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlsl_laneq_, 0, NONE) + + BUILTIN_VSD_HSI (BINOP, sqdmull, 0, NONE) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, NONE) + BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0, NONE) + BUILTIN_VD_HSI (BINOP, sqdmull_n, 0, NONE) + BUILTIN_VQ_HSI (BINOP, sqdmull2, 0, NONE) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0, NONE) + BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0, NONE) + BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0, NONE) /* Implemented by aarch64_sq<r>dmulh<mode>. */ - BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0, ALL) - BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0, ALL) + BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0, NONE) + BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0, NONE) /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0, ALL) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0, ALL) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0, ALL) - BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0, ALL) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0, NONE) - BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, ALL) + BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE) /* Implemented by aarch64_<sur>shl<mode>. */ - BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, ALL) - BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, ALL) - BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, ALL) - BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, ALL) + BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, NONE) + BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, NONE) /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>. */ BUILTIN_VB (TERNOP, sdot, 0, NONE) BUILTIN_VB (TERNOPU, udot, 0, NONE) BUILTIN_VB (TERNOP_SSUS, usdot, 0, NONE) - BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, ALL) - BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, ALL) - BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, ALL) - BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, ALL) - BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, ALL) - BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, ALL) - BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, ALL) - BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, ALL) + BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, NONE) + BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, NONE) + BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, NONE) + BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, NONE) + BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, NONE) + BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, NONE) + BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, NONE) + BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, NONE) /* Implemented by aarch64_fcadd<rot><mode>. */ BUILTIN_VHSDF (BINOP, fcadd90, 0, FP) @@ -250,41 +348,41 @@ BUILTIN_VHSDF (TERNOP, fcmla90, 0, FP) BUILTIN_VHSDF (TERNOP, fcmla180, 0, FP) BUILTIN_VHSDF (TERNOP, fcmla270, 0, FP) - BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, ALL) - BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, ALL) - BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0, ALL) - BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0, ALL) - - BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0, ALL) - BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0, ALL) - BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0, ALL) - BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0, ALL) - - BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, ALL) - VAR1 (SHIFTIMM, ashr_simd, 0, ALL, di) - BUILTIN_VDQ_I (SHIFTIMM, lshr, 3, ALL) - VAR1 (USHIFTIMM, lshr_simd, 0, ALL, di) + BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, FP) + BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, FP) + BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0, FP) + BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0, FP) + + BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0, FP) + BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0, FP) + BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0, FP) + BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0, FP) + + BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE) + VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di) + BUILTIN_VDQ_I (SHIFTIMM, lshr, 3, NONE) + VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di) /* Implemented by aarch64_<sur>shr_n<mode>. */ - BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, ALL) - BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, ALL) + BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, NONE) + BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, NONE) /* Implemented by aarch64_<sur>sra_n<mode>. */ - BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, ALL) - BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, ALL) - BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, ALL) - BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, ALL) + BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, NONE) + BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, NONE) + BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, NONE) + BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, NONE) /* Implemented by aarch64_<sur>shll_n<mode>. */ - BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, ALL) - BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, ALL) + BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, NONE) + BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, NONE) /* Implemented by aarch64_<sur>shll2_n<mode>. */ - BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, ALL) - BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, ALL) + BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, NONE) + BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, NONE) /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ - BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0, ALL) - BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0, ALL) - BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0, ALL) - BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0, ALL) - BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0, ALL) - BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0, ALL) + BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0, NONE) + BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0, NONE) + BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0, NONE) + BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0, NONE) + BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0, NONE) + BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0, NONE) /* Implemented by aarch64_<sur>q<r>shr<u>n2_n<mode>. */ BUILTIN_VQN (SHIFT2IMM_UUSS, sqshrun2_n, 0, NONE) BUILTIN_VQN (SHIFT2IMM_UUSS, sqrshrun2_n, 0, NONE) @@ -293,15 +391,22 @@ BUILTIN_VQN (SHIFT2IMM, sqrshrn2_n, 0, NONE) BUILTIN_VQN (USHIFT2IMM, uqrshrn2_n, 0, NONE) /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ - BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, ALL) - BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, ALL) - BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, ALL) - VAR2 (SHIFTINSERTP, ssli_n, 0, ALL, di, v2di) - BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, ALL) + BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, NONE) + BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, NONE) + BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, NONE) + VAR2 (SHIFTINSERTP, ssli_n, 0, NONE, di, v2di) + BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, NONE) /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ - BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0, ALL) - BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0, ALL) - BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0, ALL) + BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0, NONE) + BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0, NONE) + BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0, NONE) + + /* Implemented by aarch64_xtn2<mode>. */ + BUILTIN_VQN (UNOP, xtn2, 0, NONE) + + /* Implemented by vec_unpack<su>_hi_<mode>. */ + BUILTIN_VQW (UNOP, vec_unpacks_hi_, 10, NONE) + BUILTIN_VQW (UNOPU, vec_unpacku_hi_, 10, NONE) /* Implemented by aarch64_reduc_plus_<mode>. */ BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, NONE) @@ -449,18 +554,18 @@ VAR1 (UNOP, floatunsv4si, 2, FP, v4sf) VAR1 (UNOP, floatunsv2di, 2, FP, v2df) - VAR5 (UNOPU, bswap, 2, ALL, v4hi, v8hi, v2si, v4si, v2di) + VAR5 (UNOPU, bswap, 2, NONE, v4hi, v8hi, v2si, v4si, v2di) - BUILTIN_VB (UNOP, rbit, 0, ALL) + BUILTIN_VB (UNOP, rbit, 0, NONE) /* Implemented by aarch64_<PERMUTE:perm_insn><mode>. */ - BUILTIN_VALL (BINOP, zip1, 0, ALL) - BUILTIN_VALL (BINOP, zip2, 0, ALL) - BUILTIN_VALL (BINOP, uzp1, 0, ALL) - BUILTIN_VALL (BINOP, uzp2, 0, ALL) - BUILTIN_VALL (BINOP, trn1, 0, ALL) - BUILTIN_VALL (BINOP, trn2, 0, ALL) + BUILTIN_VALL (BINOP, zip1, 0, AUTO_FP) + BUILTIN_VALL (BINOP, zip2, 0, AUTO_FP) + BUILTIN_VALL (BINOP, uzp1, 0, AUTO_FP) + BUILTIN_VALL (BINOP, uzp2, 0, AUTO_FP) + BUILTIN_VALL (BINOP, trn1, 0, AUTO_FP) + BUILTIN_VALL (BINOP, trn2, 0, AUTO_FP) BUILTIN_GPF_F16 (UNOP, frecpe, 0, FP) BUILTIN_GPF_F16 (UNOP, frecpx, 0, FP) @@ -485,7 +590,7 @@ BUILTIN_VDF (UNOP, float_truncate_lo_, 0, FP) /* Implemented by aarch64_ld1<VALL_F16:mode>. */ - BUILTIN_VALL_F16 (LOAD1, ld1, 0, ALL) + BUILTIN_VALL_F16 (LOAD1, ld1, 0, LOAD) VAR1(STORE1P, ld1, 0, ALL, v2di) /* Implemented by aarch64_st1<VALL_F16:mode>. */ @@ -493,10 +598,10 @@ VAR1 (STORE1P, st1, 0, STORE, v2di) /* Implemented by aarch64_ld1x3<VALLDIF:mode>. */ - BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0, ALL) + BUILTIN_VALLDIF (LOADSTRUCT, ld1x3, 0, LOAD) /* Implemented by aarch64_ld1x4<VALLDIF:mode>. */ - BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0, ALL) + BUILTIN_VALLDIF (LOADSTRUCT, ld1x4, 0, LOAD) /* Implemented by aarch64_st1x2<VALLDIF:mode>. */ BUILTIN_VALLDIF (STORESTRUCT, st1x2, 0, STORE) @@ -515,10 +620,10 @@ VAR1 (TERNOP, fnma, 4, FP, hf) /* Implemented by aarch64_simd_bsl<mode>. */ - BUILTIN_VDQQH (BSL_P, simd_bsl, 0, ALL) - VAR2 (BSL_P, simd_bsl,0, ALL, di, v2di) - BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0, ALL) - BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, ALL) + BUILTIN_VDQQH (BSL_P, simd_bsl, 0, NONE) + VAR2 (BSL_P, simd_bsl,0, NONE, di, v2di) + BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0, NONE) + BUILTIN_VALLDIF (BSL_S, simd_bsl, 0, AUTO_FP) /* Implemented by aarch64_crypto_aes<op><mode>. */ VAR1 (BINOPU, crypto_aese, 0, NONE, v16qi) @@ -571,28 +676,28 @@ /* Builtins for ARMv8.1-A Adv.SIMD instructions. */ /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */ - BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0, ALL) - BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0, ALL) + BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0, NONE) + BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0, NONE) /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */ - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0, ALL) - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0, ALL) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0, NONE) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0, NONE) /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */ - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0, ALL) - BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0, ALL) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0, NONE) + BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0, NONE) /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */ - BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3, ALL) - BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3, ALL) - BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3, ALL) - BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3, ALL) - VAR1 (SHIFTIMM, scvtfsi, 3, ALL, hf) - VAR1 (SHIFTIMM, scvtfdi, 3, ALL, hf) - VAR1 (FCVTIMM_SUS, ucvtfsi, 3, ALL, hf) - VAR1 (FCVTIMM_SUS, ucvtfdi, 3, ALL, hf) - BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3, ALL) - BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3, ALL) + BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3, FP) + BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3, FP) + BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3, FP) + BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3, FP) + VAR1 (SHIFTIMM, scvtfsi, 3, FP, hf) + VAR1 (SHIFTIMM, scvtfdi, 3, FP, hf) + VAR1 (FCVTIMM_SUS, ucvtfsi, 3, FP, hf) + VAR1 (FCVTIMM_SUS, ucvtfdi, 3, FP, hf) + BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3, FP) + BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3, FP) /* Implemented by aarch64_rsqrte<mode>. */ BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0, FP) @@ -600,6 +705,9 @@ /* Implemented by aarch64_rsqrts<mode>. */ BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0, FP) + /* Implemented by aarch64_ursqrte<mode>. */ + BUILTIN_VDQ_SI (UNOPU, ursqrte, 0, NONE) + /* Implemented by fabd<mode>3. */ BUILTIN_VHSDF_HSDF (BINOP, fabd, 3, FP) @@ -662,15 +770,15 @@ /* Implemented by aarch64_crypto_sha512su1qv2di. */ VAR1 (TERNOPU, crypto_sha512su1q, 0, NONE, v2di) /* Implemented by eor3q<mode>4. */ - BUILTIN_VQ_I (TERNOPU, eor3q, 4, ALL) - BUILTIN_VQ_I (TERNOP, eor3q, 4, ALL) + BUILTIN_VQ_I (TERNOPU, eor3q, 4, NONE) + BUILTIN_VQ_I (TERNOP, eor3q, 4, NONE) /* Implemented by aarch64_rax1qv2di. */ - VAR1 (BINOPU, rax1q, 0, ALL, v2di) + VAR1 (BINOPU, rax1q, 0, NONE, v2di) /* Implemented by aarch64_xarqv2di. */ - VAR1 (TERNOPUI, xarq, 0, ALL, v2di) + VAR1 (TERNOPUI, xarq, 0, NONE, v2di) /* Implemented by bcaxq<mode>4. */ - BUILTIN_VQ_I (TERNOPU, bcaxq, 4, ALL) - BUILTIN_VQ_I (TERNOP, bcaxq, 4, ALL) + BUILTIN_VQ_I (TERNOPU, bcaxq, 4, NONE) + BUILTIN_VQ_I (TERNOP, bcaxq, 4, NONE) /* Implemented by aarch64_fml<f16mac1>l<f16quad>_low<mode>. */ VAR1 (TERNOP, fmlal_low, 0, FP, v2sf) @@ -683,29 +791,29 @@ VAR1 (TERNOP, fmlalq_high, 0, FP, v4sf) VAR1 (TERNOP, fmlslq_high, 0, FP, v4sf) /* Implemented by aarch64_fml<f16mac1>l_lane_lowv2sf. */ - VAR1 (QUADOP_LANE, fmlal_lane_low, 0, ALL, v2sf) - VAR1 (QUADOP_LANE, fmlsl_lane_low, 0, ALL, v2sf) + VAR1 (QUADOP_LANE, fmlal_lane_low, 0, FP, v2sf) + VAR1 (QUADOP_LANE, fmlsl_lane_low, 0, FP, v2sf) /* Implemented by aarch64_fml<f16mac1>l_laneq_lowv2sf. */ - VAR1 (QUADOP_LANE, fmlal_laneq_low, 0, ALL, v2sf) - VAR1 (QUADOP_LANE, fmlsl_laneq_low, 0, ALL, v2sf) + VAR1 (QUADOP_LANE, fmlal_laneq_low, 0, FP, v2sf) + VAR1 (QUADOP_LANE, fmlsl_laneq_low, 0, FP, v2sf) /* Implemented by aarch64_fml<f16mac1>lq_lane_lowv4sf. */ - VAR1 (QUADOP_LANE, fmlalq_lane_low, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, fmlslq_lane_low, 0, ALL, v4sf) + VAR1 (QUADOP_LANE, fmlalq_lane_low, 0, FP, v4sf) + VAR1 (QUADOP_LANE, fmlslq_lane_low, 0, FP, v4sf) /* Implemented by aarch64_fml<f16mac1>lq_laneq_lowv4sf. */ - VAR1 (QUADOP_LANE, fmlalq_laneq_low, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, fmlslq_laneq_low, 0, ALL, v4sf) + VAR1 (QUADOP_LANE, fmlalq_laneq_low, 0, FP, v4sf) + VAR1 (QUADOP_LANE, fmlslq_laneq_low, 0, FP, v4sf) /* Implemented by aarch64_fml<f16mac1>l_lane_highv2sf. */ - VAR1 (QUADOP_LANE, fmlal_lane_high, 0, ALL, v2sf) - VAR1 (QUADOP_LANE, fmlsl_lane_high, 0, ALL, v2sf) + VAR1 (QUADOP_LANE, fmlal_lane_high, 0, FP, v2sf) + VAR1 (QUADOP_LANE, fmlsl_lane_high, 0, FP, v2sf) /* Implemented by aarch64_fml<f16mac1>l_laneq_highv2sf. */ - VAR1 (QUADOP_LANE, fmlal_laneq_high, 0, ALL, v2sf) - VAR1 (QUADOP_LANE, fmlsl_laneq_high, 0, ALL, v2sf) + VAR1 (QUADOP_LANE, fmlal_laneq_high, 0, FP, v2sf) + VAR1 (QUADOP_LANE, fmlsl_laneq_high, 0, FP, v2sf) /* Implemented by aarch64_fml<f16mac1>lq_lane_highv4sf. */ - VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, ALL, v4sf) + VAR1 (QUADOP_LANE, fmlalq_lane_high, 0, FP, v4sf) + VAR1 (QUADOP_LANE, fmlslq_lane_high, 0, FP, v4sf) /* Implemented by aarch64_fml<f16mac1>lq_laneq_highv4sf. */ - VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, ALL, v4sf) + VAR1 (QUADOP_LANE, fmlalq_laneq_high, 0, FP, v4sf) + VAR1 (QUADOP_LANE, fmlslq_laneq_high, 0, FP, v4sf) /* Implemented by aarch64_<frintnzs_op><mode>. */ BUILTIN_VSFDF (UNOP, frint32z, 0, FP) @@ -715,8 +823,8 @@ /* Implemented by aarch64_bfdot{_lane}{q}<mode>. */ VAR2 (TERNOP, bfdot, 0, AUTO_FP, v2sf, v4sf) - VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, ALL, v2sf, v4sf) - VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, ALL, v2sf, v4sf) + VAR2 (QUADOP_LANE_PAIR, bfdot_lane, 0, AUTO_FP, v2sf, v4sf) + VAR2 (QUADOP_LANE_PAIR, bfdot_laneq, 0, AUTO_FP, v2sf, v4sf) /* Implemented by aarch64_bfmmlaqv4sf */ VAR1 (TERNOP, bfmmlaq, 0, AUTO_FP, v4sf) @@ -724,10 +832,10 @@ /* Implemented by aarch64_bfmlal<bt>{_lane{q}}v4sf */ VAR1 (TERNOP, bfmlalb, 0, FP, v4sf) VAR1 (TERNOP, bfmlalt, 0, FP, v4sf) - VAR1 (QUADOP_LANE, bfmlalb_lane, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, bfmlalt_lane, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, ALL, v4sf) - VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, ALL, v4sf) + VAR1 (QUADOP_LANE, bfmlalb_lane, 0, FP, v4sf) + VAR1 (QUADOP_LANE, bfmlalt_lane, 0, FP, v4sf) + VAR1 (QUADOP_LANE, bfmlalb_lane_q, 0, FP, v4sf) + VAR1 (QUADOP_LANE, bfmlalt_lane_q, 0, FP, v4sf) /* Implemented by aarch64_vget_lo/hi_halfv8bf. */ VAR1 (UNOP, vget_lo_half, 0, AUTO_FP, v8bf) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 68baf41..767d673 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 AdvSIMD architecture. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -449,6 +449,14 @@ [(set_attr "type" "neon_fcadd")] ) +(define_expand "cadd<rot><mode>3" + [(set (match_operand:VHSDF 0 "register_operand") + (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand") + (match_operand:VHSDF 2 "register_operand")] + FCADD))] + "TARGET_COMPLEX && !BYTES_BIG_ENDIAN" +) + (define_insn "aarch64_fcmla<rot><mode>" [(set (match_operand:VHSDF 0 "register_operand" "=w") (plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0") @@ -508,6 +516,44 @@ [(set_attr "type" "neon_fcmla")] ) +;; The complex mla/mls operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cml<fcmac1><conj_op><mode>4" + [(set (match_operand:VHSDF 0 "register_operand") + (plus:VHSDF (match_operand:VHSDF 1 "register_operand") + (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand") + (match_operand:VHSDF 3 "register_operand")] + FCMLA_OP)))] + "TARGET_COMPLEX && !BYTES_BIG_ENDIAN" +{ + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn (gen_aarch64_fcmla<rotsplit1><mode> (tmp, operands[1], + operands[3], operands[2])); + emit_insn (gen_aarch64_fcmla<rotsplit2><mode> (operands[0], tmp, + operands[3], operands[2])); + DONE; +}) + +;; The complex mul operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cmul<conj_op><mode>3" + [(set (match_operand:VHSDF 0 "register_operand") + (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand") + (match_operand:VHSDF 2 "register_operand")] + FCMUL_OP))] + "TARGET_COMPLEX && !BYTES_BIG_ENDIAN" +{ + rtx tmp = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + rtx res1 = gen_reg_rtx (<MODE>mode); + emit_insn (gen_aarch64_fcmla<rotsplit1><mode> (res1, tmp, + operands[2], operands[1])); + emit_insn (gen_aarch64_fcmla<rotsplit2><mode> (operands[0], res1, + operands[2], operands[1])); + DONE; +}) + ;; These instructions map to the __builtins for the Dot Product operations. (define_insn "aarch64_<sur>dot<vsi2qi>" [(set (match_operand:VS 0 "register_operand" "=w") @@ -709,6 +755,14 @@ DONE; }) +(define_insn "aarch64_ursqrte<mode>" +[(set (match_operand:VDQ_SI 0 "register_operand" "=w") + (unspec:VDQ_SI [(match_operand:VDQ_SI 1 "register_operand" "w")] + UNSPEC_RSQRTE))] +"TARGET_SIMD" +"ursqrte\\t%<v>0<Vmtype>, %<v>1<Vmtype>" +[(set_attr "type" "neon_fp_rsqrte_<stype><q>")]) + (define_insn "*aarch64_mul3_elt_to_64v2df" [(set (match_operand:DF 0 "register_operand" "=w") (mult:DF @@ -758,7 +812,7 @@ ;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64. ;; Whereas SABD would return 192 (-64 signed) on the above example. ;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead. -(define_insn "aarch64_<su>abd<mode>_3" +(define_insn "aarch64_<su>abd<mode>" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (minus:VDQ_BHSI (USMAX:VDQ_BHSI @@ -772,34 +826,56 @@ [(set_attr "type" "neon_abd<q>")] ) -(define_insn "aarch64_<sur>abdl2<mode>_3" + +(define_insn "aarch64_<sur>abdl<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (unspec:<VWIDE> [(match_operand:VD_BHSI 1 "register_operand" "w") + (match_operand:VD_BHSI 2 "register_operand" "w")] + ABDL))] + "TARGET_SIMD" + "<sur>abdl\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "type" "neon_abd<q>")] +) + +(define_insn "aarch64_<sur>abdl2<mode>" [(set (match_operand:<VDBLW> 0 "register_operand" "=w") - (unspec:<VDBLW> [(match_operand:VDQV_S 1 "register_operand" "w") - (match_operand:VDQV_S 2 "register_operand" "w")] + (unspec:<VDBLW> [(match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 2 "register_operand" "w")] ABDL2))] "TARGET_SIMD" "<sur>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" [(set_attr "type" "neon_abd<q>")] ) -(define_insn "aarch64_<sur>abal<mode>_4" - [(set (match_operand:<VDBLW> 0 "register_operand" "=w") - (unspec:<VDBLW> [(match_operand:VDQV_S 1 "register_operand" "w") - (match_operand:VDQV_S 2 "register_operand" "w") - (match_operand:<VDBLW> 3 "register_operand" "0")] +(define_insn "aarch64_<sur>abal<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (unspec:<VWIDE> [(match_operand:VD_BHSI 2 "register_operand" "w") + (match_operand:VD_BHSI 3 "register_operand" "w") + (match_operand:<VWIDE> 1 "register_operand" "0")] ABAL))] "TARGET_SIMD" - "<sur>abal\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" + "<sur>abal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>" [(set_attr "type" "neon_arith_acc<q>")] ) -(define_insn "aarch64_<sur>adalp<mode>_3" +(define_insn "aarch64_<sur>abal2<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (unspec:<VWIDE> [(match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "register_operand" "w") + (match_operand:<VWIDE> 1 "register_operand" "0")] + ABAL2))] + "TARGET_SIMD" + "<sur>abal2\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>" + [(set_attr "type" "neon_arith_acc<q>")] +) + +(define_insn "aarch64_<sur>adalp<mode>" [(set (match_operand:<VDBLW> 0 "register_operand" "=w") - (unspec:<VDBLW> [(match_operand:VDQV_S 1 "register_operand" "w") - (match_operand:<VDBLW> 2 "register_operand" "0")] + (unspec:<VDBLW> [(match_operand:VDQV_S 2 "register_operand" "w") + (match_operand:<VDBLW> 1 "register_operand" "0")] ADALP))] "TARGET_SIMD" - "<sur>adalp\t%0.<Vwtype>, %1.<Vtype>" + "<sur>adalp\t%0.<Vwhalf>, %2.<Vtype>" [(set_attr "type" "neon_reduc_add<q>")] ) @@ -809,7 +885,7 @@ ;; operand 3 before copying that into the result operand 0. ;; Perform that with a sequence of: ;; UABDL2 tmp.8h, op1.16b, op2.16b -;; UABAL tmp.8h, op1.16b, op2.16b +;; UABAL tmp.8h, op1.8b, op2.8b ;; UADALP op3.4s, tmp.8h ;; MOV op0, op3 // should be eliminated in later passes. ;; @@ -834,31 +910,36 @@ { rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode)); rtx abd = gen_reg_rtx (V16QImode); - emit_insn (gen_aarch64_<sur>abdv16qi_3 (abd, operands[1], operands[2])); + emit_insn (gen_aarch64_<sur>abdv16qi (abd, operands[1], operands[2])); emit_insn (gen_aarch64_udotv16qi (operands[0], operands[3], abd, ones)); DONE; } rtx reduc = gen_reg_rtx (V8HImode); - emit_insn (gen_aarch64_<sur>abdl2v16qi_3 (reduc, operands[1], - operands[2])); - emit_insn (gen_aarch64_<sur>abalv16qi_4 (reduc, operands[1], - operands[2], reduc)); - emit_insn (gen_aarch64_<sur>adalpv8hi_3 (operands[3], reduc, - operands[3])); + emit_insn (gen_aarch64_<sur>abdl2v16qi (reduc, operands[1], + operands[2])); + emit_insn (gen_aarch64_<sur>abalv8qi (reduc, reduc, + gen_lowpart (V8QImode, operands[1]), + gen_lowpart (V8QImode, + operands[2]))); + emit_insn (gen_aarch64_<sur>adalpv8hi (operands[3], operands[3], reduc)); emit_move_insn (operands[0], operands[3]); DONE; } ) -(define_insn "aba<mode>_3" +(define_insn "aarch64_<su>aba<mode>" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") - (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI - (match_operand:VDQ_BHSI 1 "register_operand" "w") - (match_operand:VDQ_BHSI 2 "register_operand" "w"))) - (match_operand:VDQ_BHSI 3 "register_operand" "0")))] - "TARGET_SIMD" - "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>" + (plus:VDQ_BHSI (minus:VDQ_BHSI + (USMAX:VDQ_BHSI + (match_operand:VDQ_BHSI 2 "register_operand" "w") + (match_operand:VDQ_BHSI 3 "register_operand" "w")) + (<max_opp>:VDQ_BHSI + (match_dup 2) + (match_dup 3))) + (match_operand:VDQ_BHSI 1 "register_operand" "0")))] + "TARGET_SIMD" + "<su>aba\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>" [(set_attr "type" "neon_arith_acc<q>")] ) @@ -1335,15 +1416,16 @@ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")] ) -(define_insn "*aarch64_mla_elt_merge<mode>" - [(set (match_operand:VDQHS 0 "register_operand" "=w") +(define_insn "aarch64_mla_n<mode>" + [(set (match_operand:VDQHS 0 "register_operand" "=w") (plus:VDQHS - (mult:VDQHS (vec_duplicate:VDQHS - (match_operand:<VEL> 1 "register_operand" "<h_con>")) - (match_operand:VDQHS 2 "register_operand" "w")) - (match_operand:VDQHS 3 "register_operand" "0")))] + (mult:VDQHS + (vec_duplicate:VDQHS + (match_operand:<VEL> 3 "register_operand" "<h_con>")) + (match_operand:VDQHS 2 "register_operand" "w")) + (match_operand:VDQHS 1 "register_operand" "0")))] "TARGET_SIMD" - "mla\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]" + "mla\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[0]" [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")] ) @@ -1393,15 +1475,16 @@ [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")] ) -(define_insn "*aarch64_mls_elt_merge<mode>" +(define_insn "aarch64_mls_n<mode>" [(set (match_operand:VDQHS 0 "register_operand" "=w") (minus:VDQHS (match_operand:VDQHS 1 "register_operand" "0") - (mult:VDQHS (vec_duplicate:VDQHS - (match_operand:<VEL> 2 "register_operand" "<h_con>")) - (match_operand:VDQHS 3 "register_operand" "w"))))] + (mult:VDQHS + (vec_duplicate:VDQHS + (match_operand:<VEL> 3 "register_operand" "<h_con>")) + (match_operand:VDQHS 2 "register_operand" "w"))))] "TARGET_SIMD" - "mls\t%0.<Vtype>, %3.<Vtype>, %2.<Vetype>[0]" + "mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vetype>[0]" [(set_attr "type" "neon_mla_<Vetype>_scalar<q>")] ) @@ -1628,6 +1711,187 @@ DONE; }) +(define_insn "aarch64_shrn<mode>_insn_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm"))) + (match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "shrn\\t%0.<Vntype>, %1.<Vtype>, %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_shrn<mode>_insn_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero") + (truncate:<VNARROWQ> + (lshiftrt:VQN (match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm")))))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "shrn\\t%0.<Vntype>, %1.<Vtype>, %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_shrn<mode>" + [(set (match_operand:<VNARROWQ> 0 "register_operand") + (truncate:<VNARROWQ> + (lshiftrt:VQN (match_operand:VQN 1 "register_operand") + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>"))))] + "TARGET_SIMD" + { + operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode, + INTVAL (operands[2])); + rtx tmp = gen_reg_rtx (<VNARROWQ2>mode); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_shrn<mode>_insn_be (tmp, operands[1], + operands[2], CONST0_RTX (<VNARROWQ>mode))); + else + emit_insn (gen_aarch64_shrn<mode>_insn_le (tmp, operands[1], + operands[2], CONST0_RTX (<VNARROWQ>mode))); + + /* The intrinsic expects a narrow result, so emit a subreg that will get + optimized away as appropriate. */ + emit_move_insn (operands[0], lowpart_subreg (<VNARROWQ>mode, tmp, + <VNARROWQ2>mode)); + DONE; + } +) + +(define_insn "aarch64_rshrn<mode>_insn_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm") + ] UNSPEC_RSHRN) + (match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "rshrn\\t%0.<Vntype>, %1.<Vtype>, %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_rshrn<mode>_insn_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero") + (unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w") + (match_operand:VQN 2 "aarch64_simd_rshift_imm") + ] UNSPEC_RSHRN)))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "rshrn\\t%0.<Vntype>, %1.<Vtype>, %2" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_rshrn<mode>" + [(match_operand:<VNARROWQ> 0 "register_operand") + (match_operand:VQN 1 "register_operand") + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_<vn_mode>")] + "TARGET_SIMD" + { + operands[2] = aarch64_simd_gen_const_vector_dup (<MODE>mode, + INTVAL (operands[2])); + rtx tmp = gen_reg_rtx (<VNARROWQ2>mode); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_rshrn<mode>_insn_be (tmp, operands[1], + operands[2], CONST0_RTX (<VNARROWQ>mode))); + else + emit_insn (gen_aarch64_rshrn<mode>_insn_le (tmp, operands[1], + operands[2], CONST0_RTX (<VNARROWQ>mode))); + + /* The intrinsic expects a narrow result, so emit a subreg that will get + optimized away as appropriate. */ + emit_move_insn (operands[0], lowpart_subreg (<VNARROWQ>mode, tmp, + <VNARROWQ2>mode)); + DONE; + } +) + +(define_insn "aarch64_shrn2<mode>_insn_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 1 "register_operand" "0") + (truncate:<VNARROWQ> + (lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_rshift_imm")))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "shrn2\\t%0.<V2ntype>, %2.<Vtype>, %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_shrn2<mode>_insn_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_rshift_imm"))) + (match_operand:<VNARROWQ> 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "shrn2\\t%0.<V2ntype>, %2.<Vtype>, %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_shrn2<mode>" + [(match_operand:<VNARROWQ2> 0 "register_operand") + (match_operand:<VNARROWQ> 1 "register_operand") + (match_operand:VQN 2 "register_operand") + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_<vn_mode>")] + "TARGET_SIMD" + { + operands[3] = aarch64_simd_gen_const_vector_dup (<MODE>mode, + INTVAL (operands[3])); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_shrn2<mode>_insn_be (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_aarch64_shrn2<mode>_insn_le (operands[0], operands[1], + operands[2], operands[3])); + DONE; + } +) + +(define_insn "aarch64_rshrn2<mode>_insn_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 1 "register_operand" "0") + (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_rshift_imm")] UNSPEC_RSHRN)))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "rshrn2\\t%0.<V2ntype>, %2.<Vtype>, %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_rshrn2<mode>_insn_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (unspec:<VNARROWQ> [(match_operand:VQN 2 "register_operand" "w") + (match_operand:VQN 3 "aarch64_simd_rshift_imm")] UNSPEC_RSHRN) + (match_operand:<VNARROWQ> 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "rshrn2\\t%0.<V2ntype>, %2.<Vtype>, %3" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_rshrn2<mode>" + [(match_operand:<VNARROWQ2> 0 "register_operand") + (match_operand:<VNARROWQ> 1 "register_operand") + (match_operand:VQN 2 "register_operand") + (match_operand:SI 3 "aarch64_simd_shift_imm_offset_<vn_mode>")] + "TARGET_SIMD" + { + operands[3] = aarch64_simd_gen_const_vector_dup (<MODE>mode, + INTVAL (operands[3])); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_rshrn2<mode>_insn_be (operands[0], operands[1], + operands[2], operands[3])); + else + emit_insn (gen_aarch64_rshrn2<mode>_insn_le (operands[0], operands[1], + operands[2], operands[3])); + DONE; + } +) + ;; For quads. (define_insn "vec_pack_trunc_<mode>" @@ -1744,7 +2008,7 @@ [(set_attr "type" "neon_mla_<Vetype>_long")] ) -(define_insn "*aarch64_<su>mlsl_hi<mode>" +(define_insn "aarch64_<su>mlsl_hi<mode>_insn" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") @@ -1760,21 +2024,50 @@ [(set_attr "type" "neon_mla_<Vetype>_long")] ) -(define_insn "*aarch64_<su>mlal<mode>" +(define_expand "aarch64_<su>mlsl_hi<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (match_operand:<VWIDE> 1 "register_operand") + (ANY_EXTEND:<VWIDE>(match_operand:VQW 2 "register_operand")) + (match_operand:VQW 3 "register_operand")] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>mlsl_hi<mode>_insn (operands[0], operands[1], + operands[2], p, operands[3])); + DONE; +} +) + +(define_insn "aarch64_<su>mlal<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (plus:<VWIDE> + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> + (match_operand:VD_BHSI 2 "register_operand" "w")) + (ANY_EXTEND:<VWIDE> + (match_operand:VD_BHSI 3 "register_operand" "w"))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "<su>mlal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>" + [(set_attr "type" "neon_mla_<Vetype>_long")] +) + +(define_insn "aarch64_<su>mlal_n<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> (mult:<VWIDE> (ANY_EXTEND:<VWIDE> - (match_operand:VD_BHSI 1 "register_operand" "w")) + (match_operand:VD_HSI 2 "register_operand" "w")) (ANY_EXTEND:<VWIDE> - (match_operand:VD_BHSI 2 "register_operand" "w"))) - (match_operand:<VWIDE> 3 "register_operand" "0")))] + (vec_duplicate:VD_HSI + (match_operand:<VEL> 3 "register_operand" "<h_con>")))) + (match_operand:<VWIDE> 1 "register_operand" "0")))] "TARGET_SIMD" - "<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + "<su>mlal\t%0.<Vwtype>, %2.<Vtype>, %3.<Vetype>[0]" [(set_attr "type" "neon_mla_<Vetype>_long")] ) -(define_insn "*aarch64_<su>mlsl<mode>" +(define_insn "aarch64_<su>mlsl<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") @@ -1788,6 +2081,21 @@ [(set_attr "type" "neon_mla_<Vetype>_long")] ) +(define_insn "aarch64_<su>mlsl_n<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (match_operand:<VWIDE> 1 "register_operand" "0") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> + (match_operand:VD_HSI 2 "register_operand" "w")) + (ANY_EXTEND:<VWIDE> + (vec_duplicate:VD_HSI + (match_operand:<VEL> 3 "register_operand" "<h_con>"))))))] + "TARGET_SIMD" + "<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vetype>[0]" + [(set_attr "type" "neon_mla_<Vetype>_long")] +) + (define_insn "aarch64_simd_vec_<su>mult_lo_<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (mult:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:<VHALF> @@ -1873,6 +2181,19 @@ [(set_attr "type" "neon_mul_<Vetype>_scalar_long")] ) +(define_insn "aarch64_<su>mull_n<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> + (match_operand:VD_HSI 1 "register_operand" "w")) + (ANY_EXTEND:<VWIDE> + (vec_duplicate:<VCOND> + (match_operand:<VEL> 2 "register_operand" "<h_con>")))))] + "TARGET_SIMD" + "<su>mull\t%0.<Vwtype>, %1.<Vtype>, %2.<Vetype>[0]" + [(set_attr "type" "neon_mul_<Vetype>_scalar_long")] +) + ;; vmlal_lane_s16 intrinsics (define_insn "aarch64_vec_<su>mlal_lane<Qlane>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") @@ -1894,6 +2215,26 @@ [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] ) +(define_insn "aarch64_vec_<su>mlsl_lane<Qlane>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (match_operand:<VWIDE> 1 "register_operand" "0") + (mult:<VWIDE> + (ANY_EXTEND:<VWIDE> + (match_operand:<VCOND> 2 "register_operand" "w")) + (ANY_EXTEND:<VWIDE> + (vec_duplicate:<VCOND> + (vec_select:<VEL> + (match_operand:VDQHS 3 "register_operand" "<vwx>") + (parallel [(match_operand:SI 4 "immediate_operand" "i")])))))))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4])); + return "<su>mlsl\\t%0.<Vwtype>, %2.<Vcondtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_mla_<Vetype>_scalar_long")] +) + ;; FP vector operations. ;; AArch64 AdvSIMD supports single-precision (32-bit) and ;; double-precision (64-bit) floating-point data types and arithmetic as @@ -2487,6 +2828,15 @@ [(set_attr "type" "neon_reduc_add<q>")] ) +(define_insn "aarch64_<su>addlv<mode>" + [(set (match_operand:<VWIDE_S> 0 "register_operand" "=w") + (unspec:<VWIDE_S> [(match_operand:VDQV_L 1 "register_operand" "w")] + USADDLV))] + "TARGET_SIMD" + "<su>addl<vp>\\t%<Vwstype>0<Vwsuf>, %1.<Vtype>" + [(set_attr "type" "neon_reduc_add<q>")] +) + ;; ADDV with result zero-extended to SI/DImode (for popcount). (define_insn "aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>" [(set (match_operand:GPI 0 "register_operand" "=w") @@ -3249,7 +3599,9 @@ ;; Lane extraction of a value, neither sign nor zero extension ;; is guaranteed so upper bits should be considered undefined. ;; RTL uses GCC vector extension indices throughout so flip only for assembly. -(define_insn "aarch64_get_lane<mode>" +;; Extracting lane zero is split into a simple move when it is between SIMD +;; registers or a store. +(define_insn_and_split "aarch64_get_lane<mode>" [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=?r, w, Utv") (vec_select:<VEL> (match_operand:VALL_F16 1 "register_operand" "w, w, w") @@ -3269,6 +3621,12 @@ gcc_unreachable (); } } + "&& reload_completed + && ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0" + [(set (match_dup 0) (match_dup 1))] + { + operands[1] = aarch64_replace_reg_mode (operands[1], <VEL>mode); + } [(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")] ) @@ -3332,11 +3690,20 @@ (define_expand "aarch64_combine<mode>" [(match_operand:<VDBL> 0 "register_operand") (match_operand:VDC 1 "register_operand") - (match_operand:VDC 2 "register_operand")] + (match_operand:VDC 2 "aarch64_simd_reg_or_zero")] "TARGET_SIMD" { - aarch64_split_simd_combine (operands[0], operands[1], operands[2]); - + if (operands[2] == CONST0_RTX (<MODE>mode)) + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_combinez_be<mode> (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_combinez<mode> (operands[0], operands[1], + operands[2])); + } + else + aarch64_split_simd_combine (operands[0], operands[1], operands[2]); DONE; } ) @@ -3858,6 +4225,84 @@ [(set_attr "type" "neon_sat_shift_imm_narrow_q")] ) +(define_insn "aarch64_<su>qxtn2<mode>_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 1 "register_operand" "0") + (SAT_TRUNC:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "<su>qxtn2\\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_insn "aarch64_<su>qxtn2<mode>_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (SAT_TRUNC:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w")) + (match_operand:<VNARROWQ> 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "<su>qxtn2\\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_expand "aarch64_<su>qxtn2<mode>" + [(match_operand:<VNARROWQ2> 0 "register_operand") + (match_operand:<VNARROWQ> 1 "register_operand") + (SAT_TRUNC:<VNARROWQ> + (match_operand:VQN 2 "register_operand"))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_<su>qxtn2<mode>_be (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_<su>qxtn2<mode>_le (operands[0], operands[1], + operands[2])); + DONE; + } +) + +(define_insn "aarch64_sqxtun2<mode>_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 1 "register_operand" "0") + (unspec:<VNARROWQ> + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2)))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "sqxtun2\\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_insn "aarch64_sqxtun2<mode>_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (unspec:<VNARROWQ> + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2) + (match_operand:<VNARROWQ> 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "sqxtun2\\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_expand "aarch64_sqxtun2<mode>" + [(match_operand:<VNARROWQ2> 0 "register_operand") + (match_operand:<VNARROWQ> 1 "register_operand") + (unspec:<VNARROWQ> + [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN2)] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_sqxtun2<mode>_be (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_sqxtun2<mode>_le (operands[0], operands[1], + operands[2])); + DONE; + } +) + ;; <su>q<absneg> (define_insn "aarch64_s<optab><mode>" @@ -4036,9 +4481,25 @@ ;; vqdml[sa]l -(define_insn "aarch64_sqdml<SBINQOPS:as>l<mode>" +(define_insn "aarch64_sqdmlal<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:VSD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (match_operand:VSD_HSI 3 "register_operand" "w"))) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" + [(set_attr "type" "neon_sat_mla_<Vetype>_long")] +) + +(define_insn "aarch64_sqdmlsl<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4048,15 +4509,39 @@ (match_operand:VSD_HSI 3 "register_operand" "w"))) (const_int 1))))] "TARGET_SIMD" - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" [(set_attr "type" "neon_sat_mla_<Vetype>_long")] ) ;; vqdml[sa]l_lane -(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>" +(define_insn "aarch64_sqdmlal_lane<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:VD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (vec_duplicate:VD_HSI + (vec_select:<VEL> + (match_operand:<VCOND> 3 "register_operand" "<vwx>") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) + )) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4])); + return + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqdmlsl_lane<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4073,14 +4558,15 @@ { operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4])); return - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; } [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) -(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>" + +(define_insn "aarch64_sqdmlsl_laneq<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4097,14 +4583,62 @@ { operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4])); return - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; } [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) -(define_insn "aarch64_sqdml<SBINQOPS:as>l_lane<mode>" +(define_insn "aarch64_sqdmlal_laneq<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:VD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (vec_duplicate:VD_HSI + (vec_select:<VEL> + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) + )) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4])); + return + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + + +(define_insn "aarch64_sqdmlal_lane<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:SD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (vec_select:<VEL> + (match_operand:<VCOND> 3 "register_operand" "<vwx>") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) + ) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4])); + return + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqdmlsl_lane<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4120,14 +4654,38 @@ { operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4])); return - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; } [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) -(define_insn "aarch64_sqdml<SBINQOPS:as>l_laneq<mode>" + +(define_insn "aarch64_sqdmlal_laneq<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:SD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (vec_select:<VEL> + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))) + ) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + { + operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4])); + return + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + } + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqdmlsl_laneq<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4143,16 +4701,16 @@ { operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4])); return - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[%4]"; } [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) ;; vqdml[sa]l_n -(define_insn "aarch64_sqdml<SBINQOPS:as>l_n<mode>" +(define_insn "aarch64_sqdmlsl_n<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4163,15 +4721,53 @@ (match_operand:<VEL> 3 "register_operand" "<vwx>")))) (const_int 1))))] "TARGET_SIMD" - "sqdml<SBINQOPS:as>l\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]" + "sqdmlsl\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]" + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqdmlal_n<mode>" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (match_operand:VD_HSI 2 "register_operand" "w")) + (sign_extend:<VWIDE> + (vec_duplicate:VD_HSI + (match_operand:<VEL> 3 "register_operand" "<vwx>")))) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "sqdmlal\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %3.<Vetype>[0]" [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) + ;; sqdml[as]l2 -(define_insn "aarch64_sqdml<SBINQOPS:as>l2<mode>_internal" +(define_insn "aarch64_sqdmlal2<mode>_internal" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") - (SBINQOPS:<VWIDE> + (ss_plus:<VWIDE> + (ss_ashift:<VWIDE> + (mult:<VWIDE> + (sign_extend:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQ_HSI 2 "register_operand" "w") + (match_operand:VQ_HSI 4 "vect_par_cnst_hi_half" ""))) + (sign_extend:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQ_HSI 3 "register_operand" "w") + (match_dup 4)))) + (const_int 1)) + (match_operand:<VWIDE> 1 "register_operand" "0")))] + "TARGET_SIMD" + "sqdmlal2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" + [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] +) + +(define_insn "aarch64_sqdmlsl2<mode>_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (ss_minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "0") (ss_ashift:<VWIDE> (mult:<VWIDE> @@ -4185,7 +4781,7 @@ (match_dup 4)))) (const_int 1))))] "TARGET_SIMD" - "sqdml<SBINQOPS:as>l2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" + "sqdmlsl2\\t%<vw2>0<Vmwtype>, %<v>2<Vmtype>, %<v>3<Vmtype>" [(set_attr "type" "neon_sat_mla_<Vetype>_scalar_long")] ) @@ -7242,6 +7838,20 @@ [(set_attr "type" "neon_shift_imm_long")] ) +(define_expand "aarch64_<su>xtl<mode>" + [(set (match_operand:VQN 0 "register_operand" "=w") + (ANY_EXTEND:VQN (match_operand:<VNARROWQ> 1 "register_operand" "w")))] + "TARGET_SIMD" + "" +) + +(define_expand "aarch64_xtn<mode>" + [(set (match_operand:<VNARROWQ> 0 "register_operand" "=w") + (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))] + "TARGET_SIMD" + "" +) + ;; Truncate a 128-bit integer vector to a 64-bit vector. (define_insn "trunc<mode><Vnarrowq>2" [(set (match_operand:<VNARROWQ> 0 "register_operand" "=w") @@ -7251,6 +7861,42 @@ [(set_attr "type" "neon_shift_imm_narrow_q")] ) +(define_insn "aarch64_xtn2<mode>_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (match_operand:<VNARROWQ> 1 "register_operand" "0") + (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "xtn2\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_xtn2<mode>_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w")) + (match_operand:<VNARROWQ> 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "xtn2\t%0.<V2ntype>, %2.<Vtype>" + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_xtn2<mode>" + [(match_operand:<VNARROWQ2> 0 "register_operand") + (match_operand:<VNARROWQ> 1 "register_operand") + (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand"))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_xtn2<mode>_be (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_xtn2<mode>_le (operands[0], operands[1], + operands[2])); + DONE; + } +) + (define_insn "aarch64_bfdot<mode>" [(set (match_operand:VDQSF 0 "register_operand" "=w") (plus:VDQSF diff --git a/gcc/config/aarch64/aarch64-speculation.cc b/gcc/config/aarch64/aarch64-speculation.cc index f490b64..dbade37 100644 --- a/gcc/config/aarch64/aarch64-speculation.cc +++ b/gcc/config/aarch64/aarch64-speculation.cc @@ -1,5 +1,5 @@ /* Speculation tracking and mitigation (e.g. CVE 2017-5753) for AArch64. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index 4223125..dfdf0e2 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE intrinsics) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def b/gcc/config/aarch64/aarch64-sve-builtins-base.def index 27ab05d..7d3f19a 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE intrinsics) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.h b/gcc/config/aarch64/aarch64-sve-builtins-base.h index 957ace8..dc8d685 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.h @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE intrinsics) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h index 71a3943..09c60fa 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (function_base classes) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc index 5f8c85d..e16c81c 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (function shapes) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h index 3a19982..2e2ee26 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.h @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (function shapes) - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index 9e7219c..4b29986 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE2 intrinsics) - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 8daf8f7..bed792d 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE intrinsics) - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h index 06d4a93..00bf17c 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE (__ARM_FEATURE_SVE intrinsics) - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index e73aa9a..6270b51 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -2580,7 +2580,7 @@ gimple_folder::fold_contiguous_base (gimple_seq &stmts, tree vectype) tree gimple_folder::load_store_cookie (tree type) { - return build_int_cst (build_pointer_type (type), TYPE_ALIGN_UNIT (type)); + return build_int_cst (build_pointer_type (type), TYPE_ALIGN (type)); } /* Fold the call to a call to INSTANCE, with the same arguments. */ diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def b/gcc/config/aarch64/aarch64-sve-builtins.def index 3dbf4f5..6505163 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.def +++ b/gcc/config/aarch64/aarch64-sve-builtins.def @@ -1,5 +1,5 @@ /* Builtin lists for AArch64 SVE - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h index 3ffe251..620e188 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.h +++ b/gcc/config/aarch64/aarch64-sve-builtins.h @@ -1,5 +1,5 @@ /* ACLE support for AArch64 SVE - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 6359c40..6083196 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 SVE. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -2940,23 +2940,23 @@ ;; Predicated integer unary arithmetic with merging. (define_expand "@cond_<optab><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") - (SVE_INT_UNARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand")) - (match_operand:SVE_FULL_I 3 "aarch64_simd_reg_or_zero")] + (SVE_INT_UNARY:SVE_I + (match_operand:SVE_I 2 "register_operand")) + (match_operand:SVE_I 3 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE" ) ;; Predicated integer unary arithmetic, merging with the first input. (define_insn "*cond_<optab><mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (SVE_INT_UNARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w")) + (SVE_INT_UNARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -2974,12 +2974,12 @@ ;; as earlyclobber helps to make the instruction more regular to the ;; register allocator. (define_insn "*cond_<optab><mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (SVE_INT_UNARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, w")) - (match_operand:SVE_FULL_I 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] + (SVE_INT_UNARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, w")) + (match_operand:SVE_I 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[3])" "@ @@ -3135,12 +3135,12 @@ ;; The canonical form of this operation is an AND of a constant rather ;; than (zero_extend (truncate ...)). (define_insn "*cond_uxt<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (and:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate")) + (and:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_sve_uxt_immediate")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -3159,13 +3159,13 @@ ;; as early-clobber helps to make the instruction more regular to the ;; register allocator. (define_insn "*cond_uxt<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (and:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")] + (and:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_sve_uxt_immediate")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4])" "@ @@ -3227,16 +3227,16 @@ ) (define_insn "*cnot<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(unspec:<VPRED> [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") (match_operand:SI 5 "aarch64_sve_ptrue_flag") (eq:<VPRED> - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_imm_zero"))] + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] UNSPEC_PRED_Z) - (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_one") + (match_operand:SVE_I 4 "aarch64_simd_imm_one") (match_dup 3)] UNSPEC_SEL))] "TARGET_SVE" @@ -3274,19 +3274,19 @@ ;; Predicated logical inverse, merging with the first input. (define_insn_and_rewrite "*cond_cnot<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") ;; Logical inverse of operand 2 (as above). - (unspec:SVE_FULL_I + (unspec:SVE_I [(unspec:<VPRED> [(match_operand 5) (const_int SVE_KNOWN_PTRUE) (eq:<VPRED> - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_imm_zero"))] + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] UNSPEC_PRED_Z) - (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_one") + (match_operand:SVE_I 4 "aarch64_simd_imm_one") (match_dup 3)] UNSPEC_SEL) (match_dup 2)] @@ -3310,22 +3310,22 @@ ;; as earlyclobber helps to make the instruction more regular to the ;; register allocator. (define_insn_and_rewrite "*cond_cnot<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") ;; Logical inverse of operand 2 (as above). - (unspec:SVE_FULL_I + (unspec:SVE_I [(unspec:<VPRED> [(match_operand 5) (const_int SVE_KNOWN_PTRUE) (eq:<VPRED> - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_imm_zero"))] + (match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_simd_imm_zero"))] UNSPEC_PRED_Z) - (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_one") + (match_operand:SVE_I 4 "aarch64_simd_imm_one") (match_dup 3)] UNSPEC_SEL) - (match_operand:SVE_FULL_I 6 "aarch64_simd_reg_or_zero" "0, Dz, w")] + (match_operand:SVE_I 6 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[6])" "@ @@ -3628,12 +3628,12 @@ ;; Unpredicated integer binary operations that have an immediate form. (define_expand "<optab><mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_dup 3) - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "aarch64_sve_<sve_imm_con>_operand"))] + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_operand"))] UNSPEC_PRED_X))] "TARGET_SVE" { @@ -3647,12 +3647,12 @@ ;; and would make the instruction seem less uniform to the register ;; allocator. (define_insn_and_split "@aarch64_pred_<optab><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl") - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "%0, 0, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_<sve_imm_con>_operand" "<sve_imm_con>, w, <sve_imm_con>, w"))] + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 2 "register_operand" "%0, 0, w, w") + (match_operand:SVE_I 3 "aarch64_sve_<sve_imm_con>_operand" "<sve_imm_con>, w, <sve_imm_con>, w"))] UNSPEC_PRED_X))] "TARGET_SVE" "@ @@ -3665,7 +3665,7 @@ "&& reload_completed && !register_operand (operands[3], <MODE>mode)" [(set (match_dup 0) - (SVE_INT_BINARY_IMM:SVE_FULL_I (match_dup 2) (match_dup 3)))] + (SVE_INT_BINARY_IMM:SVE_I (match_dup 2) (match_dup 3)))] "" [(set_attr "movprfx" "*,*,yes,yes")] ) @@ -3674,10 +3674,10 @@ ;; These are generated by splitting a predicated instruction whose ;; predicate is unused. (define_insn "*post_ra_<optab><mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (SVE_INT_BINARY_IMM:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand" "0, w") - (match_operand:SVE_FULL_I 2 "aarch64_sve_<sve_imm_con>_immediate")))] + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (SVE_INT_BINARY_IMM:SVE_I + (match_operand:SVE_I 1 "register_operand" "0, w") + (match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_immediate")))] "TARGET_SVE && reload_completed" "@ <sve_int_op>\t%0.<Vetype>, %0.<Vetype>, #%<sve_imm_prefix>2 @@ -3687,25 +3687,25 @@ ;; Predicated integer operations with merging. (define_expand "@cond_<optab><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") - (SVE_INT_BINARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand") - (match_operand:SVE_FULL_I 3 "<sve_pred_int_rhs2_operand>")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")] + (SVE_INT_BINARY:SVE_I + (match_operand:SVE_I 2 "register_operand") + (match_operand:SVE_I 3 "<sve_pred_int_rhs2_operand>")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE" ) ;; Predicated integer operations, merging with the first input. (define_insn "*cond_<optab><mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (SVE_INT_BINARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")) + (SVE_INT_BINARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "register_operand" "w, w")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -3717,12 +3717,12 @@ ;; Predicated integer operations, merging with the second input. (define_insn "*cond_<optab><mode>_3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (SVE_INT_BINARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "0, w")) + (SVE_INT_BINARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w") + (match_operand:SVE_I 3 "register_operand" "0, w")) (match_dup 3)] UNSPEC_SEL))] "TARGET_SVE" @@ -3734,13 +3734,13 @@ ;; Predicated integer operations, merging with an independent value. (define_insn_and_rewrite "*cond_<optab><mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") - (SVE_INT_BINARY:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w, w, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, 0, w, w, w")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] + (SVE_INT_BINARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w, w, w, w") + (match_operand:SVE_I 3 "register_operand" "w, 0, w, w, w")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4]) @@ -3901,17 +3901,17 @@ ) (define_insn_and_rewrite "*aarch64_adr<mode>_shift" - [(set (match_operand:SVE_FULL_SDI 0 "register_operand" "=w") - (plus:SVE_FULL_SDI - (unspec:SVE_FULL_SDI + [(set (match_operand:SVE_24I 0 "register_operand" "=w") + (plus:SVE_24I + (unspec:SVE_24I [(match_operand 4) - (ashift:SVE_FULL_SDI - (match_operand:SVE_FULL_SDI 2 "register_operand" "w") - (match_operand:SVE_FULL_SDI 3 "const_1_to_3_operand"))] + (ashift:SVE_24I + (match_operand:SVE_24I 2 "register_operand" "w") + (match_operand:SVE_24I 3 "const_1_to_3_operand"))] UNSPEC_PRED_X) - (match_operand:SVE_FULL_SDI 1 "register_operand" "w")))] + (match_operand:SVE_24I 1 "register_operand" "w")))] "TARGET_SVE" - "adr\t%0.<Vetype>, [%1.<Vetype>, %2.<Vetype>, lsl %3]" + "adr\t%0.<Vctype>, [%1.<Vctype>, %2.<Vctype>, lsl %3]" "&& !CONSTANT_P (operands[4])" { operands[4] = CONSTM1_RTX (<VPRED>mode); @@ -3973,10 +3973,10 @@ ;; Unpredicated integer absolute difference. (define_expand "<su>abd<mode>_3" - [(use (match_operand:SVE_FULL_I 0 "register_operand")) - (USMAX:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "register_operand"))] + [(use (match_operand:SVE_I 0 "register_operand")) + (USMAX:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "register_operand"))] "TARGET_SVE" { rtx pred = aarch64_ptrue_reg (<VPRED>mode); @@ -3988,17 +3988,20 @@ ;; Predicated integer absolute difference. (define_insn "@aarch64_pred_<su>abd<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I - [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (minus:SVE_FULL_I - (USMAX:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "%0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")) - (<max_opp>:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (minus:SVE_I + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") + (USMAX:SVE_I + (match_operand:SVE_I 2 "register_operand" "%0, w") + (match_operand:SVE_I 3 "register_operand" "w, w"))] + UNSPEC_PRED_X) + (unspec:SVE_I + [(match_dup 1) + (<max_opp>:SVE_I (match_dup 2) - (match_dup 3)))] - UNSPEC_PRED_X))] + (match_dup 3))] + UNSPEC_PRED_X)))] "TARGET_SVE" "@ <su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype> @@ -4033,19 +4036,19 @@ ;; Predicated integer absolute difference, merging with the first input. (define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (minus:SVE_FULL_I - (unspec:SVE_FULL_I + (minus:SVE_I + (unspec:SVE_I [(match_operand 4) - (USMAX:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w"))] + (USMAX:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "register_operand" "w, w"))] UNSPEC_PRED_X) - (unspec:SVE_FULL_I + (unspec:SVE_I [(match_operand 5) - (<max_opp>:SVE_FULL_I + (<max_opp>:SVE_I (match_dup 2) (match_dup 3))] UNSPEC_PRED_X)) @@ -4062,25 +4065,56 @@ [(set_attr "movprfx" "*,yes")] ) +;; Predicated integer absolute difference, merging with the second input. +(define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_3" + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") + (minus:SVE_I + (unspec:SVE_I + [(match_operand 4) + (USMAX:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w") + (match_operand:SVE_I 3 "register_operand" "0, w"))] + UNSPEC_PRED_X) + (unspec:SVE_I + [(match_operand 5) + (<max_opp>:SVE_I + (match_dup 2) + (match_dup 3))] + UNSPEC_PRED_X)) + (match_dup 3)] + UNSPEC_SEL))] + "TARGET_SVE" + "@ + <su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype> + movprfx\t%0, %3\;<su>abd\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>" + "&& (!CONSTANT_P (operands[4]) || !CONSTANT_P (operands[5]))" + { + operands[4] = operands[5] = CONSTM1_RTX (<VPRED>mode); + } + [(set_attr "movprfx" "*,yes")] +) + ;; Predicated integer absolute difference, merging with an independent value. (define_insn_and_rewrite "*aarch64_cond_<su>abd<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") - (minus:SVE_FULL_I - (unspec:SVE_FULL_I + (minus:SVE_I + (unspec:SVE_I [(match_operand 5) - (USMAX:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w, w, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, 0, w, w, w"))] + (USMAX:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w, w, w, w") + (match_operand:SVE_I 3 "register_operand" "w, 0, w, w, w"))] UNSPEC_PRED_X) - (unspec:SVE_FULL_I + (unspec:SVE_I [(match_operand 6) - (<max_opp>:SVE_FULL_I + (<max_opp>:SVE_I (match_dup 2) (match_dup 3))] UNSPEC_PRED_X)) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4]) @@ -4158,12 +4192,12 @@ ;; Unpredicated highpart multiplication. (define_expand "<su>mul<mode>3_highpart" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_dup 3) - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "register_operand")] + (unspec:SVE_I + [(match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "register_operand")] MUL_HIGHPART)] UNSPEC_PRED_X))] "TARGET_SVE" @@ -4174,12 +4208,12 @@ ;; Predicated highpart multiplication. (define_insn "@aarch64_pred_<optab><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 2 "register_operand" "%0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")] + (unspec:SVE_I + [(match_operand:SVE_I 2 "register_operand" "%0, w") + (match_operand:SVE_I 3 "register_operand" "w, w")] MUL_HIGHPART)] UNSPEC_PRED_X))] "TARGET_SVE" @@ -4441,13 +4475,13 @@ ;; Predicated integer BIC, merging with the first input. (define_insn "*cond_bic<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (and:SVE_FULL_I - (not:SVE_FULL_I - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")) - (match_operand:SVE_FULL_I 2 "register_operand" "0, w")) + (and:SVE_I + (not:SVE_I + (match_operand:SVE_I 3 "register_operand" "w, w")) + (match_operand:SVE_I 2 "register_operand" "0, w")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -4459,14 +4493,14 @@ ;; Predicated integer BIC, merging with an independent value. (define_insn_and_rewrite "*cond_bic<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl") - (and:SVE_FULL_I - (not:SVE_FULL_I - (match_operand:SVE_FULL_I 3 "register_operand" "w, w, w, w")) - (match_operand:SVE_FULL_I 2 "register_operand" "0, w, w, w")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, 0, w")] + (and:SVE_I + (not:SVE_I + (match_operand:SVE_I 3 "register_operand" "w, w, w, w")) + (match_operand:SVE_I 2 "register_operand" "0, w, w, w")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4])" "@ @@ -4500,9 +4534,9 @@ ;; Unpredicated shift by a scalar, which expands into one of the vector ;; shifts below. (define_expand "<ASHIFT:optab><mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") + [(set (match_operand:SVE_I 0 "register_operand") + (ASHIFT:SVE_I + (match_operand:SVE_I 1 "register_operand") (match_operand:<VEL> 2 "general_operand")))] "TARGET_SVE" { @@ -4527,12 +4561,12 @@ ;; Unpredicated shift by a vector. (define_expand "v<optab><mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_dup 3) - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "aarch64_sve_<lr>shift_operand"))] + (ASHIFT:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "aarch64_sve_<lr>shift_operand"))] UNSPEC_PRED_X))] "TARGET_SVE" { @@ -4545,12 +4579,12 @@ ;; likely to gain much and would make the instruction seem less uniform ;; to the register allocator. (define_insn_and_split "@aarch64_pred_<optab><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl") - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, 0, w"))] + (ASHIFT:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, 0, w, w") + (match_operand:SVE_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, 0, w"))] UNSPEC_PRED_X))] "TARGET_SVE" "@ @@ -4560,7 +4594,7 @@ movprfx\t%0, %2\;<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>" "&& reload_completed && !register_operand (operands[3], <MODE>mode)" - [(set (match_dup 0) (ASHIFT:SVE_FULL_I (match_dup 2) (match_dup 3)))] + [(set (match_dup 0) (ASHIFT:SVE_I (match_dup 2) (match_dup 3)))] "" [(set_attr "movprfx" "*,*,*,yes")] ) @@ -4569,22 +4603,22 @@ ;; These are generated by splitting a predicated instruction whose ;; predicate is unused. (define_insn "*post_ra_v<optab><mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand" "w") - (match_operand:SVE_FULL_I 2 "aarch64_simd_<lr>shift_imm")))] + [(set (match_operand:SVE_I 0 "register_operand" "=w") + (ASHIFT:SVE_I + (match_operand:SVE_I 1 "register_operand" "w") + (match_operand:SVE_I 2 "aarch64_simd_<lr>shift_imm")))] "TARGET_SVE && reload_completed" "<shift>\t%0.<Vetype>, %1.<Vetype>, #%2" ) ;; Predicated integer shift, merging with the first input. (define_insn "*cond_<optab><mode>_2_const" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_<lr>shift_imm")) + (ASHIFT:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_<lr>shift_imm")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -4596,13 +4630,13 @@ ;; Predicated integer shift, merging with an independent value. (define_insn_and_rewrite "*cond_<optab><mode>_any_const" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (ASHIFT:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_<lr>shift_imm")) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + (ASHIFT:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_simd_<lr>shift_imm")) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[4])" "@ @@ -4690,68 +4724,111 @@ ;; - URSHR (SVE2) ;; ------------------------------------------------------------------------- -;; Unpredicated <SVE_INT_OP>. +;; Unpredicated ASRD. (define_expand "sdiv_pow2<mode>3" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_dup 3) - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 1 "register_operand") + (unspec:SVE_I + [(match_operand:SVE_I 1 "register_operand") (match_operand 2 "aarch64_simd_rshift_imm")] - UNSPEC_ASRD) - (match_dup 1)] - UNSPEC_SEL))] + UNSPEC_ASRD)] + UNSPEC_PRED_X))] "TARGET_SVE" { operands[3] = aarch64_ptrue_reg (<VPRED>mode); } ) -;; Predicated right shift with merging. +;; Predicated ASRD. +(define_insn "*sdiv_pow2<mode>3" + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") + (unspec:SVE_I + [(match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_rshift_imm")] + UNSPEC_ASRD)] + UNSPEC_PRED_X))] + "TARGET_SVE" + "@ + asrd\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3 + movprfx\t%0, %2\;asrd\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3" + [(set_attr "movprfx" "*,yes")]) + +;; Predicated shift with merging. (define_expand "@cond_<sve_int_op><mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 2 "register_operand") - (match_operand:SVE_FULL_I 3 "aarch64_simd_<lr>shift_imm")] - SVE_INT_SHIFT_IMM) - (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")] + (unspec:SVE_I + [(match_dup 5) + (unspec:SVE_I + [(match_operand:SVE_I 2 "register_operand") + (match_operand:SVE_I 3 "aarch64_simd_<lr>shift_imm")] + SVE_INT_SHIFT_IMM)] + UNSPEC_PRED_X) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE" + { + operands[5] = aarch64_ptrue_reg (<VPRED>mode); + } ) -;; Predicated right shift, merging with the first input. -(define_insn "*cond_<sve_int_op><mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I +;; Predicated shift, merging with the first input. +(define_insn_and_rewrite "*cond_<sve_int_op><mode>_2" + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_<lr>shift_imm")] - SVE_INT_SHIFT_IMM) + (unspec:SVE_I + [(match_operand 4) + (unspec:SVE_I + [(match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "aarch64_simd_<lr>shift_imm")] + SVE_INT_SHIFT_IMM)] + UNSPEC_PRED_X) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" "@ <sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3 movprfx\t%0, %2\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3" + "&& !CONSTANT_P (operands[4])" + { + operands[4] = CONSTM1_RTX (<VPRED>mode); + } [(set_attr "movprfx" "*,yes")]) -;; Predicated right shift, merging with zero. -(define_insn "*cond_<sve_int_op><mode>_z" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") - (unspec:SVE_FULL_I - [(match_operand:<VPRED> 1 "register_operand" "Upl") - (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 2 "register_operand" "w") - (match_operand:SVE_FULL_I 3 "aarch64_simd_<lr>shift_imm")] - SVE_INT_SHIFT_IMM) - (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_zero")] - UNSPEC_SEL))] - "TARGET_SVE" - "movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3" - [(set_attr "movprfx" "yes")]) +;; Predicated shift, merging with an independent value. +(define_insn_and_rewrite "*cond_<sve_int_op><mode>_any" + [(set (match_operand:SVE_I 0 "register_operand" "=w, &w, ?&w") + (unspec:SVE_I + [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_I + [(match_operand 5) + (unspec:SVE_I + [(match_operand:SVE_I 2 "register_operand" "w, w, w") + (match_operand:SVE_I 3 "aarch64_simd_<lr>shift_imm")] + SVE_INT_SHIFT_IMM)] + UNSPEC_PRED_X) + (match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + UNSPEC_SEL))] + "TARGET_SVE && !rtx_equal_p (operands[2], operands[4])" + "@ + movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3 + movprfx\t%0.<Vetype>, %1/m, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3 + #" + "&& reload_completed + && register_operand (operands[4], <MODE>mode) + && !rtx_equal_p (operands[0], operands[4])" + { + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2], + operands[4], operands[1])); + operands[4] = operands[2] = operands[0]; + } + [(set_attr "movprfx" "yes")] +) ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] General binary arithmetic corresponding to unspecs @@ -5480,6 +5557,20 @@ "TARGET_SVE" ) +;; Predicated FCADD using ptrue for unpredicated optab for auto-vectorizer +(define_expand "@cadd<rot><mode>3" + [(set (match_operand:SVE_FULL_F 0 "register_operand") + (unspec:SVE_FULL_F + [(match_dup 3) + (const_int SVE_RELAXED_GP) + (match_operand:SVE_FULL_F 1 "register_operand") + (match_operand:SVE_FULL_F 2 "register_operand")] + SVE_COND_FCADD))] + "TARGET_SVE" +{ + operands[3] = aarch64_ptrue_reg (<VPRED>mode); +}) + ;; Predicated FCADD, merging with the first input. (define_insn_and_rewrite "*cond_<optab><mode>_2_relaxed" [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, ?&w") @@ -6463,15 +6554,15 @@ ;; Unpredicated integer addition of product. (define_expand "fma<mode>4" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (plus:SVE_FULL_I - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (plus:SVE_I + (unspec:SVE_I [(match_dup 4) - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "nonmemory_operand"))] + (mult:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "nonmemory_operand"))] UNSPEC_PRED_X) - (match_operand:SVE_FULL_I 3 "register_operand")))] + (match_operand:SVE_I 3 "register_operand")))] "TARGET_SVE" { if (aarch64_prepare_sve_int_fma (operands, PLUS)) @@ -6482,15 +6573,15 @@ ;; Predicated integer addition of product. (define_insn "@aarch64_pred_fma<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w") - (plus:SVE_FULL_I - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") + (plus:SVE_I + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "%0, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w, w"))] + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "%0, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w"))] UNSPEC_PRED_X) - (match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w")))] + (match_operand:SVE_I 4 "register_operand" "w, 0, w")))] "TARGET_SVE" "@ mad\t%0.<Vetype>, %1/m, %3.<Vetype>, %4.<Vetype> @@ -6501,15 +6592,15 @@ ;; Predicated integer addition of product with merging. (define_expand "cond_fma<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") - (plus:SVE_FULL_I - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand") - (match_operand:SVE_FULL_I 3 "general_operand")) - (match_operand:SVE_FULL_I 4 "register_operand")) - (match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero")] + (plus:SVE_I + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand") + (match_operand:SVE_I 3 "general_operand")) + (match_operand:SVE_I 4 "register_operand")) + (match_operand:SVE_I 5 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE" { @@ -6524,14 +6615,14 @@ ;; Predicated integer addition of product, merging with the first input. (define_insn "*cond_fma<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (plus:SVE_FULL_I - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")) - (match_operand:SVE_FULL_I 4 "register_operand" "w, w")) + (plus:SVE_I + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "register_operand" "w, w")) + (match_operand:SVE_I 4 "register_operand" "w, w")) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -6543,14 +6634,14 @@ ;; Predicated integer addition of product, merging with the third input. (define_insn "*cond_fma<mode>_4" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (plus:SVE_FULL_I - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w")) - (match_operand:SVE_FULL_I 4 "register_operand" "0, w")) + (plus:SVE_I + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w") + (match_operand:SVE_I 3 "register_operand" "w, w")) + (match_operand:SVE_I 4 "register_operand" "0, w")) (match_dup 4)] UNSPEC_SEL))] "TARGET_SVE" @@ -6562,15 +6653,15 @@ ;; Predicated integer addition of product, merging with an independent value. (define_insn_and_rewrite "*cond_fma<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl") - (plus:SVE_FULL_I - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, 0, w, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w, w, 0, w, w")) - (match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w, w, w, w")) - (match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] + (plus:SVE_I + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, 0, w, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w, 0, w, w")) + (match_operand:SVE_I 4 "register_operand" "w, 0, w, w, w, w")) + (match_operand:SVE_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[5]) @@ -6604,14 +6695,14 @@ ;; Unpredicated integer subtraction of product. (define_expand "fnma<mode>4" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 3 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (minus:SVE_I + (match_operand:SVE_I 3 "register_operand") + (unspec:SVE_I [(match_dup 4) - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 1 "register_operand") - (match_operand:SVE_FULL_I 2 "general_operand"))] + (mult:SVE_I + (match_operand:SVE_I 1 "register_operand") + (match_operand:SVE_I 2 "general_operand"))] UNSPEC_PRED_X)))] "TARGET_SVE" { @@ -6623,14 +6714,14 @@ ;; Predicated integer subtraction of product. (define_insn "@aarch64_pred_fnma<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") + (minus:SVE_I + (match_operand:SVE_I 4 "register_operand" "w, 0, w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "%0, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w, w"))] + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "%0, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w"))] UNSPEC_PRED_X)))] "TARGET_SVE" "@ @@ -6642,15 +6733,15 @@ ;; Predicated integer subtraction of product with merging. (define_expand "cond_fnma<mode>" - [(set (match_operand:SVE_FULL_I 0 "register_operand") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 4 "register_operand") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand") - (match_operand:SVE_FULL_I 3 "general_operand"))) - (match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero")] + (minus:SVE_I + (match_operand:SVE_I 4 "register_operand") + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand") + (match_operand:SVE_I 3 "general_operand"))) + (match_operand:SVE_I 5 "aarch64_simd_reg_or_zero")] UNSPEC_SEL))] "TARGET_SVE" { @@ -6665,14 +6756,14 @@ ;; Predicated integer subtraction of product, merging with the first input. (define_insn "*cond_fnma<mode>_2" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 4 "register_operand" "w, w") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "0, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w"))) + (minus:SVE_I + (match_operand:SVE_I 4 "register_operand" "w, w") + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w") + (match_operand:SVE_I 3 "register_operand" "w, w"))) (match_dup 2)] UNSPEC_SEL))] "TARGET_SVE" @@ -6684,14 +6775,14 @@ ;; Predicated integer subtraction of product, merging with the third input. (define_insn "*cond_fnma<mode>_4" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 4 "register_operand" "0, w") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w"))) + (minus:SVE_I + (match_operand:SVE_I 4 "register_operand" "0, w") + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w") + (match_operand:SVE_I 3 "register_operand" "w, w"))) (match_dup 4)] UNSPEC_SEL))] "TARGET_SVE" @@ -6704,15 +6795,15 @@ ;; Predicated integer subtraction of product, merging with an ;; independent value. (define_insn_and_rewrite "*cond_fnma<mode>_any" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") - (unspec:SVE_FULL_I + [(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") + (unspec:SVE_I [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl") - (minus:SVE_FULL_I - (match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w, w, w, w") - (mult:SVE_FULL_I - (match_operand:SVE_FULL_I 2 "register_operand" "w, w, 0, w, w, w") - (match_operand:SVE_FULL_I 3 "register_operand" "w, w, w, 0, w, w"))) - (match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] + (minus:SVE_I + (match_operand:SVE_I 4 "register_operand" "w, 0, w, w, w, w") + (mult:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, 0, w, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w, 0, w, w"))) + (match_operand:SVE_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[5]) @@ -7152,6 +7243,62 @@ [(set_attr "movprfx" "*,yes")] ) +;; unpredicated optab pattern for auto-vectorizer +;; The complex mla/mls operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cml<fcmac1><conj_op><mode>4" + [(set (match_operand:SVE_FULL_F 0 "register_operand") + (unspec:SVE_FULL_F + [(match_dup 4) + (match_dup 5) + (match_operand:SVE_FULL_F 1 "register_operand") + (match_operand:SVE_FULL_F 2 "register_operand") + (match_operand:SVE_FULL_F 3 "register_operand")] + FCMLA_OP))] + "TARGET_SVE" +{ + operands[4] = aarch64_ptrue_reg (<VPRED>mode); + operands[5] = gen_int_mode (SVE_RELAXED_GP, SImode); + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn + (gen_aarch64_pred_fcmla<sve_rot1><mode> (tmp, operands[4], + operands[3], operands[2], + operands[1], operands[5])); + emit_insn + (gen_aarch64_pred_fcmla<sve_rot2><mode> (operands[0], operands[4], + operands[3], operands[2], + tmp, operands[5])); + DONE; +}) + +;; unpredicated optab pattern for auto-vectorizer +;; The complex mul operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cmul<conj_op><mode>3" + [(set (match_operand:SVE_FULL_F 0 "register_operand") + (unspec:SVE_FULL_F + [(match_operand:SVE_FULL_F 1 "register_operand") + (match_operand:SVE_FULL_F 2 "register_operand")] + FCMUL_OP))] + "TARGET_SVE" +{ + rtx pred_reg = aarch64_ptrue_reg (<VPRED>mode); + rtx gp_mode = gen_int_mode (SVE_RELAXED_GP, SImode); + rtx accum = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn + (gen_aarch64_pred_fcmla<sve_rot1><mode> (tmp, pred_reg, + operands[2], operands[1], + accum, gp_mode)); + emit_insn + (gen_aarch64_pred_fcmla<sve_rot2><mode> (operands[0], pred_reg, + operands[2], operands[1], + tmp, gp_mode)); + DONE; +}) + ;; Predicated FCMLA with merging. (define_expand "@cond_<optab><mode>" [(set (match_operand:SVE_FULL_F 0 "register_operand") diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 772c350..e7cd2b8 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 SVE2. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -1799,6 +1799,16 @@ [(set_attr "movprfx" "*,yes")] ) +;; unpredicated optab pattern for auto-vectorizer +(define_expand "cadd<rot><mode>3" + [(set (match_operand:SVE_FULL_I 0 "register_operand") + (unspec:SVE_FULL_I + [(match_operand:SVE_FULL_I 1 "register_operand") + (match_operand:SVE_FULL_I 2 "register_operand")] + SVE2_INT_CADD_OP))] + "TARGET_SVE2" +) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Complex ternary operations ;; ------------------------------------------------------------------------- @@ -1838,6 +1848,48 @@ [(set_attr "movprfx" "*,yes")] ) +;; unpredicated optab pattern for auto-vectorizer +;; The complex mla/mls operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cml<fcmac1><conj_op><mode>4" + [(set (match_operand:SVE_FULL_I 0 "register_operand") + (plus:SVE_FULL_I (match_operand:SVE_FULL_I 1 "register_operand") + (unspec:SVE_FULL_I + [(match_operand:SVE_FULL_I 2 "register_operand") + (match_operand:SVE_FULL_I 3 "register_operand")] + SVE2_INT_CMLA_OP)))] + "TARGET_SVE2" +{ + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn (gen_aarch64_sve_cmla<sve_rot1><mode> (tmp, operands[1], + operands[3], operands[2])); + emit_insn (gen_aarch64_sve_cmla<sve_rot2><mode> (operands[0], tmp, + operands[3], operands[2])); + DONE; +}) + +;; unpredicated optab pattern for auto-vectorizer +;; The complex mul operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cmul<conj_op><mode>3" + [(set (match_operand:SVE_FULL_I 0 "register_operand") + (unspec:SVE_FULL_I + [(match_operand:SVE_FULL_I 1 "register_operand") + (match_operand:SVE_FULL_I 2 "register_operand")] + SVE2_INT_CMUL_OP))] + "TARGET_SVE2" +{ + rtx accum = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn (gen_aarch64_sve_cmla<sve_rot1><mode> (tmp, accum, + operands[2], operands[1])); + emit_insn (gen_aarch64_sve_cmla<sve_rot2><mode> (operands[0], tmp, + operands[2], operands[1])); + DONE; +}) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Complex dot product ;; ------------------------------------------------------------------------- diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index e060302..af66c11 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82" + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index ccef3c0..aae9952 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-vxworks.h b/gcc/config/aarch64/aarch64-vxworks.h index 9e172c1..d5bdb4e 100644 --- a/gcc/config/aarch64/aarch64-vxworks.h +++ b/gcc/config/aarch64/aarch64-vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Vxworks Aarch 64bit version. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Douglas B Rupp This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 67ffba0..b6192e5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -464,6 +464,22 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table = 2, /* imm_offset */ }; +static const struct cpu_addrcost_table a64fx_addrcost_table = +{ + { + 1, /* hi */ + 1, /* si */ + 1, /* di */ + 2, /* ti */ + }, + 0, /* pre_modify */ + 0, /* post_modify */ + 2, /* register_offset */ + 3, /* register_sextend */ + 3, /* register_zextend */ + 0, /* imm_offset */ +}; + static const struct cpu_regmove_cost generic_regmove_cost = { 1, /* GP2GP */ @@ -559,6 +575,44 @@ static const struct cpu_regmove_cost tsv110_regmove_cost = 2 /* FP2FP */ }; +static const struct cpu_regmove_cost a64fx_regmove_cost = +{ + 1, /* GP2GP */ + /* Avoid the use of slow int<->fp moves for spilling by setting + their cost higher than memmov_cost. */ + 5, /* GP2FP */ + 7, /* FP2GP */ + 2 /* FP2FP */ +}; + +/* Generic costs for Advanced SIMD vector operations. */ +static const advsimd_vec_cost generic_advsimd_vector_cost = +{ + 1, /* int_stmt_cost */ + 1, /* fp_stmt_cost */ + 2, /* permute_cost */ + 2, /* vec_to_scalar_cost */ + 1, /* scalar_to_vec_cost */ + 1, /* align_load_cost */ + 1, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ +}; + +/* Generic costs for SVE vector operations. */ +static const sve_vec_cost generic_sve_vector_cost = +{ + 1, /* int_stmt_cost */ + 1, /* fp_stmt_cost */ + 2, /* permute_cost */ + 2, /* vec_to_scalar_cost */ + 1, /* scalar_to_vec_cost */ + 1, /* align_load_cost */ + 1, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ +}; + /* Generic costs for vector insn classes. */ static const struct cpu_vector_cost generic_vector_cost = { @@ -566,17 +620,61 @@ static const struct cpu_vector_cost generic_vector_cost = 1, /* scalar_fp_stmt_cost */ 1, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 1, /* vec_int_stmt_cost */ - 1, /* vec_fp_stmt_cost */ - 2, /* vec_permute_cost */ - 2, /* vec_to_scalar_cost */ - 1, /* scalar_to_vec_cost */ - 1, /* vec_align_load_cost */ - 1, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 3, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &generic_advsimd_vector_cost, /* advsimd */ + &generic_sve_vector_cost /* sve */ +}; + +static const advsimd_vec_cost a64fx_advsimd_vector_cost = +{ + 2, /* int_stmt_cost */ + 5, /* fp_stmt_cost */ + 3, /* permute_cost */ + 13, /* vec_to_scalar_cost */ + 4, /* scalar_to_vec_cost */ + 6, /* align_load_cost */ + 6, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ +}; + +static const sve_vec_cost a64fx_sve_vector_cost = +{ + 2, /* int_stmt_cost */ + 5, /* fp_stmt_cost */ + 3, /* permute_cost */ + 13, /* vec_to_scalar_cost */ + 4, /* scalar_to_vec_cost */ + 6, /* align_load_cost */ + 6, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ +}; + +static const struct cpu_vector_cost a64fx_vector_cost = +{ + 1, /* scalar_int_stmt_cost */ + 5, /* scalar_fp_stmt_cost */ + 4, /* scalar_load_cost */ + 1, /* scalar_store_cost */ + 3, /* cond_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &a64fx_advsimd_vector_cost, /* advsimd */ + &a64fx_sve_vector_cost /* sve */ +}; + +static const advsimd_vec_cost qdf24xx_advsimd_vector_cost = +{ + 1, /* int_stmt_cost */ + 3, /* fp_stmt_cost */ + 2, /* permute_cost */ + 1, /* vec_to_scalar_cost */ + 1, /* scalar_to_vec_cost */ + 1, /* align_load_cost */ + 1, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ }; /* QDF24XX costs for vector insn classes. */ @@ -586,17 +684,24 @@ static const struct cpu_vector_cost qdf24xx_vector_cost = 1, /* scalar_fp_stmt_cost */ 1, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 1, /* vec_int_stmt_cost */ - 3, /* vec_fp_stmt_cost */ - 2, /* vec_permute_cost */ - 1, /* vec_to_scalar_cost */ - 1, /* scalar_to_vec_cost */ - 1, /* vec_align_load_cost */ - 1, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 3, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &qdf24xx_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + + +static const advsimd_vec_cost thunderx_advsimd_vector_cost = +{ + 4, /* int_stmt_cost */ + 1, /* fp_stmt_cost */ + 4, /* permute_cost */ + 2, /* vec_to_scalar_cost */ + 2, /* scalar_to_vec_cost */ + 3, /* align_load_cost */ + 5, /* unalign_load_cost */ + 5, /* unalign_store_cost */ + 1 /* store_cost */ }; /* ThunderX costs for vector insn classes. */ @@ -606,17 +711,23 @@ static const struct cpu_vector_cost thunderx_vector_cost = 1, /* scalar_fp_stmt_cost */ 3, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 4, /* vec_int_stmt_cost */ - 1, /* vec_fp_stmt_cost */ - 4, /* vec_permute_cost */ - 2, /* vec_to_scalar_cost */ - 2, /* scalar_to_vec_cost */ - 3, /* vec_align_load_cost */ - 5, /* vec_unalign_load_cost */ - 5, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 3, /* cond_taken_branch_cost */ - 3 /* cond_not_taken_branch_cost */ + 3, /* cond_not_taken_branch_cost */ + &thunderx_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + +static const advsimd_vec_cost tsv110_advsimd_vector_cost = +{ + 2, /* int_stmt_cost */ + 2, /* fp_stmt_cost */ + 2, /* permute_cost */ + 3, /* vec_to_scalar_cost */ + 2, /* scalar_to_vec_cost */ + 5, /* align_load_cost */ + 5, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ }; static const struct cpu_vector_cost tsv110_vector_cost = @@ -625,37 +736,49 @@ static const struct cpu_vector_cost tsv110_vector_cost = 1, /* scalar_fp_stmt_cost */ 5, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 2, /* vec_int_stmt_cost */ - 2, /* vec_fp_stmt_cost */ - 2, /* vec_permute_cost */ - 3, /* vec_to_scalar_cost */ - 2, /* scalar_to_vec_cost */ - 5, /* vec_align_load_cost */ - 5, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 1, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &tsv110_advsimd_vector_cost, /* advsimd */ + NULL, /* sve */ }; -/* Generic costs for vector insn classes. */ +static const advsimd_vec_cost cortexa57_advsimd_vector_cost = +{ + 2, /* int_stmt_cost */ + 2, /* fp_stmt_cost */ + 3, /* permute_cost */ + 8, /* vec_to_scalar_cost */ + 8, /* scalar_to_vec_cost */ + 4, /* align_load_cost */ + 4, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ +}; + +/* Cortex-A57 costs for vector insn classes. */ static const struct cpu_vector_cost cortexa57_vector_cost = { 1, /* scalar_int_stmt_cost */ 1, /* scalar_fp_stmt_cost */ 4, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 2, /* vec_int_stmt_cost */ - 2, /* vec_fp_stmt_cost */ - 3, /* vec_permute_cost */ - 8, /* vec_to_scalar_cost */ - 8, /* scalar_to_vec_cost */ - 4, /* vec_align_load_cost */ - 4, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 1, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &cortexa57_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + +static const advsimd_vec_cost exynosm1_advsimd_vector_cost = +{ + 3, /* int_stmt_cost */ + 3, /* fp_stmt_cost */ + 3, /* permute_cost */ + 3, /* vec_to_scalar_cost */ + 3, /* scalar_to_vec_cost */ + 5, /* align_load_cost */ + 5, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ }; static const struct cpu_vector_cost exynosm1_vector_cost = @@ -664,17 +787,23 @@ static const struct cpu_vector_cost exynosm1_vector_cost = 1, /* scalar_fp_stmt_cost */ 5, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 3, /* vec_int_stmt_cost */ - 3, /* vec_fp_stmt_cost */ - 3, /* vec_permute_cost */ - 3, /* vec_to_scalar_cost */ - 3, /* scalar_to_vec_cost */ - 5, /* vec_align_load_cost */ - 5, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 1, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &exynosm1_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + +static const advsimd_vec_cost xgene1_advsimd_vector_cost = +{ + 2, /* int_stmt_cost */ + 2, /* fp_stmt_cost */ + 2, /* permute_cost */ + 4, /* vec_to_scalar_cost */ + 4, /* scalar_to_vec_cost */ + 10, /* align_load_cost */ + 10, /* unalign_load_cost */ + 2, /* unalign_store_cost */ + 2 /* store_cost */ }; /* Generic costs for vector insn classes. */ @@ -684,17 +813,23 @@ static const struct cpu_vector_cost xgene1_vector_cost = 1, /* scalar_fp_stmt_cost */ 5, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 2, /* vec_int_stmt_cost */ - 2, /* vec_fp_stmt_cost */ - 2, /* vec_permute_cost */ - 4, /* vec_to_scalar_cost */ - 4, /* scalar_to_vec_cost */ - 10, /* vec_align_load_cost */ - 10, /* vec_unalign_load_cost */ - 2, /* vec_unalign_store_cost */ - 2, /* vec_store_cost */ 2, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &xgene1_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + +static const advsimd_vec_cost thunderx2t99_advsimd_vector_cost = +{ + 4, /* int_stmt_cost */ + 5, /* fp_stmt_cost */ + 10, /* permute_cost */ + 6, /* vec_to_scalar_cost */ + 5, /* scalar_to_vec_cost */ + 4, /* align_load_cost */ + 4, /* unalign_load_cost */ + 1, /* unalign_store_cost */ + 1 /* store_cost */ }; /* Costs for vector insn classes for Vulcan. */ @@ -704,17 +839,23 @@ static const struct cpu_vector_cost thunderx2t99_vector_cost = 6, /* scalar_fp_stmt_cost */ 4, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 4, /* vec_int_stmt_cost */ - 5, /* vec_fp_stmt_cost */ - 10, /* vec_permute_cost */ - 6, /* vec_to_scalar_cost */ - 5, /* scalar_to_vec_cost */ - 4, /* vec_align_load_cost */ - 4, /* vec_unalign_load_cost */ - 1, /* vec_unalign_store_cost */ - 1, /* vec_store_cost */ 2, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &thunderx2t99_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ +}; + +static const advsimd_vec_cost thunderx3t110_advsimd_vector_cost = +{ + 5, /* int_stmt_cost */ + 5, /* fp_stmt_cost */ + 10, /* permute_cost */ + 5, /* vec_to_scalar_cost */ + 5, /* scalar_to_vec_cost */ + 4, /* align_load_cost */ + 4, /* unalign_load_cost */ + 4, /* unalign_store_cost */ + 4 /* store_cost */ }; static const struct cpu_vector_cost thunderx3t110_vector_cost = @@ -723,17 +864,10 @@ static const struct cpu_vector_cost thunderx3t110_vector_cost = 5, /* scalar_fp_stmt_cost */ 4, /* scalar_load_cost */ 1, /* scalar_store_cost */ - 5, /* vec_int_stmt_cost */ - 5, /* vec_fp_stmt_cost */ - 10, /* vec_permute_cost */ - 5, /* vec_to_scalar_cost */ - 5, /* scalar_to_vec_cost */ - 4, /* vec_align_load_cost */ - 4, /* vec_unalign_load_cost */ - 4, /* vec_unalign_store_cost */ - 4, /* vec_store_cost */ 2, /* cond_taken_branch_cost */ - 1 /* cond_not_taken_branch_cost */ + 1, /* cond_not_taken_branch_cost */ + &thunderx3t110_advsimd_vector_cost, /* advsimd */ + NULL /* sve */ }; @@ -1390,10 +1524,10 @@ static const struct tune_params neoversen2_tunings = static const struct tune_params a64fx_tunings = { - &generic_extra_costs, - &generic_addrcost_table, - &generic_regmove_cost, - &generic_vector_cost, + &a64fx_extra_costs, + &a64fx_addrcost_table, + &a64fx_regmove_cost, + &a64fx_vector_cost, &generic_branch_cost, &generic_approx_modes, SVE_512, /* sve_width */ @@ -5154,8 +5288,11 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm) switch (sty) { case SYMBOL_FORCE_TO_MEM: + if (int_mode != ptr_mode) + imm = convert_memory_address (ptr_mode, imm); + if (const_offset != 0 - && targetm.cannot_force_const_mem (int_mode, imm)) + && targetm.cannot_force_const_mem (ptr_mode, imm)) { gcc_assert (can_create_pseudo_p ()); base = aarch64_force_temporary (int_mode, dest, base); @@ -7366,7 +7503,18 @@ offset_4bit_signed_scaled_p (machine_mode mode, poly_int64 offset) && IN_RANGE (multiple, -8, 7)); } -/* Return true if OFFSET is a unsigned 6-bit value multiplied by the size +/* Return true if OFFSET is a signed 6-bit value multiplied by the size + of MODE. */ + +static inline bool +offset_6bit_signed_scaled_p (machine_mode mode, poly_int64 offset) +{ + HOST_WIDE_INT multiple; + return (constant_multiple_p (offset, GET_MODE_SIZE (mode), &multiple) + && IN_RANGE (multiple, -32, 31)); +} + +/* Return true if OFFSET is an unsigned 6-bit value multiplied by the size of MODE. */ static inline bool @@ -11912,10 +12060,11 @@ aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode mode, rtx mask, rtx shft_amnt) { return CONST_INT_P (mask) && CONST_INT_P (shft_amnt) - && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode) - && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0 - && (INTVAL (mask) - & ((HOST_WIDE_INT_1U << INTVAL (shft_amnt)) - 1)) == 0; + && INTVAL (mask) > 0 + && UINTVAL (shft_amnt) < GET_MODE_BITSIZE (mode) + && exact_log2 ((UINTVAL (mask) >> UINTVAL (shft_amnt)) + 1) >= 0 + && (UINTVAL (mask) + & ((HOST_WIDE_INT_1U << UINTVAL (shft_amnt)) - 1)) == 0; } /* Return true if the masks and a shift amount from an RTX of the form @@ -13712,6 +13861,13 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, if (vectype != NULL) fp = FLOAT_TYPE_P (vectype); + const simd_vec_cost *simd_costs; + if (vectype != NULL && aarch64_sve_mode_p (TYPE_MODE (vectype)) + && costs->sve != NULL) + simd_costs = costs->sve; + else + simd_costs = costs->advsimd; + switch (type_of_cost) { case scalar_stmt: @@ -13724,27 +13880,28 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, return costs->scalar_store_cost; case vector_stmt: - return fp ? costs->vec_fp_stmt_cost : costs->vec_int_stmt_cost; + return fp ? simd_costs->fp_stmt_cost + : simd_costs->int_stmt_cost; case vector_load: - return costs->vec_align_load_cost; + return simd_costs->align_load_cost; case vector_store: - return costs->vec_store_cost; + return simd_costs->store_cost; case vec_to_scalar: - return costs->vec_to_scalar_cost; + return simd_costs->vec_to_scalar_cost; case scalar_to_vec: - return costs->scalar_to_vec_cost; + return simd_costs->scalar_to_vec_cost; case unaligned_load: case vector_gather_load: - return costs->vec_unalign_load_cost; + return simd_costs->unalign_load_cost; case unaligned_store: case vector_scatter_store: - return costs->vec_unalign_store_cost; + return simd_costs->unalign_store_cost; case cond_branch_taken: return costs->cond_taken_branch_cost; @@ -13753,10 +13910,11 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, return costs->cond_not_taken_branch_cost; case vec_perm: - return costs->vec_permute_cost; + return simd_costs->permute_cost; case vec_promote_demote: - return fp ? costs->vec_fp_stmt_cost : costs->vec_int_stmt_cost; + return fp ? simd_costs->fp_stmt_cost + : simd_costs->int_stmt_cost; case vec_construct: elements = estimated_poly_value (TYPE_VECTOR_SUBPARTS (vectype)); @@ -17288,8 +17446,6 @@ aarch64_simd_container_mode (scalar_mode mode, poly_int64 width) return word_mode; } -static HOST_WIDE_INT aarch64_estimated_poly_value (poly_int64); - /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M and return whether the SVE mode should be preferred over the Advanced SIMD one in aarch64_autovectorize_vector_modes. */ @@ -17322,8 +17478,8 @@ aarch64_cmp_autovec_modes (machine_mode sve_m, machine_mode asimd_m) return maybe_gt (nunits_sve, nunits_asimd); /* Otherwise estimate the runtime width of the modes involved. */ - HOST_WIDE_INT est_sve = aarch64_estimated_poly_value (nunits_sve); - HOST_WIDE_INT est_asimd = aarch64_estimated_poly_value (nunits_asimd); + HOST_WIDE_INT est_sve = estimated_poly_value (nunits_sve); + HOST_WIDE_INT est_asimd = estimated_poly_value (nunits_asimd); /* Preferring SVE means picking it first unless the Advanced SIMD mode is clearly wider. */ @@ -17344,10 +17500,11 @@ aarch64_preferred_simd_mode (scalar_mode mode) { /* Take into account explicit auto-vectorization ISA preferences through aarch64_cmp_autovec_modes. */ - poly_int64 bits - = (TARGET_SVE && aarch64_cmp_autovec_modes (VNx16QImode, V16QImode)) - ? BITS_PER_SVE_VECTOR : 128; - return aarch64_simd_container_mode (mode, bits); + if (TARGET_SVE && aarch64_cmp_autovec_modes (VNx16QImode, V16QImode)) + return aarch64_full_sve_mode (mode).else_mode (word_mode); + if (TARGET_SIMD) + return aarch64_vq_mode (mode).else_mode (word_mode); + return word_mode; } /* Return a list of possible vector sizes for the vectorizer @@ -18416,11 +18573,11 @@ bool aarch64_sve_prefetch_operand_p (rtx op, machine_mode mode) { struct aarch64_address_info addr; - if (!aarch64_classify_address (&addr, op, mode, false)) + if (!aarch64_classify_address (&addr, op, mode, false, ADDR_QUERY_ANY)) return false; if (addr.type == ADDRESS_REG_IMM) - return known_eq (addr.const_offset, 0); + return offset_6bit_signed_scaled_p (mode, addr.const_offset); return addr.type == ADDRESS_REG_REG; } @@ -20928,8 +21085,11 @@ aarch64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, d.vmode = vmode; d.vec_flags = aarch64_classify_vector_mode (d.vmode); d.target = target; - d.op0 = op0; - d.op1 = op1; + d.op0 = op0 ? force_reg (vmode, op0) : NULL_RTX; + if (op0 == op1) + d.op1 = d.op0; + else + d.op1 = op1 ? force_reg (vmode, op1) : NULL_RTX; d.testing_p = !target; if (!d.testing_p) @@ -23116,19 +23276,38 @@ aarch64_speculation_safe_value (machine_mode mode, /* Implement TARGET_ESTIMATED_POLY_VALUE. Look into the tuning structure for an estimate. - VAL.coeffs[1] is multiplied by the number of VQ chunks over the initial - Advanced SIMD 128 bits. */ + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known SVE width all three estimates are the same. + For generic SVE tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with SVE when it is a win + even for 128-bit SVE. + When SVE width information is available VAL.coeffs[1] is multiplied by + the number of VQ chunks over the initial Advanced SIMD 128 bits. */ static HOST_WIDE_INT -aarch64_estimated_poly_value (poly_int64 val) +aarch64_estimated_poly_value (poly_int64 val, + poly_value_estimate_kind kind + = POLY_VALUE_LIKELY) { enum aarch64_sve_vector_bits_enum width_source = aarch64_tune_params.sve_width; - /* If we still don't have an estimate, use the default. */ + /* If there is no core-specific information then the minimum and likely + values are based on 128-bit vectors and the maximum is based on + the architectural maximum of 2048 bits. */ if (width_source == SVE_SCALABLE) - return default_estimated_poly_value (val); + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * 15; + } + /* If the core provides width information, use that. */ HOST_WIDE_INT over_128 = width_source - 128; return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 0bdcc74..d0bae61 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -227,6 +227,9 @@ extern unsigned aarch64_architecture_version; /* Flag Manipulation Instructions (FLAGM) extension. */ #define AARCH64_FL_FLAGM (1ULL << 39) +/* Pointer Authentication (PAUTH) extension. */ +#define AARCH64_FL_PAUTH (1ULL << 40) + /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -241,7 +244,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_FOR_ARCH8_2 \ (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) #define AARCH64_FL_FOR_ARCH8_3 \ - (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3) + (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3 | AARCH64_FL_PAUTH) #define AARCH64_FL_FOR_ARCH8_4 \ (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \ | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4 | AARCH64_FL_FLAGM) @@ -290,6 +293,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) #define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) #define AARCH64_ISA_V8_R (aarch64_isa_flags & AARCH64_FL_V8_R) +#define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) @@ -378,6 +382,9 @@ extern unsigned aarch64_architecture_version; #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) +/* PAUTH instructions are enabled through +pauth. */ +#define TARGET_PAUTH (AARCH64_ISA_PAUTH) + /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT @@ -1212,12 +1219,14 @@ extern enum aarch64_code_model aarch64_cmodel; #define ENDIAN_LANE_N(NUNITS, N) \ (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) -/* Support for a configure-time default CPU, etc. We currently support - --with-arch and --with-cpu. Both are ignored if either is specified - explicitly on the command line at run time. */ +/* Support for configure-time --with-arch, --with-cpu and --with-tune. + --with-arch and --with-cpu are ignored if either -mcpu or -march is used. + --with-tune is ignored if either -mtune or -mcpu is used (but is not + affected by -march). */ #define OPTION_DEFAULT_SPECS \ {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ - {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, + {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, #define MCPU_TO_MARCH_SPEC \ " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index eed06de..a482419 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -197,6 +197,8 @@ UNSPEC_REV UNSPEC_RBIT UNSPEC_SABAL + UNSPEC_SABAL2 + UNSPEC_SABDL UNSPEC_SABDL2 UNSPEC_SADALP UNSPEC_SCVTF @@ -218,6 +220,8 @@ UNSPEC_TLSLE32 UNSPEC_TLSLE48 UNSPEC_UABAL + UNSPEC_UABAL2 + UNSPEC_UABDL UNSPEC_UABDL2 UNSPEC_UADALP UNSPEC_UCVTF @@ -226,6 +230,7 @@ UNSPEC_SSP_SYSREG UNSPEC_SP_SET UNSPEC_SP_TEST + UNSPEC_RSHRN UNSPEC_RSQRT UNSPEC_RSQRTE UNSPEC_RSQRTS @@ -873,7 +878,7 @@ { const char *ret = NULL; if (aarch64_return_address_signing_enabled () - && TARGET_ARMV8_3 + && (TARGET_PAUTH) && !crtl->calls_eh_return) { if (aarch64_ra_sign_key == AARCH64_KEY_B) @@ -2474,7 +2479,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) ;; zero_extend version of above @@ -2486,7 +2491,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) (define_insn "*add_<optab><ALLX:mode>_<GPI:mode>" @@ -3121,7 +3126,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "sub\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) ;; zero_extend version of above @@ -3134,7 +3139,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "sub\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) (define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>" @@ -3535,7 +3540,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "neg\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) ;; zero_extend version of above @@ -3547,7 +3552,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "neg\\t%w0, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_<shift>_op2")] ) (define_insn "mul<mode>3" @@ -5724,10 +5729,10 @@ { case 0: operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[3]))); - return "bfxil\\t%0, %1, 0, %3"; + return "bfxil\\t%w0, %w1, 0, %3"; case 1: operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[4]))); - return "bfxil\\t%0, %2, 0, %3"; + return "bfxil\\t%w0, %w2, 0, %3"; default: gcc_unreachable (); } diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 1b3d942..91e5c61 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -1,5 +1,5 @@ ; Machine description for AArch64 architecture. -; Copyright (C) 2009-2020 Free Software Foundation, Inc. +; Copyright (C) 2009-2021 Free Software Foundation, Inc. ; Contributed by ARM Ltd. ; ; This file is part of GCC. @@ -64,11 +64,11 @@ EnumValue Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) mbig-endian -Target Report RejectNegative Mask(BIG_END) +Target RejectNegative Mask(BIG_END) Assume target CPU is configured as big endian. mgeneral-regs-only -Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save +Target RejectNegative Mask(GENERAL_REGS_ONLY) Save Generate code which uses only the general registers. mharden-sls= @@ -76,15 +76,15 @@ Target RejectNegative Joined Var(aarch64_harden_sls_string) Generate code to mitigate against straight line speculation. mfix-cortex-a53-835769 -Target Report Var(aarch64_fix_a53_err835769) Init(2) Save +Target Var(aarch64_fix_a53_err835769) Init(2) Save Workaround for ARM Cortex-A53 Erratum number 835769. mfix-cortex-a53-843419 -Target Report Var(aarch64_fix_a53_err843419) Init(2) Save +Target Var(aarch64_fix_a53_err843419) Init(2) Save Workaround for ARM Cortex-A53 Erratum number 843419. mlittle-endian -Target Report RejectNegative InverseMask(BIG_END) +Target RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian. mcmodel= @@ -92,11 +92,11 @@ Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_C Specify the code model. mstrict-align -Target Report Mask(STRICT_ALIGN) Save +Target Mask(STRICT_ALIGN) Save Don't assume that unaligned accesses are handled by the system. momit-leaf-frame-pointer -Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save +Target Var(flag_omit_leaf_frame_pointer) Init(2) Save Omit the frame pointer in leaf functions. mtls-dialect= @@ -153,7 +153,7 @@ EnumValue Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) mpc-relative-literal-loads -Target Report Save Var(pcrelative_literal_loads) Init(2) Save +Target Save Var(pcrelative_literal_loads) Init(2) Save PC relative literal loads. mbranch-protection= @@ -260,7 +260,7 @@ TargetVariable long aarch64_stack_protector_guard_offset = 0 moutline-atomics -Target Report Var(aarch64_flag_outline_atomics) Init(2) Save +Target Var(aarch64_flag_outline_atomics) Init(2) Save Generate local calls to out-of-line atomic operations. -param=aarch64-sve-compare-costs= diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index f58568f..73b29f4 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -1,6 +1,6 @@ /* AArch64 Non-NEON ACLE intrinsics include file. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/arm_bf16.h b/gcc/config/aarch64/arm_bf16.h index 8816154..59ed67f 100644 --- a/gcc/config/aarch64/arm_bf16.h +++ b/gcc/config/aarch64/arm_bf16.h @@ -1,6 +1,6 @@ /* Arm BF16 instrinsics include file. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Arm. This file is part of GCC. diff --git a/gcc/config/aarch64/arm_fp16.h b/gcc/config/aarch64/arm_fp16.h index 6587615..2afbd12 100644 --- a/gcc/config/aarch64/arm_fp16.h +++ b/gcc/config/aarch64/arm_fp16.h @@ -1,6 +1,6 @@ /* ARM FP16 scalar intrinsics include file. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index d79c1a2..4b905d9 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -1,6 +1,6 @@ /* ARM NEON intrinsics include file. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -6621,696 +6621,406 @@ __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) { - int8x8_t __result; - __asm__ ("saba %0.8b,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav8qi (__a, __b, __c); } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) { - int16x4_t __result; - __asm__ ("saba %0.4h,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) { - int32x2_t __result; - __asm__ ("saba %0.2s,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav2si (__a, __b, __c); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint8x8_t __result; - __asm__ ("uaba %0.8b,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav8qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint16x4_t __result; - __asm__ ("uaba %0.4h,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaba_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint32x2_t __result; - __asm__ ("uaba %0.2s,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav2si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c) { - int16x8_t __result; - __asm__ ("sabal2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabal2v16qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) { - int32x4_t __result; - __asm__ ("sabal2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabal2v8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) { - int64x2_t __result; - __asm__ ("sabal2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabal2v4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c) { - uint16x8_t __result; - __asm__ ("uabal2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabal2v16qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c) { - uint32x4_t __result; - __asm__ ("uabal2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabal2v8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) { - uint64x2_t __result; - __asm__ ("uabal2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabal2v4si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) { - int16x8_t __result; - __asm__ ("sabal %0.8h,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabalv8qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) { - int32x4_t __result; - __asm__ ("sabal %0.4s,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabalv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) { - int64x2_t __result; - __asm__ ("sabal %0.2d,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabalv2si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint16x8_t __result; - __asm__ ("uabal %0.8h,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabalv8qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint32x4_t __result; - __asm__ ("uabal %0.4s,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabalv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint64x2_t __result; - __asm__ ("uabal %0.2d,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabalv2si_uuuu (__a, __b, __c); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) { - int8x16_t __result; - __asm__ ("saba %0.16b,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav16qi (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) { - int16x8_t __result; - __asm__ ("saba %0.8h,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) { - int32x4_t __result; - __asm__ ("saba %0.4s,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabav4si (__a, __b, __c); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) { - uint8x16_t __result; - __asm__ ("uaba %0.16b,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav16qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) { - uint16x8_t __result; - __asm__ ("uaba %0.8h,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) { - uint32x4_t __result; - __asm__ ("uaba %0.4s,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabav4si_uuuu (__a, __b, __c); } __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_s8 (int8x8_t __a, int8x8_t __b) { - int8x8_t __result; - __asm__ ("sabd %0.8b, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv8qi (__a, __b); } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_s16 (int16x4_t __a, int16x4_t __b) { - int16x4_t __result; - __asm__ ("sabd %0.4h, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv4hi (__a, __b); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_s32 (int32x2_t __a, int32x2_t __b) { - int32x2_t __result; - __asm__ ("sabd %0.2s, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv2si (__a, __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_u8 (uint8x8_t __a, uint8x8_t __b) { - uint8x8_t __result; - __asm__ ("uabd %0.8b, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv8qi_uuu (__a, __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_u16 (uint16x4_t __a, uint16x4_t __b) { - uint16x4_t __result; - __asm__ ("uabd %0.4h, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv4hi_uuu (__a, __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabd_u32 (uint32x2_t __a, uint32x2_t __b) { - uint32x2_t __result; - __asm__ ("uabd %0.2s, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv2si_uuu (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s8 (int8x16_t __a, int8x16_t __b) { - int16x8_t __result; - __asm__ ("sabdl2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v16qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s16 (int16x8_t __a, int16x8_t __b) { - int32x4_t __result; - __asm__ ("sabdl2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v8hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_s32 (int32x4_t __a, int32x4_t __b) { - int64x2_t __result; - __asm__ ("sabdl2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdl2v4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u8 (uint8x16_t __a, uint8x16_t __b) { - uint16x8_t __result; - __asm__ ("uabdl2 %0.8h,%1.16b,%2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v16qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u16 (uint16x8_t __a, uint16x8_t __b) { - uint32x4_t __result; - __asm__ ("uabdl2 %0.4s,%1.8h,%2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v8hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_high_u32 (uint32x4_t __a, uint32x4_t __b) { - uint64x2_t __result; - __asm__ ("uabdl2 %0.2d,%1.4s,%2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdl2v4si_uuu (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_s8 (int8x8_t __a, int8x8_t __b) { - int16x8_t __result; - __asm__ ("sabdl %0.8h, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdlv8qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_s16 (int16x4_t __a, int16x4_t __b) { - int32x4_t __result; - __asm__ ("sabdl %0.4s, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdlv4hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_s32 (int32x2_t __a, int32x2_t __b) { - int64x2_t __result; - __asm__ ("sabdl %0.2d, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdlv2si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_u8 (uint8x8_t __a, uint8x8_t __b) { - uint16x8_t __result; - __asm__ ("uabdl %0.8h, %1.8b, %2.8b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdlv8qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_u16 (uint16x4_t __a, uint16x4_t __b) { - uint32x4_t __result; - __asm__ ("uabdl %0.4s, %1.4h, %2.4h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdlv4hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdl_u32 (uint32x2_t __a, uint32x2_t __b) { - uint64x2_t __result; - __asm__ ("uabdl %0.2d, %1.2s, %2.2s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdlv2si_uuu (__a, __b); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_s8 (int8x16_t __a, int8x16_t __b) { - int8x16_t __result; - __asm__ ("sabd %0.16b, %1.16b, %2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv16qi (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_s16 (int16x8_t __a, int16x8_t __b) { - int16x8_t __result; - __asm__ ("sabd %0.8h, %1.8h, %2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv8hi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_s32 (int32x4_t __a, int32x4_t __b) { - int32x4_t __result; - __asm__ ("sabd %0.4s, %1.4s, %2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sabdv4si (__a, __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_u8 (uint8x16_t __a, uint8x16_t __b) { - uint8x16_t __result; - __asm__ ("uabd %0.16b, %1.16b, %2.16b" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv16qi_uuu (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_u16 (uint16x8_t __a, uint16x8_t __b) { - uint16x8_t __result; - __asm__ ("uabd %0.8h, %1.8h, %2.8h" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv8hi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vabdq_u32 (uint32x4_t __a, uint32x4_t __b) { - uint32x4_t __result; - __asm__ ("uabd %0.4s, %1.4s, %2.4s" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uabdv4si_uuu (__a, __b); } __extension__ extern __inline int16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_s8 (int8x8_t __a) { - int16_t __result; - __asm__ ("saddlv %h0,%1.8b" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_saddlvv8qi (__a); } __extension__ extern __inline int32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_s16 (int16x4_t __a) { - int32_t __result; - __asm__ ("saddlv %s0,%1.4h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_saddlvv4hi (__a); } __extension__ extern __inline uint16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_u8 (uint8x8_t __a) { - uint16_t __result; - __asm__ ("uaddlv %h0,%1.8b" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uaddlvv8qi_uu (__a); } __extension__ extern __inline uint32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_u16 (uint16x4_t __a) { - uint32_t __result; - __asm__ ("uaddlv %s0,%1.4h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uaddlvv4hi_uu (__a); } __extension__ extern __inline int16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_s8 (int8x16_t __a) { - int16_t __result; - __asm__ ("saddlv %h0,%1.16b" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_saddlvv16qi (__a); } __extension__ extern __inline int32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_s16 (int16x8_t __a) { - int32_t __result; - __asm__ ("saddlv %s0,%1.8h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_saddlvv8hi (__a); } __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_s32 (int32x4_t __a) { - int64_t __result; - __asm__ ("saddlv %d0,%1.4s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_saddlvv4si (__a); } __extension__ extern __inline uint16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_u8 (uint8x16_t __a) { - uint16_t __result; - __asm__ ("uaddlv %h0,%1.16b" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uaddlvv16qi_uu (__a); } __extension__ extern __inline uint32_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_u16 (uint16x8_t __a) { - uint32_t __result; - __asm__ ("uaddlv %s0,%1.8h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uaddlvv8hi_uu (__a); } __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlvq_u32 (uint32x4_t __a) { - uint64_t __result; - __asm__ ("uaddlv %d0,%1.4s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uaddlvv4si_uu (__a); } __extension__ extern __inline float32x2_t @@ -7366,120 +7076,80 @@ __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c) { - int16x4_t __result; - __asm__ ("mla %0.4h,%2.4h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mla_nv4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c) { - int32x2_t __result; - __asm__ ("mla %0.2s,%2.2s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mla_nv2si (__a, __b, __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c) { - uint16x4_t __result; - __asm__ ("mla %0.4h,%2.4h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_mla_nv4hi ((int16x4_t) __a, + (int16x4_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c) { - uint32x2_t __result; - __asm__ ("mla %0.2s,%2.2s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_mla_nv2si ((int32x2_t) __a, + (int32x2_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) { - int8x8_t __result; - __asm__ ("mla %0.8b, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav8qi (__a, __b, __c); } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) { - int16x4_t __result; - __asm__ ("mla %0.4h, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) { - int32x2_t __result; - __asm__ ("mla %0.2s, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav2si (__a, __b, __c); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint8x8_t __result; - __asm__ ("mla %0.8b, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint8x8_t) __builtin_aarch64_mlav8qi ((int8x8_t) __a, + (int8x8_t) __b, + (int8x8_t) __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint16x4_t __result; - __asm__ ("mla %0.4h, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_mlav4hi ((int16x4_t) __a, + (int16x4_t) __b, + (int16x4_t) __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmla_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint32x2_t __result; - __asm__ ("mla %0.2s, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_mlav2si ((int32x2_t) __a, + (int32x2_t) __b, + (int32x2_t) __c); } #define vmlal_high_lane_s16(a, b, c, d) \ @@ -7774,120 +7444,70 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlal %0.4s,%2.4h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_nv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlal %0.2d,%2.2s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlal_nv2si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlal %0.4s,%2.4h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_nv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlal %0.2d,%2.2s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlal_nv2si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) { - int16x8_t __result; - __asm__ ("smlal %0.8h,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlalv8qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) { - int32x4_t __result; - __asm__ ("smlal %0.4s,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlalv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) { - int64x2_t __result; - __asm__ ("smlal %0.2d,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlalv2si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint16x8_t __result; - __asm__ ("umlal %0.8h,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlalv8qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint32x4_t __result; - __asm__ ("umlal %0.4s,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlalv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlal_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint64x2_t __result; - __asm__ ("umlal %0.2d,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlalv2si_uuuu (__a, __b, __c); } __extension__ extern __inline float32x4_t @@ -7907,120 +7527,80 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) { - int16x8_t __result; - __asm__ ("mla %0.8h,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mla_nv8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) { - int32x4_t __result; - __asm__ ("mla %0.4s,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mla_nv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) { - uint16x8_t __result; - __asm__ ("mla %0.8h,%2.8h,%3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x8_t) __builtin_aarch64_mla_nv8hi ((int16x8_t) __a, + (int16x8_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) { - uint32x4_t __result; - __asm__ ("mla %0.4s,%2.4s,%3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x4_t) __builtin_aarch64_mla_nv4si ((int32x4_t) __a, + (int32x4_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) { - int8x16_t __result; - __asm__ ("mla %0.16b, %2.16b, %3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav16qi (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) { - int16x8_t __result; - __asm__ ("mla %0.8h, %2.8h, %3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) { - int32x4_t __result; - __asm__ ("mla %0.4s, %2.4s, %3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlav4si (__a, __b, __c); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) { - uint8x16_t __result; - __asm__ ("mla %0.16b, %2.16b, %3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint8x16_t) __builtin_aarch64_mlav16qi ((int8x16_t) __a, + (int8x16_t) __b, + (int8x16_t) __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) { - uint16x8_t __result; - __asm__ ("mla %0.8h, %2.8h, %3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint16x8_t) __builtin_aarch64_mlav8hi ((int16x8_t) __a, + (int16x8_t) __b, + (int16x8_t) __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlaq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) { - uint32x4_t __result; - __asm__ ("mla %0.4s, %2.4s, %3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x4_t) __builtin_aarch64_mlav4si ((int32x4_t) __a, + (int32x4_t) __b, + (int32x4_t) __c); } __extension__ extern __inline float32x2_t @@ -8040,120 +7620,80 @@ __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_s16 (int16x4_t __a, int16x4_t __b, int16_t __c) { - int16x4_t __result; - __asm__ ("mls %0.4h, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_s32 (int32x2_t __a, int32x2_t __b, int32_t __c) { - int32x2_t __result; - __asm__ ("mls %0.2s, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv2si (__a, __b, __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_u16 (uint16x4_t __a, uint16x4_t __b, uint16_t __c) { - uint16x4_t __result; - __asm__ ("mls %0.4h, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_mls_nv4hi ((int16x4_t) __a, + (int16x4_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_n_u32 (uint32x2_t __a, uint32x2_t __b, uint32_t __c) { - uint32x2_t __result; - __asm__ ("mls %0.2s, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_mls_nv2si ((int32x2_t) __a, + (int32x2_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c) { - int8x8_t __result; - __asm__ ("mls %0.8b,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv8qi (__a, __b, __c); } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) { - int16x4_t __result; - __asm__ ("mls %0.4h,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv4hi (__a, __b, __c); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) { - int32x2_t __result; - __asm__ ("mls %0.2s,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv2si (__a, __b, __c); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_u8 (uint8x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint8x8_t __result; - __asm__ ("mls %0.8b,%2.8b,%3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint8x8_t) __builtin_aarch64_mlsv8qi ((int8x8_t) __a, + (int8x8_t) __b, + (int8x8_t) __c); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_u16 (uint16x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint16x4_t __result; - __asm__ ("mls %0.4h,%2.4h,%3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_mlsv4hi ((int16x4_t) __a, + (int16x4_t) __b, + (int16x4_t) __c); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmls_u32 (uint32x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint32x2_t __result; - __asm__ ("mls %0.2s,%2.2s,%3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_mlsv2si ((int32x2_t) __a, + (int32x2_t) __b, + (int32x2_t) __c); } #define vmlsl_high_lane_s16(a, b, c, d) \ @@ -8320,304 +7860,172 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s8 (int16x8_t __a, int8x16_t __b, int8x16_t __c) { - int16x8_t __result; - __asm__ ("smlsl2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv16qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) { - int32x4_t __result; - __asm__ ("smlsl2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv8hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) { - int64x2_t __result; - __asm__ ("smlsl2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_hiv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u8 (uint16x8_t __a, uint8x16_t __b, uint8x16_t __c) { - uint16x8_t __result; - __asm__ ("umlsl2 %0.8h,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv16qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u16 (uint32x4_t __a, uint16x8_t __b, uint16x8_t __c) { - uint32x4_t __result; - __asm__ ("umlsl2 %0.4s,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv8hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_high_u32 (uint64x2_t __a, uint32x4_t __b, uint32x4_t __c) { - uint64x2_t __result; - __asm__ ("umlsl2 %0.2d,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_hiv4si_uuuu (__a, __b, __c); } -#define vmlsl_lane_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x4_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_lane_v4hi (__a, __b, __v, __lane); +} -#define vmlsl_lane_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x2_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_lane_v2si (__a, __b, __v, __lane); +} -#define vmlsl_lane_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x4_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_lane_v4hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_lane_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x2_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_lane_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_lane_v2si_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_laneq_s16(a, b, c, d) \ - __extension__ \ - ({ \ - int16x8_t c_ = (c); \ - int16x4_t b_ = (b); \ - int32x4_t a_ = (a); \ - int32x4_t result; \ - __asm__ ("smlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_s16 (int32x4_t __a, int16x4_t __b, int16x8_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_laneq_v4hi (__a, __b, __v, __lane); +} -#define vmlsl_laneq_s32(a, b, c, d) \ - __extension__ \ - ({ \ - int32x4_t c_ = (c); \ - int32x2_t b_ = (b); \ - int64x2_t a_ = (a); \ - int64x2_t result; \ - __asm__ ("smlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __v, const int __lane) +{ + return __builtin_aarch64_vec_smlsl_laneq_v2si (__a, __b, __v, __lane); +} -#define vmlsl_laneq_u16(a, b, c, d) \ - __extension__ \ - ({ \ - uint16x8_t c_ = (c); \ - uint16x4_t b_ = (b); \ - uint32x4_t a_ = (a); \ - uint32x4_t result; \ - __asm__ ("umlsl %0.4s, %2.4h, %3.h[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "x"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_u16 (uint32x4_t __a, uint16x4_t __b, uint16x8_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_laneq_v4hi_uuuus (__a, __b, __v, __lane); +} -#define vmlsl_laneq_u32(a, b, c, d) \ - __extension__ \ - ({ \ - uint32x4_t c_ = (c); \ - uint32x2_t b_ = (b); \ - uint64x2_t a_ = (a); \ - uint64x2_t result; \ - __asm__ ("umlsl %0.2d, %2.2s, %3.s[%4]" \ - : "=w"(result) \ - : "0"(a_), "w"(b_), "w"(c_), "i"(d) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmlsl_laneq_u32 (uint64x2_t __a, uint32x2_t __b, uint32x4_t __v, + const int __lane) +{ + return __builtin_aarch64_vec_umlsl_laneq_v2si_uuuus (__a, __b, __v, __lane); +} __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c) { - int32x4_t __result; - __asm__ ("smlsl %0.4s, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_nv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c) { - int64x2_t __result; - __asm__ ("smlsl %0.2d, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlsl_nv2si (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_u16 (uint32x4_t __a, uint16x4_t __b, uint16_t __c) { - uint32x4_t __result; - __asm__ ("umlsl %0.4s, %2.4h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_nv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_n_u32 (uint64x2_t __a, uint32x2_t __b, uint32_t __c) { - uint64x2_t __result; - __asm__ ("umlsl %0.2d, %2.2s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlsl_nv2si_uuuu (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s8 (int16x8_t __a, int8x8_t __b, int8x8_t __c) { - int16x8_t __result; - __asm__ ("smlsl %0.8h, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv8qi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c) { - int32x4_t __result; - __asm__ ("smlsl %0.4s, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv4hi (__a, __b, __c); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c) { - int64x2_t __result; - __asm__ ("smlsl %0.2d, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smlslv2si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u8 (uint16x8_t __a, uint8x8_t __b, uint8x8_t __c) { - uint16x8_t __result; - __asm__ ("umlsl %0.8h, %2.8b, %3.8b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv8qi_uuuu (__a, __b, __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u16 (uint32x4_t __a, uint16x4_t __b, uint16x4_t __c) { - uint32x4_t __result; - __asm__ ("umlsl %0.4s, %2.4h, %3.4h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv4hi_uuuu (__a, __b, __c); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsl_u32 (uint64x2_t __a, uint32x2_t __b, uint32x2_t __c) { - uint64x2_t __result; - __asm__ ("umlsl %0.2d, %2.2s, %3.2s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umlslv2si_uuuu (__a, __b, __c); } __extension__ extern __inline float32x4_t @@ -8637,410 +8045,294 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_s16 (int16x8_t __a, int16x8_t __b, int16_t __c) { - int16x8_t __result; - __asm__ ("mls %0.8h, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_s32 (int32x4_t __a, int32x4_t __b, int32_t __c) { - int32x4_t __result; - __asm__ ("mls %0.4s, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mls_nv4si (__a, __b, __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_u16 (uint16x8_t __a, uint16x8_t __b, uint16_t __c) { - uint16x8_t __result; - __asm__ ("mls %0.8h, %2.8h, %3.h[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "x"(__c) - : /* No clobbers */); - return __result; + return (uint16x8_t) __builtin_aarch64_mls_nv8hi ((int16x8_t) __a, + (int16x8_t) __b, + (int16_t) __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_n_u32 (uint32x4_t __a, uint32x4_t __b, uint32_t __c) { - uint32x4_t __result; - __asm__ ("mls %0.4s, %2.4s, %3.s[0]" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x4_t) __builtin_aarch64_mls_nv4si ((int32x4_t) __a, + (int32x4_t) __b, + (int32_t) __c); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c) { - int8x16_t __result; - __asm__ ("mls %0.16b,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv16qi (__a, __b, __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) { - int16x8_t __result; - __asm__ ("mls %0.8h,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv8hi (__a, __b, __c); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) { - int32x4_t __result; - __asm__ ("mls %0.4s,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return __builtin_aarch64_mlsv4si (__a, __b, __c); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_u8 (uint8x16_t __a, uint8x16_t __b, uint8x16_t __c) { - uint8x16_t __result; - __asm__ ("mls %0.16b,%2.16b,%3.16b" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint8x16_t) __builtin_aarch64_mlsv16qi ((int8x16_t) __a, + (int8x16_t) __b, + (int8x16_t) __c); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_u16 (uint16x8_t __a, uint16x8_t __b, uint16x8_t __c) { - uint16x8_t __result; - __asm__ ("mls %0.8h,%2.8h,%3.8h" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint16x8_t) __builtin_aarch64_mlsv8hi ((int16x8_t) __a, + (int16x8_t) __b, + (int16x8_t) __c); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmlsq_u32 (uint32x4_t __a, uint32x4_t __b, uint32x4_t __c) { - uint32x4_t __result; - __asm__ ("mls %0.4s,%2.4s,%3.4s" - : "=w"(__result) - : "0"(__a), "w"(__b), "w"(__c) - : /* No clobbers */); - return __result; + return (uint32x4_t) __builtin_aarch64_mlsv4si ((int32x4_t) __a, + (int32x4_t) __b, + (int32x4_t) __c); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_s8 (int8x16_t __a) { - int16x8_t __result; - __asm__ ("sshll2 %0.8h,%1.16b,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacks_hi_v16qi (__a); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_s16 (int16x8_t __a) { - int32x4_t __result; - __asm__ ("sshll2 %0.4s,%1.8h,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacks_hi_v8hi (__a); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_s32 (int32x4_t __a) { - int64x2_t __result; - __asm__ ("sshll2 %0.2d,%1.4s,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacks_hi_v4si (__a); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_u8 (uint8x16_t __a) { - uint16x8_t __result; - __asm__ ("ushll2 %0.8h,%1.16b,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacku_hi_v16qi_uu (__a); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_u16 (uint16x8_t __a) { - uint32x4_t __result; - __asm__ ("ushll2 %0.4s,%1.8h,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacku_hi_v8hi_uu (__a); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_high_u32 (uint32x4_t __a) { - uint64x2_t __result; - __asm__ ("ushll2 %0.2d,%1.4s,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_vec_unpacku_hi_v4si_uu (__a); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_s8 (int8x8_t __a) { - int16x8_t __result; - __asm__ ("sshll %0.8h,%1.8b,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sxtlv8hi (__a); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_s16 (int16x4_t __a) { - int32x4_t __result; - __asm__ ("sshll %0.4s,%1.4h,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sxtlv4si (__a); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_s32 (int32x2_t __a) { - int64x2_t __result; - __asm__ ("sshll %0.2d,%1.2s,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sxtlv2di (__a); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_u8 (uint8x8_t __a) { - uint16x8_t __result; - __asm__ ("ushll %0.8h,%1.8b,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uxtlv8hi_uu (__a); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_u16 (uint16x4_t __a) { - uint32x4_t __result; - __asm__ ("ushll %0.4s,%1.4h,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uxtlv4si_uu (__a); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovl_u32 (uint32x2_t __a) { - uint64x2_t __result; - __asm__ ("ushll %0.2d,%1.2s,#0" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uxtlv2di_uu (__a); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_s16 (int8x8_t __a, int16x8_t __b) { - int8x16_t __result = vcombine_s8 (__a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.16b,%1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtn2v8hi (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_s32 (int16x4_t __a, int32x4_t __b) { - int16x8_t __result = vcombine_s16 (__a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.8h,%1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtn2v4si (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_s64 (int32x2_t __a, int64x2_t __b) { - int32x4_t __result = vcombine_s32 (__a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.4s,%1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtn2v2di (__a, __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_u16 (uint8x8_t __a, uint16x8_t __b) { - uint8x16_t __result = vcombine_u8 (__a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.16b,%1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return (uint8x16_t) + __builtin_aarch64_xtn2v8hi ((int8x8_t) __a, (int16x8_t) __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_u32 (uint16x4_t __a, uint32x4_t __b) { - uint16x8_t __result = vcombine_u16 (__a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.8h,%1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return (uint16x8_t) + __builtin_aarch64_xtn2v4si ((int16x4_t) __a, (int32x4_t) __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_high_u64 (uint32x2_t __a, uint64x2_t __b) { - uint32x4_t __result = vcombine_u32 (__a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("xtn2 %0.4s,%1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return (uint32x4_t) + __builtin_aarch64_xtn2v2di ((int32x2_t) __a, (int64x2_t) __b); } __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_s16 (int16x8_t __a) { - int8x8_t __result; - __asm__ ("xtn %0.8b,%1.8h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtnv8hi (__a); } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_s32 (int32x4_t __a) { - int16x4_t __result; - __asm__ ("xtn %0.4h,%1.4s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtnv4si (__a); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_s64 (int64x2_t __a) { - int32x2_t __result; - __asm__ ("xtn %0.2s,%1.2d" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_xtnv2di (__a); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_u16 (uint16x8_t __a) { - uint8x8_t __result; - __asm__ ("xtn %0.8b,%1.8h" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return (uint8x8_t)__builtin_aarch64_xtnv8hi ((int16x8_t) __a); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_u32 (uint32x4_t __a) { - uint16x4_t __result; - __asm__ ("xtn %0.4h,%1.4s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return (uint16x4_t) __builtin_aarch64_xtnv4si ((int32x4_t )__a); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmovn_u64 (uint64x2_t __a) { - uint32x2_t __result; - __asm__ ("xtn %0.2s,%1.2d" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return (uint32x2_t) __builtin_aarch64_xtnv2di ((int64x2_t) __a); +} + +__extension__ extern __inline int8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s16 (int16x8_t __a, const int __b) +{ + return __builtin_aarch64_shrnv8hi (__a, __b); +} + +__extension__ extern __inline int16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s32 (int32x4_t __a, const int __b) +{ + return __builtin_aarch64_shrnv4si (__a, __b); +} + +__extension__ extern __inline int32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_s64 (int64x2_t __a, const int __b) +{ + return __builtin_aarch64_shrnv2di (__a, __b); +} + +__extension__ extern __inline uint8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t)__builtin_aarch64_shrnv8hi ((int16x8_t)__a, __b); } +__extension__ extern __inline uint16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t)__builtin_aarch64_shrnv4si ((int32x4_t)__a, __b); +} + +__extension__ extern __inline uint32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b); +} #define vmull_high_lane_s16(a, b, c) \ __extension__ \ ({ \ @@ -9307,48 +8599,28 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_n_s16 (int16x4_t __a, int16_t __b) { - int32x4_t __result; - __asm__ ("smull %0.4s,%1.4h,%2.h[0]" - : "=w"(__result) - : "w"(__a), "x"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smull_nv4hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_n_s32 (int32x2_t __a, int32_t __b) { - int64x2_t __result; - __asm__ ("smull %0.2d,%1.2s,%2.s[0]" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_smull_nv2si (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_n_u16 (uint16x4_t __a, uint16_t __b) { - uint32x4_t __result; - __asm__ ("umull %0.4s,%1.4h,%2.h[0]" - : "=w"(__result) - : "w"(__a), "x"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umull_nv4hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmull_n_u32 (uint32x2_t __a, uint32_t __b) { - uint64x2_t __result; - __asm__ ("umull %0.2d,%1.2s,%2.s[0]" - : "=w"(__result) - : "w"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_umull_nv2si_uuu (__a, __b); } __extension__ extern __inline poly16x8_t @@ -9409,24 +8681,14 @@ __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadal_s8 (int16x4_t __a, int8x8_t __b) { - int16x4_t __result; - __asm__ ("sadalp %0.4h,%2.8b" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sadalpv8qi (__a, __b); } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadal_s16 (int32x2_t __a, int16x4_t __b) { - int32x2_t __result; - __asm__ ("sadalp %0.2s,%2.4h" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sadalpv4hi (__a, __b); } __extension__ extern __inline int64x1_t @@ -9445,24 +8707,14 @@ __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadal_u8 (uint16x4_t __a, uint8x8_t __b) { - uint16x4_t __result; - __asm__ ("uadalp %0.4h,%2.8b" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uadalpv8qi_uuu (__a, __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadal_u16 (uint32x2_t __a, uint16x4_t __b) { - uint32x2_t __result; - __asm__ ("uadalp %0.2s,%2.4h" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uadalpv4hi_uuu (__a, __b); } __extension__ extern __inline uint64x1_t @@ -9481,72 +8733,42 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_s8 (int16x8_t __a, int8x16_t __b) { - int16x8_t __result; - __asm__ ("sadalp %0.8h,%2.16b" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sadalpv16qi (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_s16 (int32x4_t __a, int16x8_t __b) { - int32x4_t __result; - __asm__ ("sadalp %0.4s,%2.8h" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sadalpv8hi (__a, __b); } __extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_s32 (int64x2_t __a, int32x4_t __b) { - int64x2_t __result; - __asm__ ("sadalp %0.2d,%2.4s" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sadalpv4si (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_u8 (uint16x8_t __a, uint8x16_t __b) { - uint16x8_t __result; - __asm__ ("uadalp %0.8h,%2.16b" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uadalpv16qi_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_u16 (uint32x4_t __a, uint16x8_t __b) { - uint32x4_t __result; - __asm__ ("uadalp %0.4s,%2.8h" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uadalpv8hi_uuu (__a, __b); } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vpadalq_u32 (uint64x2_t __a, uint32x4_t __b) { - uint64x2_t __result; - __asm__ ("uadalp %0.2d,%2.4s" - : "=w"(__result) - : "0"(__a), "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uadalpv4si_uuu (__a, __b); } __extension__ extern __inline int16x4_t @@ -9841,108 +9063,63 @@ __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_s16 (int8x8_t __a, int16x8_t __b) { - int8x16_t __result = vcombine_s8 (__a, vcreate_s8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtn2 %0.16b, %1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtn2v8hi (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_s32 (int16x4_t __a, int32x4_t __b) { - int16x8_t __result = vcombine_s16 (__a, vcreate_s16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtn2 %0.8h, %1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtn2v4si (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_s64 (int32x2_t __a, int64x2_t __b) { - int32x4_t __result = vcombine_s32 (__a, vcreate_s32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtn2 %0.4s, %1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtn2v2di (__a, __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_u16 (uint8x8_t __a, uint16x8_t __b) { - uint8x16_t __result = vcombine_u8 (__a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("uqxtn2 %0.16b, %1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uqxtn2v8hi_uuu (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_u32 (uint16x4_t __a, uint32x4_t __b) { - uint16x8_t __result = vcombine_u16 (__a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("uqxtn2 %0.8h, %1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uqxtn2v4si_uuu (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovn_high_u64 (uint32x2_t __a, uint64x2_t __b) { - uint32x4_t __result = vcombine_u32 (__a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("uqxtn2 %0.4s, %1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_uqxtn2v2di_uuu (__a, __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s16 (uint8x8_t __a, int16x8_t __b) { - uint8x16_t __result = vcombine_u8 (__a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.16b, %1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v8hi_uus (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s32 (uint16x4_t __a, int32x4_t __b) { - uint16x8_t __result = vcombine_u16 (__a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.8h, %1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v4si_uus (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s64 (uint32x2_t __a, int64x2_t __b) { - uint32x4_t __result = vcombine_u32 (__a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.4s, %1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v2di_uus (__a, __b); } __extension__ extern __inline int16x4_t @@ -10119,353 +9296,151 @@ vqshrun_high_n_s64 (uint32x2_t __a, int64x2_t __b, const int __c) return __builtin_aarch64_sqshrun2_nv2di_uuss (__a, __b, __c); } -#define vrshrn_high_n_s16(a, b, c) \ - __extension__ \ - ({ \ - int16x8_t b_ = (b); \ - int8x8_t a_ = (a); \ - int8x16_t result = vcombine_s8 \ - (a_, vcreate_s8 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_s16 (int8x8_t __a, int16x8_t __b, const int __c) +{ + return __builtin_aarch64_rshrn2v8hi (__a, __b, __c); +} -#define vrshrn_high_n_s32(a, b, c) \ - __extension__ \ - ({ \ - int32x4_t b_ = (b); \ - int16x4_t a_ = (a); \ - int16x8_t result = vcombine_s16 \ - (a_, vcreate_s16 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_s32 (int16x4_t __a, int32x4_t __b, const int __c) +{ + return __builtin_aarch64_rshrn2v4si (__a, __b, __c); +} -#define vrshrn_high_n_s64(a, b, c) \ - __extension__ \ - ({ \ - int64x2_t b_ = (b); \ - int32x2_t a_ = (a); \ - int32x4_t result = vcombine_s32 \ - (a_, vcreate_s32 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_s64 (int32x2_t __a, int64x2_t __b, const int __c) +{ + return __builtin_aarch64_rshrn2v2di (__a, __b, __c); +} -#define vrshrn_high_n_u16(a, b, c) \ - __extension__ \ - ({ \ - uint16x8_t b_ = (b); \ - uint8x8_t a_ = (a); \ - uint8x16_t result = vcombine_u8 \ - (a_, vcreate_u8 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.16b,%1.8h,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint8x16_t) __builtin_aarch64_rshrn2v8hi ((int8x8_t) __a, + (int16x8_t) __b, __c); +} -#define vrshrn_high_n_u32(a, b, c) \ - __extension__ \ - ({ \ - uint32x4_t b_ = (b); \ - uint16x4_t a_ = (a); \ - uint16x8_t result = vcombine_u16 \ - (a_, vcreate_u16 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.8h,%1.4s,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint16x8_t) __builtin_aarch64_rshrn2v4si ((int16x4_t) __a, + (int32x4_t) __b, __c); +} -#define vrshrn_high_n_u64(a, b, c) \ - __extension__ \ - ({ \ - uint64x2_t b_ = (b); \ - uint32x2_t a_ = (a); \ - uint32x4_t result = vcombine_u32 \ - (a_, vcreate_u32 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("rshrn2 %0.4s,%1.2d,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint32x4_t) __builtin_aarch64_rshrn2v2di ((int32x2_t)__a, + (int64x2_t)__b, __c); +} -#define vrshrn_n_s16(a, b) \ - __extension__ \ - ({ \ - int16x8_t a_ = (a); \ - int8x8_t result; \ - __asm__ ("rshrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_s16 (int16x8_t __a, const int __b) +{ + return __builtin_aarch64_rshrnv8hi (__a, __b); +} -#define vrshrn_n_s32(a, b) \ - __extension__ \ - ({ \ - int32x4_t a_ = (a); \ - int16x4_t result; \ - __asm__ ("rshrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_s32 (int32x4_t __a, const int __b) +{ + return __builtin_aarch64_rshrnv4si (__a, __b); +} -#define vrshrn_n_s64(a, b) \ - __extension__ \ - ({ \ - int64x2_t a_ = (a); \ - int32x2_t result; \ - __asm__ ("rshrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_s64 (int64x2_t __a, const int __b) +{ + return __builtin_aarch64_rshrnv2di (__a, __b); +} -#define vrshrn_n_u16(a, b) \ - __extension__ \ - ({ \ - uint16x8_t a_ = (a); \ - uint8x8_t result; \ - __asm__ ("rshrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint8x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_u16 (uint16x8_t __a, const int __b) +{ + return (uint8x8_t) __builtin_aarch64_rshrnv8hi ((int16x8_t) __a, __b); +} -#define vrshrn_n_u32(a, b) \ - __extension__ \ - ({ \ - uint32x4_t a_ = (a); \ - uint16x4_t result; \ - __asm__ ("rshrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint16x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_u32 (uint32x4_t __a, const int __b) +{ + return (uint16x4_t) __builtin_aarch64_rshrnv4si ((int32x4_t) __a, __b); +} -#define vrshrn_n_u64(a, b) \ - __extension__ \ - ({ \ - uint64x2_t a_ = (a); \ - uint32x2_t result; \ - __asm__ ("rshrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vrshrn_n_u64 (uint64x2_t __a, const int __b) +{ + return (uint32x2_t) __builtin_aarch64_rshrnv2di ((int64x2_t) __a, __b); +} __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrsqrte_u32 (uint32x2_t __a) { - uint32x2_t __result; - __asm__ ("ursqrte %0.2s,%1.2s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_ursqrtev2si_uu (__a); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vrsqrteq_u32 (uint32x4_t __a) { - uint32x4_t __result; - __asm__ ("ursqrte %0.4s,%1.4s" - : "=w"(__result) - : "w"(__a) - : /* No clobbers */); - return __result; + return __builtin_aarch64_ursqrtev4si_uu (__a); } -#define vshrn_high_n_s16(a, b, c) \ - __extension__ \ - ({ \ - int16x8_t b_ = (b); \ - int8x8_t a_ = (a); \ - int8x16_t result = vcombine_s8 \ - (a_, vcreate_s8 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_high_n_s32(a, b, c) \ - __extension__ \ - ({ \ - int32x4_t b_ = (b); \ - int16x4_t a_ = (a); \ - int16x8_t result = vcombine_s16 \ - (a_, vcreate_s16 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_high_n_s64(a, b, c) \ - __extension__ \ - ({ \ - int64x2_t b_ = (b); \ - int32x2_t a_ = (a); \ - int32x4_t result = vcombine_s32 \ - (a_, vcreate_s32 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_high_n_u16(a, b, c) \ - __extension__ \ - ({ \ - uint16x8_t b_ = (b); \ - uint8x8_t a_ = (a); \ - uint8x16_t result = vcombine_u8 \ - (a_, vcreate_u8 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.16b,%1.8h,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_high_n_u32(a, b, c) \ - __extension__ \ - ({ \ - uint32x4_t b_ = (b); \ - uint16x4_t a_ = (a); \ - uint16x8_t result = vcombine_u16 \ - (a_, vcreate_u16 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.8h,%1.4s,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_high_n_u64(a, b, c) \ - __extension__ \ - ({ \ - uint64x2_t b_ = (b); \ - uint32x2_t a_ = (a); \ - uint32x4_t result = vcombine_u32 \ - (a_, vcreate_u32 \ - (__AARCH64_UINT64_C (0x0))); \ - __asm__ ("shrn2 %0.4s,%1.2d,#%2" \ - : "+w"(result) \ - : "w"(b_), "i"(c) \ - : /* No clobbers */); \ - result; \ - }) - -#define vshrn_n_s16(a, b) \ - __extension__ \ - ({ \ - int16x8_t a_ = (a); \ - int8x8_t result; \ - __asm__ ("shrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_s16 (int8x8_t __a, int16x8_t __b, const int __c) +{ + return __builtin_aarch64_shrn2v8hi (__a, __b, __c); +} -#define vshrn_n_s32(a, b) \ - __extension__ \ - ({ \ - int32x4_t a_ = (a); \ - int16x4_t result; \ - __asm__ ("shrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_s32 (int16x4_t __a, int32x4_t __b, const int __c) +{ + return __builtin_aarch64_shrn2v4si (__a, __b, __c); +} -#define vshrn_n_s64(a, b) \ - __extension__ \ - ({ \ - int64x2_t a_ = (a); \ - int32x2_t result; \ - __asm__ ("shrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_s64 (int32x2_t __a, int64x2_t __b, const int __c) +{ + return __builtin_aarch64_shrn2v2di (__a, __b, __c); +} -#define vshrn_n_u16(a, b) \ - __extension__ \ - ({ \ - uint16x8_t a_ = (a); \ - uint8x8_t result; \ - __asm__ ("shrn %0.8b,%1.8h,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c) +{ + return (uint8x16_t) + __builtin_aarch64_shrn2v8hi ((int8x8_t) __a, (int16x8_t) __b, __c); +} -#define vshrn_n_u32(a, b) \ - __extension__ \ - ({ \ - uint32x4_t a_ = (a); \ - uint16x4_t result; \ - __asm__ ("shrn %0.4h,%1.4s,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c) +{ + return (uint16x8_t) + __builtin_aarch64_shrn2v4si ((int16x4_t) __a, (int32x4_t) __b, __c); +} -#define vshrn_n_u64(a, b) \ - __extension__ \ - ({ \ - uint64x2_t a_ = (a); \ - uint32x2_t result; \ - __asm__ ("shrn %0.2s,%1.2d,%2" \ - : "=w"(result) \ - : "w"(a_), "i"(b) \ - : /* No clobbers */); \ - result; \ - }) +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c) +{ + return (uint32x4_t) + __builtin_aarch64_shrn2v2di ((int32x2_t) __a, (int64x2_t) __b, __c); +} #define vsli_n_p8(a, b, c) \ __extension__ \ @@ -10986,18 +9961,14 @@ __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_s32 (int32x2_t __a) { - int64_t __result; - __asm__ ("saddlp %0.1d, %1.2s" : "=w"(__result) : "w"(__a) : ); - return __result; + return __builtin_aarch64_saddlvv2si (__a); } __extension__ extern __inline uint64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vaddlv_u32 (uint32x2_t __a) { - uint64_t __result; - __asm__ ("uaddlp %0.1d, %1.2s" : "=w"(__result) : "w"(__a) : ); - return __result; + return __builtin_aarch64_uaddlvv2si_uu (__a); } __extension__ extern __inline int16x4_t diff --git a/gcc/config/aarch64/arm_sve.h b/gcc/config/aarch64/arm_sve.h index 5cad9a4..708114c 100644 --- a/gcc/config/aarch64/arm_sve.h +++ b/gcc/config/aarch64/arm_sve.h @@ -1,5 +1,5 @@ /* AArch64 SVE intrinsics include file. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index b27a80f..7bdb4ba 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 processor synchronization primitives. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. diff --git a/gcc/config/aarch64/biarchilp32.h b/gcc/config/aarch64/biarchilp32.h index 539c45a..8b4bc55 100644 --- a/gcc/config/aarch64/biarchilp32.h +++ b/gcc/config/aarch64/biarchilp32.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to ilp32 ABI. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/biarchlp64.h b/gcc/config/aarch64/biarchlp64.h index a15643e..daede57 100644 --- a/gcc/config/aarch64/biarchlp64.h +++ b/gcc/config/aarch64/biarchlp64.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to ilp64 ABI. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/check-sve-md.awk b/gcc/config/aarch64/check-sve-md.awk index 3275c5e..b482f04 100644 --- a/gcc/config/aarch64/check-sve-md.awk +++ b/gcc/config/aarch64/check-sve-md.awk @@ -1,5 +1,5 @@ #!/usr/bin/awk -f -# Copyright (C) 2019-2020 Free Software Foundation, Inc. +# Copyright (C) 2019-2021 Free Software Foundation, Inc. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 8cc6f50..09c2b72 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.c b/gcc/config/aarch64/cortex-a57-fma-steering.c index 58fa2f6..724dfd8 100644 --- a/gcc/config/aarch64/cortex-a57-fma-steering.c +++ b/gcc/config/aarch64/cortex-a57-fma-steering.c @@ -1,5 +1,5 @@ /* FMA steering optimization pass for Cortex-A57. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c index d68a725..e2935a1 100644 --- a/gcc/config/aarch64/driver-aarch64.c +++ b/gcc/config/aarch64/driver-aarch64.c @@ -1,5 +1,5 @@ /* Native CPU detection for aarch64. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/falkor-tag-collision-avoidance.c b/gcc/config/aarch64/falkor-tag-collision-avoidance.c index a96a332..de214e4 100644 --- a/gcc/config/aarch64/falkor-tag-collision-avoidance.c +++ b/gcc/config/aarch64/falkor-tag-collision-avoidance.c @@ -1,5 +1,5 @@ /* Tag Collision Avoidance pass for Falkor. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md index b501771..6118a52 100644 --- a/gcc/config/aarch64/falkor.md +++ b/gcc/config/aarch64/falkor.md @@ -1,5 +1,5 @@ ;; Falkor pipeline description -;; Copyright (C) 2017-2020 Free Software Foundation, Inc. +;; Copyright (C) 2017-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -302,7 +302,7 @@ (define_insn_reservation "falkor_alu_1_xyz" 1 (and (eq_attr "tune" "falkor") - (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) + (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) "falkor_xyz") ;; SIMD Miscellaneous Instructions diff --git a/gcc/config/aarch64/geniterators.sh b/gcc/config/aarch64/geniterators.sh index 43feb48..5fd8bec9 100644 --- a/gcc/config/aarch64/geniterators.sh +++ b/gcc/config/aarch64/geniterators.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# Copyright (C) 2014-2020 Free Software Foundation, Inc. +# Copyright (C) 2014-2021 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/gentune.sh b/gcc/config/aarch64/gentune.sh index e25d484..bde0813 100644 --- a/gcc/config/aarch64/gentune.sh +++ b/gcc/config/aarch64/gentune.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index fb1426b..fb6e228 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -215,6 +215,9 @@ ;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended). (define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI]) +;; Advanced SIMD modes for Integer widening reduction across lanes. +(define_mode_iterator VDQV_L [V8QI V16QI V4HI V8HI V4SI V2SI]) + ;; All double integer narrow-able modes. (define_mode_iterator VDN [V4HI V2SI DI]) @@ -422,6 +425,10 @@ VNx2DI VNx2DF VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF]) +;; SVE integer modes with 2 or 4 elements. +(define_mode_iterator SVE_24I [VNx2QI VNx2HI VNx2SI VNx2DI + VNx4QI VNx4HI VNx4SI]) + ;; SVE modes with 2 elements. (define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2BF VNx2SI VNx2SF VNx2DI VNx2DF]) @@ -488,6 +495,8 @@ UNSPEC_FMINV ; Used in aarch64-simd.md. UNSPEC_FADDV ; Used in aarch64-simd.md. UNSPEC_ADDV ; Used in aarch64-simd.md. + UNSPEC_SADDLV ; Used in aarch64-simd.md. + UNSPEC_UADDLV ; Used in aarch64-simd.md. UNSPEC_SMAXV ; Used in aarch64-simd.md. UNSPEC_SMINV ; Used in aarch64-simd.md. UNSPEC_UMAXV ; Used in aarch64-simd.md. @@ -513,6 +522,7 @@ UNSPEC_USQADD ; Used in aarch64-simd.md. UNSPEC_SUQADD ; Used in aarch64-simd.md. UNSPEC_SQXTUN ; Used in aarch64-simd.md. + UNSPEC_SQXTUN2 ; Used in aarch64-simd.md. UNSPEC_SQXTN ; Used in aarch64-simd.md. UNSPEC_UQXTN ; Used in aarch64-simd.md. UNSPEC_SSRA ; Used in aarch64-simd.md. @@ -708,6 +718,10 @@ UNSPEC_FCMLA90 ; Used in aarch64-simd.md. UNSPEC_FCMLA180 ; Used in aarch64-simd.md. UNSPEC_FCMLA270 ; Used in aarch64-simd.md. + UNSPEC_FCMUL ; Used in aarch64-simd.md. + UNSPEC_FCMUL_CONJ ; Used in aarch64-simd.md. + UNSPEC_FCMLA_CONJ ; Used in aarch64-simd.md. + UNSPEC_FCMLA180_CONJ ; Used in aarch64-simd.md. UNSPEC_ASRD ; Used in aarch64-sve.md. UNSPEC_ADCLB ; Used in aarch64-sve2.md. UNSPEC_ADCLT ; Used in aarch64-sve2.md. @@ -726,6 +740,10 @@ UNSPEC_CMLA180 ; Used in aarch64-sve2.md. UNSPEC_CMLA270 ; Used in aarch64-sve2.md. UNSPEC_CMLA90 ; Used in aarch64-sve2.md. + UNSPEC_CMLA_CONJ ; Used in aarch64-sve2.md. + UNSPEC_CMLA180_CONJ ; Used in aarch64-sve2.md. + UNSPEC_CMUL ; Used in aarch64-sve2.md. + UNSPEC_CMUL_CONJ ; Used in aarch64-sve2.md. UNSPEC_COND_FCVTLT ; Used in aarch64-sve2.md. UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md. UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md. @@ -1287,10 +1305,29 @@ ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") - (V2SI "2d") (V16QI "8h") + (V2SI "2d") (V16QI "8h") (V8HI "4s") (V4SI "2d") (V8HF "4s") (V4SF "2d")]) +;; Widened scalar register suffixes. +(define_mode_attr Vwstype [(V8QI "h") (V4HI "s") + (V2SI "") (V16QI "h") + (V8HI "s") (V4SI "d")]) +;; Add a .1d for V2SI. +(define_mode_attr Vwsuf [(V8QI "") (V4HI "") + (V2SI ".1d") (V16QI "") + (V8HI "") (V4SI "")]) + +;; Scalar mode of widened vector reduction. +(define_mode_attr VWIDE_S [(V8QI "HI") (V4HI "SI") + (V2SI "DI") (V16QI "HI") + (V8HI "SI") (V4SI "DI")]) + +;; Widened mode with half the element register suffixes for VD_BHSI/VQW/VQ_HSF. +(define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s") + (V2SI "1d") (V16QI "8h") + (V8HI "4s") (V4SI "2d")]) + ;; SVE vector after narrowing. (define_mode_attr Ventype [(VNx8HI "b") (VNx4SI "h") (VNx4SF "h") @@ -1304,7 +1341,7 @@ ;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") - (V2SI ".2d") (V16QI ".8h") + (V2SI ".2d") (V16QI ".8h") (V8HI ".4s") (V4SI ".2d") (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) @@ -1441,6 +1478,9 @@ (QI "qi") (HI "hi") (SI "si")]) +;; Like ve_mode but for the half-width modes. +(define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")]) + ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") (V2SI "w") (V4SI "w") (SI "w")]) @@ -1825,6 +1865,9 @@ ;; Unsigned comparison operators. (define_code_iterator FAC_COMPARISONS [lt le ge gt]) +;; Signed and unsigned saturating truncations. +(define_code_iterator SAT_TRUNC [ss_truncate us_truncate]) + ;; SVE integer unary operations. (define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount (ss_abs "TARGET_SVE2") @@ -1978,7 +2021,8 @@ (fix "s") (unsigned_fix "u") (div "s") (udiv "u") (smax "s") (umax "u") - (smin "s") (umin "u")]) + (smin "s") (umin "u") + (ss_truncate "s") (us_truncate "u")]) ;; "s" for signed ops, empty for unsigned ones. (define_code_attr s [(sign_extend "s") (zero_extend "")]) @@ -2146,6 +2190,12 @@ ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions. (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL]) +;; The unspec codes for the SABDL, UABDL AdvancedSIMD instructions. +(define_int_iterator ABDL [UNSPEC_SABDL UNSPEC_UABDL]) + +;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions. +(define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2]) + ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions. (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2]) @@ -2160,6 +2210,8 @@ (define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV]) +(define_int_iterator USADDLV [UNSPEC_SADDLV UNSPEC_UADDLV]) + (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD @@ -2598,6 +2650,24 @@ UNSPEC_SQRDCMLAH180 UNSPEC_SQRDCMLAH270]) +;; Unlike the normal CMLA instructions these represent the actual operation +;; to be performed. They will always need to be expanded into multiple +;; sequences consisting of CMLA. +(define_int_iterator SVE2_INT_CMLA_OP [UNSPEC_CMLA + UNSPEC_CMLA_CONJ + UNSPEC_CMLA180 + UNSPEC_CMLA180_CONJ]) + +;; Unlike the normal CMLA instructions these represent the actual operation +;; to be performed. They will always need to be expanded into multiple +;; sequences consisting of CMLA. +(define_int_iterator SVE2_INT_CMUL_OP [UNSPEC_CMUL + UNSPEC_CMUL_CONJ]) + +;; Same as SVE2_INT_CADD but exclude the saturating instructions +(define_int_iterator SVE2_INT_CADD_OP [UNSPEC_CADD90 + UNSPEC_CADD270]) + (define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT UNSPEC_CDOT90 UNSPEC_CDOT180 @@ -2708,6 +2778,14 @@ (define_int_iterator BF_MLA [UNSPEC_BFMLALB UNSPEC_BFMLALT]) +(define_int_iterator FCMLA_OP [UNSPEC_FCMLA + UNSPEC_FCMLA180 + UNSPEC_FCMLA_CONJ + UNSPEC_FCMLA180_CONJ]) + +(define_int_iterator FCMUL_OP [UNSPEC_FCMUL + UNSPEC_FCMUL_CONJ]) + ;; Iterators for atomic operations. (define_int_iterator ATOMIC_LDOP @@ -2884,6 +2962,8 @@ ;; "s" for signed operations and "u" for unsigned ones. (define_int_attr su [(UNSPEC_SADDV "s") (UNSPEC_UADDV "u") + (UNSPEC_SADDLV "s") + (UNSPEC_UADDLV "u") (UNSPEC_UNPACKSHI "s") (UNSPEC_UNPACKUHI "u") (UNSPEC_UNPACKSLO "s") @@ -2902,6 +2982,8 @@ (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") (UNSPEC_SABAL "s") (UNSPEC_UABAL "u") + (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u") + (UNSPEC_SABDL "s") (UNSPEC_UABDL "u") (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u") (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") @@ -3418,7 +3500,80 @@ (UNSPEC_COND_FCMLA "0") (UNSPEC_COND_FCMLA90 "90") (UNSPEC_COND_FCMLA180 "180") - (UNSPEC_COND_FCMLA270 "270")]) + (UNSPEC_COND_FCMLA270 "270") + (UNSPEC_FCMUL "0") + (UNSPEC_FCMUL_CONJ "180")]) + +;; A conjucate is a negation of the imaginary component +;; The number in the unspecs are the rotation component of the instruction, e.g +;; FCMLA180 means use the instruction with #180. +;; The iterator is used to produce the right name mangling for the function. +(define_int_attr conj_op [(UNSPEC_FCMLA180 "") + (UNSPEC_FCMLA180_CONJ "_conj") + (UNSPEC_FCMLA "") + (UNSPEC_FCMLA_CONJ "_conj") + (UNSPEC_FCMUL "") + (UNSPEC_FCMUL_CONJ "_conj") + (UNSPEC_CMLA "") + (UNSPEC_CMLA180 "") + (UNSPEC_CMLA180_CONJ "_conj") + (UNSPEC_CMLA_CONJ "_conj") + (UNSPEC_CMUL "") + (UNSPEC_CMUL_CONJ "_conj")]) + +;; The complex operations when performed on a real complex number require two +;; instructions to perform the operation. e.g. complex multiplication requires +;; two FCMUL with a particular rotation value. +;; +;; These values can be looked up in rotsplit1 and rotsplit2. as an example +;; FCMUL needs the first instruction to use #0 and the second #90. +(define_int_attr rotsplit1 [(UNSPEC_FCMLA "0") + (UNSPEC_FCMLA_CONJ "0") + (UNSPEC_FCMUL "0") + (UNSPEC_FCMUL_CONJ "0") + (UNSPEC_FCMLA180 "180") + (UNSPEC_FCMLA180_CONJ "180")]) + +(define_int_attr rotsplit2 [(UNSPEC_FCMLA "90") + (UNSPEC_FCMLA_CONJ "270") + (UNSPEC_FCMUL "90") + (UNSPEC_FCMUL_CONJ "270") + (UNSPEC_FCMLA180 "270") + (UNSPEC_FCMLA180_CONJ "90")]) + +;; SVE has slightly different namings from NEON so we have to split these +;; iterators. +(define_int_attr sve_rot1 [(UNSPEC_FCMLA "") + (UNSPEC_FCMLA_CONJ "") + (UNSPEC_FCMUL "") + (UNSPEC_FCMUL_CONJ "") + (UNSPEC_FCMLA180 "180") + (UNSPEC_FCMLA180_CONJ "180") + (UNSPEC_CMLA "") + (UNSPEC_CMLA_CONJ "") + (UNSPEC_CMUL "") + (UNSPEC_CMUL_CONJ "") + (UNSPEC_CMLA180 "180") + (UNSPEC_CMLA180_CONJ "180")]) + +(define_int_attr sve_rot2 [(UNSPEC_FCMLA "90") + (UNSPEC_FCMLA_CONJ "270") + (UNSPEC_FCMUL "90") + (UNSPEC_FCMUL_CONJ "270") + (UNSPEC_FCMLA180 "270") + (UNSPEC_FCMLA180_CONJ "90") + (UNSPEC_CMLA "90") + (UNSPEC_CMLA_CONJ "270") + (UNSPEC_CMUL "90") + (UNSPEC_CMUL_CONJ "270") + (UNSPEC_CMLA180 "270") + (UNSPEC_CMLA180_CONJ "90")]) + + +(define_int_attr fcmac1 [(UNSPEC_FCMLA "a") (UNSPEC_FCMLA_CONJ "a") + (UNSPEC_FCMLA180 "s") (UNSPEC_FCMLA180_CONJ "s") + (UNSPEC_CMLA "a") (UNSPEC_CMLA_CONJ "a") + (UNSPEC_CMLA180 "s") (UNSPEC_CMLA180_CONJ "s")]) (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla") (UNSPEC_COND_FMLS "fmls") diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 91b5148..75612fd 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -18,6 +18,8 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +(include "../arm/common.md") + (define_special_predicate "cc_register" (and (match_code "reg") (and (match_test "REGNO (op) == CC_REGNUM") diff --git a/gcc/config/aarch64/rtems.h b/gcc/config/aarch64/rtems.h index 6d96be2..84904b0 100644 --- a/gcc/config/aarch64/rtems.h +++ b/gcc/config/aarch64/rtems.h @@ -1,5 +1,5 @@ /* Definitions for RTEMS based AARCH64 system. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/saphira.md b/gcc/config/aarch64/saphira.md index 78a495b..e51dfec 100644 --- a/gcc/config/aarch64/saphira.md +++ b/gcc/config/aarch64/saphira.md @@ -1,5 +1,5 @@ ;; Saphira pipeline description -;; Copyright (C) 2017-2020 Free Software Foundation, Inc. +;; Copyright (C) 2017-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -224,7 +224,7 @@ (define_insn_reservation "saphira_alu_1_xyz" 1 (and (eq_attr "tune" "saphira") - (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) + (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) "saphira_xyzb") ;; SIMD Miscellaneous Instructions diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 11d20b7..7e1606c 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2009-2020 Free Software Foundation, Inc. +# Copyright (C) 2009-2021 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. @@ -158,6 +158,12 @@ aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.c \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/aarch64-bti-insert.c +aarch64-cc-fusion.o: $(srcdir)/config/aarch64/aarch64-cc-fusion.cc \ + $(CONFIG_H) $(SYSTEM_H) $(CORETYPES_H) $(BACKEND_H) $(RTL_H) $(DF_H) \ + $(RTL_SSA_H) tree-pass.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/aarch64/aarch64-cc-fusion.cc + comma=, MULTILIB_OPTIONS = $(subst $(comma),/, $(patsubst %, mabi=%, $(subst $(comma),$(comma)mabi=,$(TM_MULTILIB_CONFIG)))) MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) diff --git a/gcc/config/aarch64/t-aarch64-freebsd b/gcc/config/aarch64/t-aarch64-freebsd index 82758d4..2f1c0a7 100644 --- a/gcc/config/aarch64/t-aarch64-freebsd +++ b/gcc/config/aarch64/t-aarch64-freebsd @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux index 83e59e3..241b0ef 100644 --- a/gcc/config/aarch64/t-aarch64-linux +++ b/gcc/config/aarch64/t-aarch64-linux @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2009-2020 Free Software Foundation, Inc. +# Copyright (C) 2009-2021 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/t-aarch64-netbsd b/gcc/config/aarch64/t-aarch64-netbsd index 82758d4..2f1c0a7 100644 --- a/gcc/config/aarch64/t-aarch64-netbsd +++ b/gcc/config/aarch64/t-aarch64-netbsd @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/aarch64/t-aarch64-vxworks b/gcc/config/aarch64/t-aarch64-vxworks index b8d7629..deebcfb 100644 --- a/gcc/config/aarch64/t-aarch64-vxworks +++ b/gcc/config/aarch64/t-aarch64-vxworks @@ -1,6 +1,6 @@ # Multilibs for VxWorks. # -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index 52cd171..9194a3e 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -1,5 +1,5 @@ ;; Cavium ThunderX pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; Written by Andrew Pinski <apinski@cavium.com> @@ -51,7 +51,7 @@ (define_insn_reservation "thunderx_arith_shift" 2 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "alu_ext,alu_shift_imm,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm")) + (eq_attr "type" "alu_ext,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm")) "thunderx_pipe0 | thunderx_pipe1") (define_insn_reservation "thunderx_csel" 2 diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 064e1ca..9f7f19a 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -1,5 +1,5 @@ ;; Cavium ThunderX 2 CN99xx pipeline description -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; Contributed by Cavium, Broadcom and Mentor Embedded. @@ -109,7 +109,7 @@ (define_insn_reservation "thunderx2t99_alu_shift" 2 (and (eq_attr "tune" "thunderx2t99") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx2t99_i012,thunderx2t99_i012") diff --git a/gcc/config/aarch64/thunderx3t110.md b/gcc/config/aarch64/thunderx3t110.md index f8d6204..4f83be2 100644 --- a/gcc/config/aarch64/thunderx3t110.md +++ b/gcc/config/aarch64/thunderx3t110.md @@ -1,5 +1,5 @@ ;; Cavium ThunderX 3 CN11xx pipeline description -;; Copyright (C) 2020 Free Software Foundation, Inc. +;; Copyright (C) 2020-2021 Free Software Foundation, Inc. ;; ;; Contributed by Marvell @@ -126,14 +126,14 @@ ; is it actually 1,1/2,{i0,i1} vs 2,1/4,{i0,i1,i2,i3} (define_insn_reservation "thunderx3t110_alu_shift" 2 (and (eq_attr "tune" "thunderx3t110") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx3t110_i0123") (define_insn_reservation "thunderx3t110_alu_shift1" 1 (and (eq_attr "tune" "thunderx3t110") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx3t110_i01") diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md index 53293f5..3f9cbe0 100644 --- a/gcc/config/aarch64/tsv110.md +++ b/gcc/config/aarch64/tsv110.md @@ -1,5 +1,5 @@ ;; tsv110 pipeline description -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -295,7 +295,7 @@ (define_insn_reservation "tsv110_alu_shift" 2 (and (eq_attr "tune" "tsv110") (eq_attr "type" "extend,\ - alu_shift_imm,alu_shift_reg,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,\ crc,logic_shift_imm,logic_shift_reg,\ mov_shift,mvn_shift,\ mov_shift_reg,mvn_shift_reg")) diff --git a/gcc/config/alpha/alpha-modes.def b/gcc/config/alpha/alpha-modes.def index 5ae3517..26c757f 100644 --- a/gcc/config/alpha/alpha-modes.def +++ b/gcc/config/alpha/alpha-modes.def @@ -1,5 +1,5 @@ /* Alpha extra machine modes. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/alpha-passes.def b/gcc/config/alpha/alpha-passes.def index ba0764a..d7b4941 100644 --- a/gcc/config/alpha/alpha-passes.def +++ b/gcc/config/alpha/alpha-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for DEC Alpha - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h index ba4cb3b..b2fa3d2 100644 --- a/gcc/config/alpha/alpha-protos.h +++ b/gcc/config/alpha/alpha-protos.h @@ -1,5 +1,5 @@ /* Prototypes for alpha.c functions used in the md file & elsewhere. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 49b5a24..335f1db 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the DEC Alpha. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index 8da9ebc..a2a2db8 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index cee4c71..98d09d4 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -1,5 +1,5 @@ ;; Machine description for DEC Alpha for GNU C compiler -;; Copyright (C) 1992-2020 Free Software Foundation, Inc. +;; Copyright (C) 1992-2021 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; ;; This file is part of GCC. diff --git a/gcc/config/alpha/alpha.opt b/gcc/config/alpha/alpha.opt index 43b35e2..6f799e6 100644 --- a/gcc/config/alpha/alpha.opt +++ b/gcc/config/alpha/alpha.opt @@ -1,6 +1,6 @@ ; Options for the DEC Alpha port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,11 +19,11 @@ ; <http://www.gnu.org/licenses/>. msoft-float -Target Report Mask(SOFT_FP) +Target Mask(SOFT_FP) Do not use hardware fp. mfp-regs -Target Report Mask(FPREGS) +Target Mask(FPREGS) Use fp registers. mgas @@ -35,70 +35,70 @@ Target RejectNegative Mask(IEEE_CONFORMANT) Request IEEE-conformant math library routines (OSF/1). mieee -Target Report RejectNegative Mask(IEEE) +Target RejectNegative Mask(IEEE) Emit IEEE-conformant code, without inexact exceptions. mieee-with-inexact -Target Report RejectNegative Mask(IEEE_WITH_INEXACT) +Target RejectNegative Mask(IEEE_WITH_INEXACT) mbuild-constants -Target Report Mask(BUILD_CONSTANTS) +Target Mask(BUILD_CONSTANTS) Do not emit complex integer constants to read-only memory. mfloat-vax -Target Report RejectNegative Mask(FLOAT_VAX) +Target RejectNegative Mask(FLOAT_VAX) Use VAX fp. mfloat-ieee -Target Report RejectNegative InverseMask(FLOAT_VAX) +Target RejectNegative InverseMask(FLOAT_VAX) Do not use VAX fp. mbwx -Target Report Mask(BWX) +Target Mask(BWX) Emit code for the byte/word ISA extension. mmax -Target Report Mask(MAX) +Target Mask(MAX) Emit code for the motion video ISA extension. mfix -Target Report Mask(FIX) +Target Mask(FIX) Emit code for the fp move and sqrt ISA extension. mcix -Target Report Mask(CIX) +Target Mask(CIX) Emit code for the counting ISA extension. mexplicit-relocs -Target Report Mask(EXPLICIT_RELOCS) +Target Mask(EXPLICIT_RELOCS) Emit code using explicit relocation directives. msmall-data -Target Report RejectNegative Mask(SMALL_DATA) +Target RejectNegative Mask(SMALL_DATA) Emit 16-bit relocations to the small data areas. mlarge-data -Target Report RejectNegative InverseMask(SMALL_DATA) +Target RejectNegative InverseMask(SMALL_DATA) Emit 32-bit relocations to the small data areas. msmall-text -Target Report RejectNegative Mask(SMALL_TEXT) +Target RejectNegative Mask(SMALL_TEXT) Emit direct branches to local functions. mlarge-text -Target Report RejectNegative InverseMask(SMALL_TEXT) +Target RejectNegative InverseMask(SMALL_TEXT) Emit indirect branches to local functions. mtls-kernel -Target Report Mask(TLS_KERNEL) +Target Mask(TLS_KERNEL) Emit rdval instead of rduniq for thread pointer. mlong-double-128 -Target Report RejectNegative Mask(LONG_DOUBLE_128) +Target RejectNegative Mask(LONG_DOUBLE_128) Use 128-bit long double. mlong-double-64 -Target Report RejectNegative InverseMask(LONG_DOUBLE_128) +Target RejectNegative InverseMask(LONG_DOUBLE_128) Use 64-bit long double. mcpu= diff --git a/gcc/config/alpha/constraints.md b/gcc/config/alpha/constraints.md index 1dac5e9..e75a148 100644 --- a/gcc/config/alpha/constraints.md +++ b/gcc/config/alpha/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for DEC Alpha. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/driver-alpha.c b/gcc/config/alpha/driver-alpha.c index 3b368b1..1051318 100644 --- a/gcc/config/alpha/driver-alpha.c +++ b/gcc/config/alpha/driver-alpha.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Arthur Loiret <aloiret@debian.org> This file is part of GCC. diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h index 395d5f0..b735f27 100644 --- a/gcc/config/alpha/elf.h +++ b/gcc/config/alpha/elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha w/ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Richard Henderson (rth@tamu.edu). This file is part of GCC. diff --git a/gcc/config/alpha/elf.opt b/gcc/config/alpha/elf.opt index 5471e21..7b8e5a6 100644 --- a/gcc/config/alpha/elf.opt +++ b/gcc/config/alpha/elf.opt @@ -1,6 +1,6 @@ ; Alpha ELF options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md index c6dfaa0..c22d0ba 100644 --- a/gcc/config/alpha/ev4.md +++ b/gcc/config/alpha/ev4.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV4. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md index 2f0f9e9..218685a 100644 --- a/gcc/config/alpha/ev5.md +++ b/gcc/config/alpha/ev5.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV5. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/ev6.md b/gcc/config/alpha/ev6.md index 22a4870..158df4c 100644 --- a/gcc/config/alpha/ev6.md +++ b/gcc/config/alpha/ev6.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV6. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/linux-elf.h b/gcc/config/alpha/linux-elf.h index e25fcac..c1dae8c 100644 --- a/gcc/config/alpha/linux-elf.h +++ b/gcc/config/alpha/linux-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler for Alpha Linux-based GNU systems using ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Richard Henderson. This file is part of GCC. diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h index 3777f18..bde7fb0 100644 --- a/gcc/config/alpha/linux.h +++ b/gcc/config/alpha/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Alpha Linux-based GNU systems. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Richard Henderson. This file is part of GCC. diff --git a/gcc/config/alpha/netbsd.h b/gcc/config/alpha/netbsd.h index b2862ce..8a3d54c 100644 --- a/gcc/config/alpha/netbsd.h +++ b/gcc/config/alpha/netbsd.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Alpha NetBSD systems. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/openbsd.h b/gcc/config/alpha/openbsd.h index ae893de..83e91fe 100644 --- a/gcc/config/alpha/openbsd.h +++ b/gcc/config/alpha/openbsd.h @@ -1,5 +1,5 @@ /* Configuration file for an alpha OpenBSD target. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md index 970b45e..8f49f2a 100644 --- a/gcc/config/alpha/predicates.md +++ b/gcc/config/alpha/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for DEC Alpha. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/sync.md b/gcc/config/alpha/sync.md index e49ab46..d1d9a92 100644 --- a/gcc/config/alpha/sync.md +++ b/gcc/config/alpha/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for Alpha synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/t-alpha b/gcc/config/alpha/t-alpha index b62cc60..54d6b4b 100644 --- a/gcc/config/alpha/t-alpha +++ b/gcc/config/alpha/t-alpha @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/alpha/t-vms b/gcc/config/alpha/t-vms index cea54c5..f8d4381 100644 --- a/gcc/config/alpha/t-vms +++ b/gcc/config/alpha/t-vms @@ -1,4 +1,4 @@ -# Copyright (C) 1996-2020 Free Software Foundation, Inc. +# Copyright (C) 1996-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h index ce47ebd..b8673b6 100644 --- a/gcc/config/alpha/vms.h +++ b/gcc/config/alpha/vms.h @@ -1,5 +1,5 @@ /* Output variables, constants and external declarations, for GNU compiler. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-arch.h b/gcc/config/arc/arc-arch.h index fda76a5..188b07a 100644 --- a/gcc/config/arc/arc-arch.h +++ b/gcc/config/arc/arc-arch.h @@ -1,6 +1,6 @@ /* Definitions of types that are used to store ARC architecture and device information. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) This file is part of GCC. diff --git a/gcc/config/arc/arc-arches.def b/gcc/config/arc/arc-arches.def index e0606b25..fc26676 100644 --- a/gcc/config/arc/arc-arches.def +++ b/gcc/config/arc/arc-arches.def @@ -1,5 +1,5 @@ /* ARC ARCH architectures. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-c.c b/gcc/config/arc/arc-c.c index 50fd654..c20256c 100644 --- a/gcc/config/arc/arc-c.c +++ b/gcc/config/arc/arc-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-c.def b/gcc/config/arc/arc-c.def index a43d3f2..5e00f27 100644 --- a/gcc/config/arc/arc-c.def +++ b/gcc/config/arc/arc-c.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-cpus.def b/gcc/config/arc/arc-cpus.def index 1064ff1..66ec834 100644 --- a/gcc/config/arc/arc-cpus.def +++ b/gcc/config/arc/arc-cpus.def @@ -1,5 +1,5 @@ /* ARC CPU architectures. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def index 85270a64..963473c 100644 --- a/gcc/config/arc/arc-modes.def +++ b/gcc/config/arc/arc-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributor: Joern Rennecke <joern.rennecke@embecosm.com> on behalf of Synopsys Inc. diff --git a/gcc/config/arc/arc-options.def b/gcc/config/arc/arc-options.def index 8823a26..4675e89 100644 --- a/gcc/config/arc/arc-options.def +++ b/gcc/config/arc/arc-options.def @@ -1,5 +1,5 @@ /* ARC options. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-opts.h b/gcc/config/arc/arc-opts.h index 9691e56..6fadccf 100644 --- a/gcc/config/arc/arc-opts.h +++ b/gcc/config/arc/arc-opts.h @@ -1,6 +1,6 @@ /* GCC option-handling definitions for the Synopsys DesignWare ARC architecture. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-passes.def b/gcc/config/arc/arc-passes.def index c8ff9bc..04b9833 100644 --- a/gcc/config/arc/arc-passes.def +++ b/gcc/config/arc/arc-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for ARC. - Copyright (C) 2019-2020 Free Software Foundation, Inc. */ + Copyright (C) 2019-2021 Free Software Foundation, Inc. */ /* This file is part of GCC. diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index c72d78e..1f56a0d 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -90,10 +90,7 @@ extern void split_subsi (rtx *); extern void arc_split_move (rtx *); extern const char *arc_short_long (rtx_insn *insn, const char *, const char *); extern rtx arc_regno_use_in (unsigned int, rtx); -extern bool arc_scheduling_not_expected (void); -extern bool arc_sets_cc_p (rtx_insn *insn); extern int arc_label_align (rtx_insn *label); -extern bool arc_need_delay (rtx_insn *insn); extern bool arc_text_label (rtx_insn *insn); extern bool arc_short_comparison_p (rtx, int); diff --git a/gcc/config/arc/arc-simd.h b/gcc/config/arc/arc-simd.h index 0da36a0..a94c046 100644 --- a/gcc/config/arc/arc-simd.h +++ b/gcc/config/arc/arc-simd.h @@ -1,5 +1,5 @@ /* Synopsys DesignWare ARC SIMD include file. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. Written by Saurabh Verma (saurabh.verma@celunite.com) on behalf os Synopsys Inc. diff --git a/gcc/config/arc/arc-tables.opt b/gcc/config/arc/arc-tables.opt index f647c28..abecea3 100644 --- a/gcc/config/arc/arc-tables.opt +++ b/gcc/config/arc/arc-tables.opt @@ -2,7 +2,7 @@ ; Generated by : ./gcc/config/arc/genoptions.awk ; Generated from : ./gcc/config/arc/arc-cpu.def ; -; Copyright (C) 2016-2020 Free Software Foundation, Inc. +; Copyright (C) 2016-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index eabc122..367e4c9 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Synopsys DesignWare ARC cpu. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Sources derived from work done by Sankhya Technologies (www.sankhya.com) on behalf of Synopsys Inc. @@ -901,7 +901,7 @@ arc_secondary_reload (bool in_p, /* It is a pseudo that ends in a stack location. This procedure only works with the old reload step. */ - if (reg_equiv_mem (REGNO (x)) && !lra_in_progress) + if (!lra_in_progress && reg_equiv_mem (REGNO (x))) { /* Get the equivalent address and check the range of the offset. */ @@ -7663,11 +7663,18 @@ arc_invalid_within_doloop (const rtx_insn *insn) static rtx_insn * arc_active_insn (rtx_insn *insn) { - rtx_insn *nxt = next_active_insn (insn); - - if (nxt && GET_CODE (PATTERN (nxt)) == ASM_INPUT) - nxt = next_active_insn (nxt); - return nxt; + while (insn) + { + insn = NEXT_INSN (insn); + if (insn == 0 + || (active_insn_p (insn) + && NONDEBUG_INSN_P (insn) + && !NOTE_P (insn) + && GET_CODE (PATTERN (insn)) != UNSPEC_VOLATILE + && GET_CODE (PATTERN (insn)) != PARALLEL)) + break; + } + return insn; } /* Search for a sequence made out of two stores and a given number of @@ -7686,11 +7693,10 @@ check_store_cacheline_hazard (void) if (!succ0) return; - if (!single_set (insn) || !single_set (succ0)) + if (!single_set (insn)) continue; - if ((get_attr_type (insn) != TYPE_STORE) - || (get_attr_type (succ0) != TYPE_STORE)) + if ((get_attr_type (insn) != TYPE_STORE)) continue; /* Found at least two consecutive stores. Goto the end of the @@ -7699,6 +7705,9 @@ check_store_cacheline_hazard (void) if (!single_set (insn1) || get_attr_type (insn1) != TYPE_STORE) break; + /* Save were we are. */ + succ0 = insn1; + /* Now, check the next two instructions for the following cases: 1. next instruction is a LD => insert 2 nops between store sequence and load. @@ -7730,9 +7739,13 @@ check_store_cacheline_hazard (void) } } - insn = insn1; if (found) - found = false; + { + insn = insn1; + found = false; + } + else + insn = succ0; } } @@ -7807,7 +7820,6 @@ static void workaround_arc_anomaly (void) { rtx_insn *insn, *succ0; - rtx_insn *succ1; /* For any architecture: call arc_hazard here. */ for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) @@ -7826,24 +7838,6 @@ workaround_arc_anomaly (void) nops between any sequence of stores and a load. */ if (arc_tune != ARC_TUNE_ARC7XX) check_store_cacheline_hazard (); - - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - succ0 = next_real_insn (insn); - if (arc_store_addr_hazard_internal_p (insn, succ0)) - { - emit_insn_after (gen_nopv (), insn); - emit_insn_after (gen_nopv (), insn); - continue; - } - - /* Avoid adding nops if the instruction between the ST and LD is - a call or jump. */ - succ1 = next_real_insn (succ0); - if (succ0 && !JUMP_P (succ0) && !CALL_P (succ0) - && arc_store_addr_hazard_internal_p (insn, succ1)) - emit_insn_after (gen_nopv (), insn); - } } /* A callback for the hw-doloop pass. Called when a loop we have discovered @@ -8589,6 +8583,7 @@ arc_reorg (void) if (!brcc_nolimm_operator (op, VOIDmode) && !long_immediate_operand (op1, VOIDmode) && (TARGET_ARC700 + || (TARGET_V2 && optimize_size) || next_active_insn (link_insn) != insn)) continue; @@ -9239,13 +9234,21 @@ prepare_move_operands (rtx *operands, machine_mode mode) } if (arc_is_uncached_mem_p (operands[1])) { + rtx tmp = operands[0]; + if (MEM_P (operands[0])) - operands[0] = force_reg (mode, operands[0]); + tmp = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET - (operands[0], + (tmp, gen_rtx_UNSPEC_VOLATILE (mode, gen_rtvec (1, operands[1]), VUNSPEC_ARC_LDDI))); + if (MEM_P (operands[0])) + { + operands[1] = tmp; + return false; + } return true; } } @@ -10299,59 +10302,6 @@ arc_attr_type (rtx_insn *insn) return get_attr_type (insn); } -/* Return true if insn sets the condition codes. */ - -bool -arc_sets_cc_p (rtx_insn *insn) -{ - if (NONJUMP_INSN_P (insn)) - if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) - insn = seq->insn (seq->len () - 1); - return arc_attr_type (insn) == TYPE_COMPARE; -} - -/* Return true if INSN is an instruction with a delay slot we may want - to fill. */ - -bool -arc_need_delay (rtx_insn *insn) -{ - rtx_insn *next; - - if (!flag_delayed_branch) - return false; - /* The return at the end of a function needs a delay slot. */ - if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE - && (!(next = next_active_insn (insn)) - || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE) - && arc_attr_type (next) == TYPE_RETURN)) - && (!TARGET_PAD_RETURN - || (prev_active_insn (insn) - && prev_active_insn (prev_active_insn (insn)) - && prev_active_insn (prev_active_insn (prev_active_insn (insn)))))) - return true; - if (NONJUMP_INSN_P (insn) - ? (GET_CODE (PATTERN (insn)) == USE - || GET_CODE (PATTERN (insn)) == CLOBBER - || GET_CODE (PATTERN (insn)) == SEQUENCE) - : JUMP_P (insn) - ? (GET_CODE (PATTERN (insn)) == ADDR_VEC - || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) - : !CALL_P (insn)) - return false; - return num_delay_slots (insn) != 0; -} - -/* Return true if the scheduling pass(es) has/have already run, - i.e. where possible, we should try to mitigate high latencies - by different instruction selection. */ - -bool -arc_scheduling_not_expected (void) -{ - return cfun->machine->arc_reorg_started; -} - /* Code has a minimum p2 alignment of 1, which we must restore after an ADDR_DIFF_VEC. */ diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index fd6e21a..bbb36250 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -588,7 +588,7 @@ extern enum reg_class arc_regno_reg_class[]; || ((REGNO) == ARG_POINTER_REGNUM) \ || ((REGNO) == FRAME_POINTER_REGNUM) \ || ((REGNO) == PCL_REG) \ - || ((unsigned) reg_renumber[REGNO] < 29) \ + || (reg_renumber && ((unsigned) reg_renumber[REGNO] < 29)) \ || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG)) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 266b7ce..7a52551 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1,5 +1,5 @@ ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler -;; Copyright (C) 1994-2020 Free Software Foundation, Inc. +;; Copyright (C) 1994-2021 Free Software Foundation, Inc. ;; Sources derived from work done by Sankhya Technologies (www.sankhya.com) on ;; behalf of Synopsys Inc. @@ -871,6 +871,8 @@ core_3, archs4x, archs4xd, archs4xd_slow" (define_code_iterator SEZ [sign_extend zero_extend]) (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) +; Optab prefix for sign/zero-extending operations +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) (define_insn "*<SEZ_prefix>xt<SQH_postfix>_cmp0_noout" [(set (match_operand 0 "cc_set_register" "") @@ -1339,7 +1341,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" if (TARGET_PLUS_QMACW && even_register_operand (operands[0], DImode) && even_register_operand (operands[1], DImode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 2: @@ -1419,7 +1421,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" if (TARGET_PLUS_QMACW && even_register_operand (operands[0], DFmode) && even_register_operand (operands[1], DFmode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 4: @@ -1448,7 +1450,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" DONE; } [(set_attr "type" "move,move,move,move,load,store") - (set_attr "predicable" "no,no,yes,yes,no,no") + (set_attr "predicable" "no,no,no,yes,no,no") ;; ??? The ld/st values could be 16 if it's [reg,bignum]. (set_attr "length" "4,16,8,16,16,16")]) @@ -2840,43 +2842,25 @@ core_3, archs4x, archs4xd, archs4xd_slow" (set_attr "type" "compare") (set_attr "length" "4,4,8")]) -; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end -; needlessly prioritizing the matching constraint. -; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional -; execution is used where possible. -(define_insn_and_split "adc" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0)) - (match_operand:SI 1 "nonmemory_operand" - "%c,0,c,0,cCal")) - (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] +(define_insn "adc" + [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r") + (plus:SI + (plus:SI + (ltu:SI (reg:CC_C CC_REG) (const_int 0)) + (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r")) + (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ - adc %0,%1,%2 - add.cs %0,%1,1 - adc %0,%1,%2 - adc %0,%1,%2 - adc %0,%1,%2" - ; if we have a bad schedule after sched2, split. - "reload_completed - && !optimize_size && (!TARGET_ARC600_FAMILY) - && arc_scheduling_not_expected () - && arc_sets_cc_p (prev_nonnote_insn (insn)) - /* If next comes a return or other insn that needs a delay slot, - expect the adc to get into the delay slot. */ - && next_nonnote_insn (insn) - && !arc_need_delay (next_nonnote_insn (insn)) - /* Restore operands before emitting. */ - && (extract_insn_cached (insn), 1)" - [(set (match_dup 0) (match_dup 3)) - (cond_exec - (ltu (reg:CC_C CC_REG) (const_int 0)) - (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))] - "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);" + adc\\t%0,%1,%2 + add.cs\\t%0,%1,1 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2" [(set_attr "cond" "use") (set_attr "type" "cc_arith") - (set_attr "length" "4,4,4,4,8")]) + (set_attr "length" "4,4,4,4,8,8")]) ; combiner-splitter cmp / scc -> cmp / adc (define_split @@ -3008,7 +2992,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" DONE; } emit_insn (gen_sub_f (l0, l1, l2)); - emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG))); + emit_insn (gen_sbc (h0, h1, h2)); DONE; ") @@ -3023,44 +3007,25 @@ core_3, archs4x, archs4xd, archs4xd_slow" (set_attr "type" "cc_arith") (set_attr "length" "4")]) -; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end -; needlessly prioritizing the matching constraint. -; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution -; is used where possible. -(define_insn_and_split "sbc" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") - (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand" - "c,0,c,0,cCal") - (ltu:SI (match_operand:CC_C 3 "cc_use_register") - (const_int 0))) - (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] +(define_insn "sbc" + [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r") + (minus:SI + (minus:SI + (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal") + (ltu:SI (reg:CC_C CC_REG) (const_int 0))) + (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ - sbc %0,%1,%2 - sub.cs %0,%1,1 - sbc %0,%1,%2 - sbc %0,%1,%2 - sbc %0,%1,%2" - ; if we have a bad schedule after sched2, split. - "reload_completed - && !optimize_size && (!TARGET_ARC600_FAMILY) - && arc_scheduling_not_expected () - && arc_sets_cc_p (prev_nonnote_insn (insn)) - /* If next comes a return or other insn that needs a delay slot, - expect the adc to get into the delay slot. */ - && next_nonnote_insn (insn) - && !arc_need_delay (next_nonnote_insn (insn)) - /* Restore operands before emitting. */ - && (extract_insn_cached (insn), 1)" - [(set (match_dup 0) (match_dup 4)) - (cond_exec - (ltu (reg:CC_C CC_REG) (const_int 0)) - (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))] - "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);" + sbc\\t%0,%1,%2 + sub.cs\\t%0,%1,1 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2" [(set_attr "cond" "use") (set_attr "type" "cc_arith") - (set_attr "length" "4,4,4,4,8")]) + (set_attr "length" "4,4,4,4,8,8")]) (define_insn "sub_f" [(set (reg:CC CC_REG) @@ -6211,12 +6176,14 @@ core_3, archs4x, archs4xd, archs4xd_slow" "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) - emit_insn (gen_macd (operands[0], operands[1], operands[2])); + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode) + && REGNO (operands[0]) != ACC_REG_FIRST) + emit_insn (gen_macd (operands[0], operands[1], operands[2])); else { emit_insn (gen_mac (operands[1], operands[2])); - emit_move_insn (operands[0], acc_reg); + if (REGNO (operands[0]) != ACC_REG_FIRST) + emit_move_insn (operands[0], acc_reg); } DONE; }" @@ -6227,8 +6194,8 @@ core_3, archs4x, archs4xd, archs4xd_slow" [(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r") (plus:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c")) - (sign_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,Cal"))) + (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) + (sign_extend:DI (match_operand:SI 2 "extend_operand" "r,rI,Cal"))) (reg:DI ARCV2_ACC))) (set (reg:DI ARCV2_ACC) (plus:DI @@ -6311,12 +6278,14 @@ core_3, archs4x, archs4xd, archs4xd_slow" "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) - emit_insn (gen_macdu (operands[0], operands[1], operands[2])); + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode) + && REGNO (operands[0]) != ACC_REG_FIRST) + emit_insn (gen_macdu (operands[0], operands[1], operands[2])); else { emit_insn (gen_macu (operands[1], operands[2])); - emit_move_insn (operands[0], acc_reg); + if (REGNO (operands[0]) != ACC_REG_FIRST) + emit_move_insn (operands[0], acc_reg); } DONE; }" @@ -6327,8 +6296,8 @@ core_3, archs4x, archs4xd, archs4xd_slow" [(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r") (plus:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c")) - (zero_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,i"))) + (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) + (zero_extend:DI (match_operand:SI 2 "extend_operand" "r,rI,i"))) (reg:DI ARCV2_ACC))) (set (reg:DI ARCV2_ACC) (plus:DI @@ -6385,66 +6354,65 @@ core_3, archs4x, archs4xd, archs4xd_slow" (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn "mpyd_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) - (sign_extend:DI (match_operand:SI 2 "register_operand" " c, c")))) +(define_insn "mpyd<su_optab>_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) + (SEZ:DI (match_operand:SI 2 "register_operand" "r")))) (set (reg:DI ARCV2_ACC) (mult:DI - (sign_extend:DI (match_dup 1)) - (sign_extend:DI (match_dup 2))))] + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2))))] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpyd_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) - (match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd<su_optab>%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd<su_optab>_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI + (SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) + (SEZ:DI (match_operand:SI 2 "register_operand" "r")))) (set (reg:DI ARCV2_ACC) - (mult:DI (sign_extend:DI (match_dup 1)) - (match_dup 2)))] + (mult:DI + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2))))] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) - -(define_insn "mpydu_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) - (zero_extend:DI (match_operand:SI 2 "register_operand" " c, c")))) + "mpyd<su_optab>%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "yes")]) + +(define_insn "mpyd<su_optab>_imm_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r,r, r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r,0, r")) + (match_operand 2 "immediate_operand" "L,I,Cal"))) (set (reg:DI ARCV2_ACC) - (mult:DI (zero_extend:DI (match_dup 1)) - (zero_extend:DI (match_dup 2))))] + (mult:DI (SEZ:DI (match_dup 1)) + (match_dup 2)))] "TARGET_PLUS_MACD" - "mpydu%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpydu_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) - (match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd<su_optab>%?\\t%0,%1,%2" + [(set_attr "length" "4,4,8") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd<su_optab>_imm_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r,r") + (mult:DI + (SEZ:DI (match_operand:SI 1 "even_register_operand" "0,0")) + (match_operand 2 "immediate_operand" "L,Cal"))) (set (reg:DI ARCV2_ACC) - (mult:DI (zero_extend:DI (match_dup 1)) + (mult:DI (SEZ:DI (match_dup 1)) (match_dup 2)))] "TARGET_PLUS_MACD" - "mpydu%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) + "mpyd<su_optab>%?\\t%0,%1,%2" + [(set_attr "length" "4,8") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "yes")]) (define_insn "*add_shift" [(set (match_operand:SI 0 "register_operand" "=q,r,r") diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index c6c64af..85688d5 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -1,6 +1,6 @@ ; Options for the Synopsys DesignWare ARC port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -22,39 +22,39 @@ HeaderInclude config/arc/arc-opts.h mbig-endian -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Compile code for big endian mode. mlittle-endian -Target Report RejectNegative InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Compile code for little endian mode. This is the default. mno-cond-exec -Target Report RejectNegative Mask(NO_COND_EXEC) +Target RejectNegative Mask(NO_COND_EXEC) Disable ARCompact specific pass to generate conditional execution instructions. mA6 -Target Report +Target Generate ARCompact 32-bit code for ARC600 processor. mARC600 -Target Report +Target Same as -mA6. mARC601 -Target Report +Target Generate ARCompact 32-bit code for ARC601 processor. mA7 -Target Report +Target Generate ARCompact 32-bit code for ARC700 processor. mARC700 -Target Report +Target Same as -mA7. mjli-always -Target Report Mask(JLI_ALWAYS) +Target Mask(JLI_ALWAYS) Force all calls to be made via a jli instruction. mmpy-option= @@ -128,15 +128,15 @@ EnumValue Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical mdiv-rem -Target Report Mask(DIVREM) +Target Mask(DIVREM) Enable DIV-REM instructions for ARCv2. mcode-density -Target Report Mask(CODE_DENSITY) +Target Mask(CODE_DENSITY) Enable code density instructions for ARCv2. mmixed-code -Target Report Mask(MIXED_CODE_SET) +Target Mask(MIXED_CODE_SET) Tweak register allocation to help 16-bit instruction generation. ; originally this was: ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions @@ -146,91 +146,91 @@ Tweak register allocation to help 16-bit instruction generation. ; We use an explict definition for the negative form because that is the ; actually interesting option, and we want that to have its own comment. mvolatile-cache -Target Report RejectNegative Mask(VOLATILE_CACHE_SET) +Target RejectNegative Mask(VOLATILE_CACHE_SET) Use ordinarily cached memory accesses for volatile references. mno-volatile-cache -Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) +Target RejectNegative InverseMask(VOLATILE_CACHE_SET) Enable cache bypass for volatile references. mbarrel-shifter -Target Report Mask(BARREL_SHIFTER) +Target Mask(BARREL_SHIFTER) Generate instructions supported by barrel shifter. mnorm -Target Report Mask(NORM_SET) +Target Mask(NORM_SET) Generate norm instruction. mswap -Target Report Mask(SWAP_SET) +Target Mask(SWAP_SET) Generate swap instruction. mmul64 -Target Report Mask(MUL64_SET) +Target Mask(MUL64_SET) Generate mul64 and mulu64 instructions. mno-mpy -Target Report Mask(NOMPY_SET) Warn(%qs is deprecated) +Target Mask(NOMPY_SET) Warn(%qs is deprecated) Do not generate mpy instructions for ARC700. mea -Target Report Mask(EA_SET) +Target Mask(EA_SET) Generate extended arithmetic instructions, only valid for ARC700. msoft-float -Target Report Mask(0) +Target Mask(0) Dummy flag. This is the default unless FPX switches are provided explicitly. mlong-calls -Target Report Mask(LONG_CALLS_SET) +Target Mask(LONG_CALLS_SET) Generate call insns as register indirect calls. mno-brcc -Target Report Mask(NO_BRCC_SET) +Target Mask(NO_BRCC_SET) Do no generate BRcc instructions in arc_reorg. msdata -Target Report InverseMask(NO_SDATA_SET) +Target InverseMask(NO_SDATA_SET) Generate sdata references. This is the default, unless you compile for PIC. mmillicode -Target Report Mask(MILLICODE_THUNK_SET) +Target Mask(MILLICODE_THUNK_SET) Generate millicode thunks. mspfp -Target Report Mask(SPFP_COMPACT_SET) +Target Mask(SPFP_COMPACT_SET) FPX: Generate Single Precision FPX (compact) instructions. mspfp-compact -Target Report Mask(SPFP_COMPACT_SET) MaskExists +Target Mask(SPFP_COMPACT_SET) MaskExists FPX: Generate Single Precision FPX (compact) instructions. mspfp-fast -Target Report Mask(SPFP_FAST_SET) +Target Mask(SPFP_FAST_SET) FPX: Generate Single Precision FPX (fast) instructions. margonaut -Target Report Mask(ARGONAUT_SET) +Target Mask(ARGONAUT_SET) FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. mdpfp -Target Report Mask(DPFP_COMPACT_SET) +Target Mask(DPFP_COMPACT_SET) FPX: Generate Double Precision FPX (compact) instructions. mdpfp-compact -Target Report Mask(DPFP_COMPACT_SET) MaskExists +Target Mask(DPFP_COMPACT_SET) MaskExists FPX: Generate Double Precision FPX (compact) instructions. mdpfp-fast -Target Report Mask(DPFP_FAST_SET) +Target Mask(DPFP_FAST_SET) FPX: Generate Double Precision FPX (fast) instructions. mno-dpfp-lrsr -Target Report Mask(DPFP_DISABLE_LRSR) +Target Mask(DPFP_DISABLE_LRSR) Disable LR and SR instructions from using FPX extension aux registers. msimd -Target Report Mask(SIMD_SET) +Target Mask(SIMD_SET) Enable generation of ARC SIMD instructions via target-specific builtins. mcpu= @@ -242,7 +242,7 @@ Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) Size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. misize -Target Report PchIgnore Var(TARGET_DUMPISIZE) +Target PchIgnore Var(TARGET_DUMPISIZE) Annotate assembler instructions with estimated addresses. mmultcost= @@ -289,7 +289,7 @@ Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT) Enable the use of pre/post modify with register displacement. mmul32x16 -Target Report Mask(MULMAC_32BY16_SET) +Target Mask(MULMAC_32BY16_SET) Generate 32x16 multiply and mac instructions. ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , @@ -346,42 +346,42 @@ Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. ; Flags used by the assembler, but for which we define preprocessor ; macro symbols as well. mcrc -Target Report Warn(%qs is deprecated) +Target Warn(%qs is deprecated) Enable variable polynomial CRC extension. mdsp-packa -Target Report Warn(%qs is deprecated) +Target Warn(%qs is deprecated) Enable DSP 3.1 Pack A extensions. mdvbf -Target Report Warn(%qs is deprecated) +Target Warn(%qs is deprecated) Enable dual viterbi butterfly extension. mmac-d16 -Target Report Undocumented Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) mmac-24 -Target Report Undocumented Warn(%qs is deprecated) +Target Undocumented Warn(%qs is deprecated) mtelephony -Target Report RejectNegative Warn(%qs is deprecated) +Target RejectNegative Warn(%qs is deprecated) Enable Dual and Single Operand Instructions for Telephony. mxy -Target Report +Target Enable XY Memory extension (DSP version 3). ; ARC700 4.10 extension instructions mlock -Target Report +Target Enable Locked Load/Store Conditional extension. mswape -Target Report +Target Enable swap byte ordering extension instruction. mrtsc -Target Report Warn(%qs is deprecated) +Target Warn(%qs is deprecated) Enable 64-bit Time-Stamp Counter extension instruction. EB @@ -402,7 +402,7 @@ Pass -marclinux_prof option through to linker. ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. mlra -Target Report Var(arc_lra_flag) Init(1) Save +Target Var(arc_lra_flag) Init(1) Save Use LRA instead of reload. mlra-priority-none @@ -426,11 +426,11 @@ multcost= Target RejectNegative Joined matomic -Target Report Mask(ATOMIC) +Target Mask(ATOMIC) Enable atomic instructions. mll64 -Target Report Mask(LL64) +Target Mask(LL64) Enable double load/store instructions for ARC HS. mfpu= @@ -484,15 +484,15 @@ mtp-regno=none Target RejectNegative Var(arc_tp_regno,-1) mbitops -Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) +Target Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) Enable use of NPS400 bit operations. mcmem -Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) +Target Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) Enable use of NPS400 xld/xst extension. munaligned-access -Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) +Target Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) Enable unaligned word and halfword accesses to packed data. mirq-ctrl-saved= @@ -529,13 +529,13 @@ EnumValue Enum(arc_lpc) String(32) Value(32) mrf16 -Target Report Mask(RF16) +Target Mask(RF16) Enable 16-entry register file. mbranch-index -Target Report Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX) +Target Var(TARGET_BRANCH_INDEX) Init(DEFAULT_BRANCH_INDEX) Enable use of BI/BIH instructions when available. mcode-density-frame -Target Report Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT) +Target Var(TARGET_CODE_DENSITY_FRAME) Init(TARGET_CODE_DENSITY_FRAME_DEFAULT) Enable ENTER_S and LEAVE_S opcodes for ARCv2. diff --git a/gcc/config/arc/arc600.md b/gcc/config/arc/arc600.md index 8362356..61f45d5 100644 --- a/gcc/config/arc/arc600.md +++ b/gcc/config/arc/arc600.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC600 cpu ;; for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributor: Joern Rennecke <joern.rennecke@embecosm.com> ;; on behalf of Synopsys Inc. diff --git a/gcc/config/arc/arc700.md b/gcc/config/arc/arc700.md index 51b97e2..43b075e 100644 --- a/gcc/config/arc/arc700.md +++ b/gcc/config/arc/arc700.md @@ -5,7 +5,7 @@ ;; Ramana Radhakrishnan(ramana.radhakrishnan@codito.com) ;; Factoring out and improvement of ARC700 Scheduling by ;; Joern Rennecke (joern.rennecke@embecosm.com) -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arc/arcEM.md b/gcc/config/arc/arcEM.md index 714a1fb..b4c4db4 100644 --- a/gcc/config/arc/arcEM.md +++ b/gcc/config/arc/arcEM.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC EM cpu ;; for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com> ;; This file is part of GCC. diff --git a/gcc/config/arc/arcHS.md b/gcc/config/arc/arcHS.md index 102963e..f02edb4 100644 --- a/gcc/config/arc/arcHS.md +++ b/gcc/config/arc/arcHS.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu ;; for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com> ;; This file is part of GCC. diff --git a/gcc/config/arc/arcHS4x.md b/gcc/config/arc/arcHS4x.md index 7458564..eb1b3dd 100644 --- a/gcc/config/arc/arcHS4x.md +++ b/gcc/config/arc/arcHS4x.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC HS4x cpu ;; for GNU C compiler -;; Copyright (C) 2017-2020 Free Software Foundation, Inc. +;; Copyright (C) 2017-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arc/atomic.md b/gcc/config/arc/atomic.md index 721e6be..27ea4a7 100644 --- a/gcc/config/arc/atomic.md +++ b/gcc/config/arc/atomic.md @@ -1,5 +1,5 @@ ;; GCC machine description for ARC atomic instructions. -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arc/big.h b/gcc/config/arc/big.h index 568025a..f9b62d0 100644 --- a/gcc/config/arc/big.h +++ b/gcc/config/arc/big.h @@ -1,6 +1,6 @@ /* Definition of big endian ARC machine for GNU compiler. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/builtins.def b/gcc/config/arc/builtins.def index 5b69a98..9e4157b 100644 --- a/gcc/config/arc/builtins.def +++ b/gcc/config/arc/builtins.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index a2a8e84..7ed7933 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Synopsys DesignWare ARC. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arc/driver-arc.c b/gcc/config/arc/driver-arc.c index 08135f6..dc5fc39 100644 --- a/gcc/config/arc/driver-arc.c +++ b/gcc/config/arc/driver-arc.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu <claziss@synopsys.com> This file is part of GCC. diff --git a/gcc/config/arc/elf.h b/gcc/config/arc/elf.h index 1fd29cf..35b3707 100644 --- a/gcc/config/arc/elf.h +++ b/gcc/config/arc/elf.h @@ -1,6 +1,6 @@ /* Target macros for arc*-elf targets. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md index 1199e6e..9caa1e4 100644 --- a/gcc/config/arc/fpx.md +++ b/gcc/config/arc/fpx.md @@ -1,6 +1,6 @@ ;; Machine description of the Synopsys DesignWare ARC cpu Floating Point ;; extensions for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arc/genmultilib.awk b/gcc/config/arc/genmultilib.awk index 082a698..af08f55 100644 --- a/gcc/config/arc/genmultilib.awk +++ b/gcc/config/arc/genmultilib.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arc/genoptions.awk b/gcc/config/arc/genoptions.awk index 40a9817..32e99cf 100644 --- a/gcc/config/arc/genoptions.awk +++ b/gcc/config/arc/genoptions.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h index 0863f1c..170c0da 100644 --- a/gcc/config/arc/linux.h +++ b/gcc/config/arc/linux.h @@ -1,6 +1,6 @@ /* Target macros for arc*-*-linux targets. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index 2ad476d..f4dce41 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Synopsys DesignWare ARC. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index d2fc309..f090075 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1,5 +1,5 @@ ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -1413,7 +1413,7 @@ if (TARGET_PLUS_QMACW && even_register_operand (operands[0], <MODE>mode) && even_register_operand (operands[1], <MODE>mode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 2: @@ -1434,7 +1434,7 @@ DONE; } [(set_attr "type" "move,multi,load,store") - (set_attr "predicable" "yes,no,no,no") + (set_attr "predicable" "no,no,no,no") (set_attr "iscompact" "false,false,false,false") ]) diff --git a/gcc/config/arc/t-arc b/gcc/config/arc/t-arc index 6029403..e6395f6 100644 --- a/gcc/config/arc/t-arc +++ b/gcc/config/arc/t-arc @@ -1,6 +1,6 @@ # GCC Makefile fragment for Synopsys DesignWare ARC. # -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arc/t-multilib b/gcc/config/arc/t-multilib index 2569b70..42eba58 100644 --- a/gcc/config/arc/t-multilib +++ b/gcc/config/arc/t-multilib @@ -3,7 +3,7 @@ # Generated from : ./gcc/config/arc/arc-cpu.def # Used by : tmake_file from Makefile and genmultilib -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arc/t-multilib-linux b/gcc/config/arc/t-multilib-linux index 344297d..fc3fff6 100644 --- a/gcc/config/arc/t-multilib-linux +++ b/gcc/config/arc/t-multilib-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/README-interworking b/gcc/config/arm/README-interworking index bd354c4..6365500 100644 --- a/gcc/config/arm/README-interworking +++ b/gcc/config/arm/README-interworking @@ -742,7 +742,7 @@ used. interworking as the --support-old-code switch has taken care if this. -Copyright (C) 1998-2020 Free Software Foundation, Inc. +Copyright (C) 1998-2021 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 4f54ae9..251de3d 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -1,6 +1,6 @@ /* Functions and structures shared between arm and aarch64. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index e7b13f0..6ff4215 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -1,7 +1,7 @@ /* Dependency checks for instruction scheduling, shared between ARM and AARCH64. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 1b9d53d..d4baee4 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -1,6 +1,6 @@ /* RTX cost tables shared between arm and aarch64. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index afcef1d..9688fb6 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM with a.out - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@armltd.co.uk). This file is part of GCC. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 51e3180..fa0fb0b 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1,5 +1,5 @@ /* Description of builtins used by the ARM backend. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-builtins.h b/gcc/config/arm/arm-builtins.h index 62d6f17..bee9f9b 100644 --- a/gcc/config/arm/arm-builtins.h +++ b/gcc/config/arm/arm-builtins.h @@ -1,5 +1,5 @@ /* Declarations for determining resolver for a given builtin. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 899b890..7f97b84 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 8c61ad0..0becb43 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1,6 +1,6 @@ # CPU, FPU and architecture specifications for ARM. # -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -1477,6 +1477,17 @@ begin cpu cortex-a78ae part d42 end cpu cortex-a78ae +begin cpu cortex-a78c + cname cortexa78c + tune for cortex-a57 + tune flags LDSCHED + architecture armv8.2-a+fp16+dotprod + option crypto add FP_ARMv8 CRYPTO + costs cortex_a57 + vendor 41 + part d4b +end cpu cortex-a78c + begin cpu cortex-x1 cname cortexx1 tune for cortex-a57 diff --git a/gcc/config/arm/arm-d.c b/gcc/config/arm/arm-d.c index e6c751c..76ede3b 100644 --- a/gcc/config/arm/arm-d.c +++ b/gcc/config/arm/arm-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the ARM architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index c8ebf1b..fdf0933 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -482,7 +482,7 @@ "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") (set_attr "shift" "1") - (set_attr "type" "alu_shift_imm")]) + (set_attr "autodetect_type" "alu_shift_operator1")]) (define_insn "arm_usatsihi" [(set (match_operand:HI 0 "s_register_operand" "=r") diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h index f7eed55..1b4402d 100644 --- a/gcc/config/arm/arm-flags.h +++ b/gcc/config/arm/arm-flags.h @@ -1,6 +1,6 @@ /* Flags used to identify the presence of processor capabilities. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md index 4e0a6da..6e90507 100644 --- a/gcc/config/arm/arm-generic.md +++ b/gcc/config/arm/arm-generic.md @@ -1,5 +1,5 @@ ;; Generic ARM Pipeline Description -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml index 33ed2f2..c58e6b4 100644 --- a/gcc/config/arm/arm-ldmstm.ml +++ b/gcc/config/arm/arm-ldmstm.ml @@ -1,5 +1,5 @@ (* Auto-generate ARM ldm/stm patterns - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. @@ -335,7 +335,7 @@ let _ = "/* ARM ldm/stm instruction patterns. This file was automatically generated"; " using arm-ldmstm.ml. Please do not edit manually."; ""; -" Copyright (C) 2010-2020 Free Software Foundation, Inc."; +" Copyright (C) 2010-2021 Free Software Foundation, Inc."; " Contributed by CodeSourcery."; ""; " This file is part of GCC."; diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def index 6e48223..a5e74ba 100644 --- a/gcc/config/arm/arm-modes.def +++ b/gcc/config/arm/arm-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index deaa2a0..5c4b62f 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for ARM. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 1ba318a..bb5d3a2 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in arm.c and pe.c - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) diff --git a/gcc/config/arm/arm-simd-builtin-types.def b/gcc/config/arm/arm-simd-builtin-types.def index e35bb76..c19a1b6 100644 --- a/gcc/config/arm/arm-simd-builtin-types.def +++ b/gcc/config/arm/arm-simd-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin AdvSIMD types. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 05f5c08..5692d4f 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -2,7 +2,7 @@ ; Generated automatically by parsecpu.awk from arm-cpus.in. ; Do not edit. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; This file is part of GCC. @@ -247,6 +247,9 @@ EnumValue Enum(processor_type) String(cortex-a78ae) Value( TARGET_CPU_cortexa78ae) EnumValue +Enum(processor_type) String(cortex-a78c) Value( TARGET_CPU_cortexa78c) + +EnumValue Enum(processor_type) String(cortex-x1) Value( TARGET_CPU_cortexx1) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 32657da..b9df864 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -2,7 +2,7 @@ ; Generated automatically by parsecpu.awk from arm-cpus.in. ; Do not edit. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; This file is part of GCC. @@ -45,9 +45,9 @@ cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35, cortexa73cortexa53,cortexa55,cortexa75, cortexa76,cortexa76ae,cortexa77, - cortexa78,cortexa78ae,cortexx1, - neoversen1,cortexa75cortexa55,cortexa76cortexa55, - neoversev1,neoversen2,cortexm23, - cortexm33,cortexm35p,cortexm55, - cortexr52" + cortexa78,cortexa78ae,cortexa78c, + cortexx1,neoversen1,cortexa75cortexa55, + cortexa76cortexa55,neoversev1,neoversen2, + cortexm23,cortexm33,cortexm35p, + cortexm55,cortexr52" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 2f0ef3b..e22396d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1,5 +1,5 @@ /* Output routines for GCC for ARM. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -11211,11 +11211,23 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, return true; case EQ: - case NE: - case LT: - case LE: - case GT: case GE: + case GT: + case LE: + case LT: + /* Neon has special instructions when comparing with 0 (vceq, vcge, vcgt, + vcle and vclt). */ + if (TARGET_NEON + && TARGET_HARD_FLOAT + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) + && (XEXP (x, 1) == CONST0_RTX (mode))) + { + *cost = 0; + return true; + } + + /* Fall through. */ + case NE: case LTU: case LEU: case GEU: @@ -11889,7 +11901,8 @@ xscale_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep, instruction we depend on is another ALU instruction, then we may have to account for an additional stall. */ if (shift_opnum != 0 - && (attr_type == TYPE_ALU_SHIFT_IMM + && (attr_type == TYPE_ALU_SHIFT_IMM_LSL_1TO4 + || attr_type == TYPE_ALU_SHIFT_IMM_OTHER || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM @@ -29130,6 +29143,8 @@ arm_preferred_simd_mode (scalar_mode mode) if (TARGET_NEON) switch (mode) { + case E_HFmode: + return TARGET_NEON_VECTORIZE_DOUBLE ? V4HFmode : V8HFmode; case E_SFmode: return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode; case E_SImode: @@ -31479,6 +31494,15 @@ arm_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, return false; d.target = target; + if (op0) + { + rtx nop0 = force_reg (vmode, op0); + if (op0 == op1) + op1 = nop0; + op0 = nop0; + } + if (op1) + op1 = force_reg (vmode, op1); d.op0 = op0; d.op1 = op1; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 4a63d33..6bc03ad 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) @@ -1151,6 +1151,46 @@ extern const int arm_arch_cde_coproc_bits[]; #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT) #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT) +/* The conditions under which vector modes are supported by load/store + instructions using Neon. */ + +#define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST +#define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST +#define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD +#define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD +#define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON +#define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON +#define ARM_HAVE_NEON_DI_LDST TARGET_NEON +#define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON + +/* The conditions under which vector modes are supported by load/store + instructions by any vector extension. */ + +#define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) +#define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) + +#define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) +#define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) +#define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE) +#define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST +#define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST + +#define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST +#define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST + +#define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST +#define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST + +#define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT) +#define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT) + /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ extern int arm_regs_in_sequence[]; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1a8e498..3e441f9 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1,5 +1,5 @@ ;;- Machine description for ARM for GNU compiler -;; Copyright (C) 1991-2020 Free Software Foundation, Inc. +;; Copyright (C) 1991-2021 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -336,7 +336,8 @@ (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\ - alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\ + alu_shift_imm_lsl_1to4, alu_shift_imm_other, alu_shift_reg, alu_dsp_reg,\ + alus_ext, alus_imm, alus_sreg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ @@ -1370,7 +1371,7 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2")] ) (define_insn "*addsi3_carryin_clobercc" @@ -1679,7 +1680,7 @@ [(set_attr "conds" "use") (set_attr "arch" "*,a,t2") (set_attr "predicable" "yes") - (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")] + (set_attr "type" "adc_reg,adc_imm,alu_shift_imm_lsl_1to4")] ) ;; Special canonicalization of the above when operand1 == (const_int 1): @@ -1727,7 +1728,7 @@ "rsc%?\\t%0, %4, %1%S3" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator3")] ) (define_insn "cmpsi3_carryin_<CC_EXTEND>out" @@ -1811,7 +1812,7 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2")] ) (define_insn "*subsi3_carryin_shift_alt" @@ -1828,7 +1829,7 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2")] ) ;; No RSC in Thumb2 @@ -1844,7 +1845,7 @@ "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2")] ) (define_insn "*rsbsi3_carryin_shift_alt" @@ -1859,7 +1860,7 @@ "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2")] ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. @@ -4646,7 +4647,7 @@ (set_attr "predicable_short_it" "yes,yes,no,no") (set_attr "length" "4") (set_attr "shift" "1") - (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator3")] ) (define_insn "*shiftsi3_compare0" @@ -9503,7 +9504,7 @@ [(set_attr "predicable" "yes") (set_attr "shift" "2") (set_attr "arch" "a,t2") - (set_attr "type" "alu_shift_imm")]) + (set_attr "autodetect_type" "alu_shift_mul_op3")]) (define_insn "*<arith_shift_insn>_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") @@ -9517,7 +9518,7 @@ [(set_attr "predicable" "yes") (set_attr "shift" "3") (set_attr "arch" "a,t2,a") - (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")]) + (set_attr "autodetect_type" "alu_shift_operator2")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") @@ -10856,7 +10857,9 @@ (set_attr "length" "4,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift_imm" ) + (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")) (const_string "multiple")])] ) @@ -10921,7 +10924,9 @@ (set_attr "length" "4,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift_imm" ) + (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")) (const_string "multiple")])] ) diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index f01cd65..d332eb6 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -1,6 +1,6 @@ ; Options for the ARM port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -55,22 +55,22 @@ EnumValue Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) mabort-on-noreturn -Target Report Mask(ABORT_NORETURN) +Target Mask(ABORT_NORETURN) Generate a call to abort if a noreturn function returns. mapcs Target RejectNegative Mask(APCS_FRAME) Undocumented mapcs-frame -Target Report Mask(APCS_FRAME) +Target Mask(APCS_FRAME) Generate APCS conformant stack frames. mapcs-reentrant -Target Report Mask(APCS_REENT) +Target Mask(APCS_REENT) Generate re-entrant, PIC code. mapcs-stack-check -Target Report Mask(APCS_STACK) Undocumented +Target Mask(APCS_STACK) Undocumented march= Target Save RejectNegative Negative(march=) ToLower Joined Var(arm_arch_string) @@ -82,19 +82,19 @@ EnumValue Enum(arm_arch) String(native) Value(-1) DriverOnly marm -Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) +Target RejectNegative Negative(mthumb) InverseMask(THUMB) Generate code in 32 bit ARM state. mbig-endian -Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END) +Target RejectNegative Negative(mlittle-endian) Mask(BIG_END) Assume target CPU is configured as big endian. mcallee-super-interworking -Target Report Mask(CALLEE_INTERWORKING) +Target Mask(CALLEE_INTERWORKING) Thumb: Assume non-static functions may be called from ARM code. mcaller-super-interworking -Target Report Mask(CALLER_INTERWORKING) +Target Mask(CALLER_INTERWORKING) Thumb: Assume function pointers may go to non-Thumb aware code. mcpu= @@ -123,7 +123,7 @@ EnumValue Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) mflip-thumb -Target Report Var(TARGET_FLIP_THUMB) Undocumented +Target Var(TARGET_FLIP_THUMB) Undocumented Switch ARM/Thumb modes on alternating functions for compiler testing. mfp16-format= @@ -151,15 +151,15 @@ mhard-float Target RejectNegative Alias(mfloat-abi=, hard) Undocumented mlittle-endian -Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END) +Target RejectNegative Negative(mbig-endian) InverseMask(BIG_END) Assume target CPU is configured as little endian. mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Generate call insns as indirect calls, if necessary. mpic-data-is-text-relative -Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) +Target Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) Assume data segments are relative to text segment. mpic-register= @@ -167,15 +167,15 @@ Target RejectNegative Joined Var(arm_pic_register_string) Specify the register to be used for PIC addressing. mpoke-function-name -Target Report Mask(POKE_FUNCTION_NAME) +Target Mask(POKE_FUNCTION_NAME) Store function names in object code. msched-prolog -Target Report Mask(SCHED_PROLOG) +Target Mask(SCHED_PROLOG) Permit scheduling of a function's prologue sequence. msingle-pic-base -Target Report Mask(SINGLE_PIC_BASE) +Target Mask(SINGLE_PIC_BASE) Do not load the PIC register in function prologues. msoft-float @@ -186,11 +186,11 @@ Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFA Specify the minimum bit alignment of structures. (Deprecated). mthumb -Target Report RejectNegative Negative(marm) Mask(THUMB) Save +Target RejectNegative Negative(marm) Mask(THUMB) Save Generate code for Thumb state. mthumb-interwork -Target Report Mask(INTERWORK) +Target Mask(INTERWORK) Support calls between Thumb and ARM instruction sets. mtls-dialect= @@ -215,11 +215,11 @@ EnumValue Enum(arm_tp_type) String(cp15) Value(TP_CP15) mtpcs-frame -Target Report Mask(TPCS_FRAME) +Target Mask(TPCS_FRAME) Thumb: Generate (non-leaf) stack frames even if not needed. mtpcs-leaf-frame -Target Report Mask(TPCS_LEAF_FRAME) +Target Mask(TPCS_LEAF_FRAME) Thumb: Generate (leaf) stack frames even if not needed. mtune= @@ -227,7 +227,7 @@ Target Save RejectNegative Negative(mtune=) ToLower Joined Var(arm_tune_string) Tune code for the given processor. mprint-tune-info -Target Report RejectNegative Var(print_tune_info) Init(0) +Target RejectNegative Var(print_tune_info) Init(0) Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code. @@ -238,11 +238,11 @@ EnumValue Enum(processor_type) String(native) Value(-1) DriverOnly mvectorize-with-neon-quad -Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) +Target RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) Use Neon quad-word (rather than double-word) registers for vectorization. mvectorize-with-neon-double -Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) +Target RejectNegative Mask(NEON_VECTORIZE_DOUBLE) Use Neon double-word (rather than quad-word) registers for vectorization. mverbose-cost-dump @@ -250,20 +250,20 @@ Common Undocumented Var(arm_verbose_cost) Init(0) Enable more verbose RTX cost dumps during debug. For GCC developers use only. mword-relocations -Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) +Target Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) Only generate absolute relocations on word sized values. mrestrict-it -Target Report Var(arm_restrict_it) Init(2) Save +Target Var(arm_restrict_it) Init(2) Save Generate IT blocks appropriate for ARMv8. mfix-cortex-m3-ldrd -Target Report Var(fix_cm3_ldrd) Init(2) +Target Var(fix_cm3_ldrd) Init(2) Avoid overlapping destination and address registers on LDRD instructions that may trigger Cortex-M3 errata. munaligned-access -Target Report Var(unaligned_access) Init(2) Save +Target Var(unaligned_access) Init(2) Save Enable unaligned word and halfword accesses to packed data. mneon-for-64bits @@ -271,23 +271,23 @@ Target WarnRemoved This option is deprecated and has no effect. mslow-flash-data -Target Report Var(target_slow_flash_data) Init(0) +Target Var(target_slow_flash_data) Init(0) Assume loading data from flash is slower than fetching instructions. masm-syntax-unified -Target Report Var(inline_asm_unified) Init(0) Save +Target Var(inline_asm_unified) Init(0) Save Assume unified syntax for inline assembly code. mpure-code -Target Report Var(target_pure_code) Init(0) +Target Var(target_pure_code) Init(0) Do not allow constant data to be placed in code sections. mbe8 -Target Report RejectNegative Negative(mbe32) Mask(BE8) +Target RejectNegative Negative(mbe32) Mask(BE8) When linking for big-endian targets, generate a BE8 format image. mbe32 -Target Report RejectNegative Negative(mbe8) InverseMask(BE8) +Target RejectNegative Negative(mbe8) InverseMask(BE8) When linking for big-endian targets, generate a legacy BE32 format image. mbranch-cost= @@ -295,9 +295,9 @@ Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1) Cost to assume for a branch insn. mgeneral-regs-only -Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save +Target RejectNegative Mask(GENERAL_REGS_ONLY) Save Generate code which uses the core registers only (r0-r14). mfdpic -Target Report Mask(FDPIC) +Target Mask(FDPIC) Enable Function Descriptor PIC mode. diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index d1043f5..1a0a77b 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -1,5 +1,5 @@ ;; ARM 1020E & ARM 1022E Pipeline Description -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com) ;; ;; This file is part of GCC. @@ -78,7 +78,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "1020alu_shift_op" 1 (and (eq_attr "tune" "arm10e") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "1020a_e,1020a_m,1020a_w") diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index 5950629..f2f9c8e 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -1,5 +1,5 @@ ;; ARM 1026EJ-S Pipeline Description -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. @@ -78,7 +78,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "alu_shift_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "a_e,a_m,a_w") diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index ead4eef..c786e99 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -1,5 +1,5 @@ ;; ARM 1136J[F]-S Pipeline Description -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. @@ -87,7 +87,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "11_alu_shift_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "e_1,e_2,e_3,e_wb") diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index ba9c942..85e5bf1 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -1,5 +1,5 @@ ;; ARM 926EJ-S Pipeline Description -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. @@ -62,7 +62,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ shift_imm,shift_reg,extend,\ mov_imm,mov_reg,mov_shift,\ diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h index 6b08ffd..41b4fc6 100644 --- a/gcc/config/arm/arm_acle.h +++ b/gcc/config/arm/arm_acle.h @@ -1,6 +1,6 @@ /* ARM Non-NEON ACLE intrinsics include file. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_acle_builtins.def b/gcc/config/arm/arm_acle_builtins.def index 48b74ca..c7df12f 100644 --- a/gcc/config/arm/arm_acle_builtins.def +++ b/gcc/config/arm/arm_acle_builtins.def @@ -1,5 +1,5 @@ /* ACLE builtin definitions for ARM. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_bf16.h b/gcc/config/arm/arm_bf16.h index 1aa5931..5ee0f6e 100644 --- a/gcc/config/arm/arm_bf16.h +++ b/gcc/config/arm/arm_bf16.h @@ -1,6 +1,6 @@ /* Arm BF16 intrinsics include file. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm_cde.h b/gcc/config/arm/arm_cde.h index 0ba3ee0..5081b86 100644 --- a/gcc/config/arm/arm_cde.h +++ b/gcc/config/arm/arm_cde.h @@ -1,6 +1,6 @@ /* Arm Custom Datapath Extension (CDE) intrinsics include file. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. Contributed by Arm Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_cde_builtins.def b/gcc/config/arm/arm_cde_builtins.def index 9f8ddb5..8673c19 100644 --- a/gcc/config/arm/arm_cde_builtins.def +++ b/gcc/config/arm/arm_cde_builtins.def @@ -1,5 +1,5 @@ /* Arm Custom Datapath Extension (CDE) builtin definitions. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. Contributed by Arm Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h index 15816c3..363b179 100644 --- a/gcc/config/arm/arm_cmse.h +++ b/gcc/config/arm/arm_cmse.h @@ -1,6 +1,6 @@ /* ARMv8-M Secure Extensions intrinsics include file. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_fp16.h b/gcc/config/arm/arm_fp16.h index 10587aa..81a4bda 100644 --- a/gcc/config/arm/arm_fp16.h +++ b/gcc/config/arm/arm_fp16.h @@ -1,6 +1,6 @@ /* ARM FP16 intrinsics include file. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 6c0d1e2..3a40c6e 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1,6 +1,6 @@ /* Arm MVE intrinsics include file. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Arm. This file is part of GCC. @@ -3670,7 +3670,7 @@ __arm_vaddlvq_p_u32 (uint32x4_t __a, mve_pred16_t __p) return __builtin_mve_vaddlvq_p_uv4si (__a, __p); } -__extension__ extern __inline int32_t +__extension__ extern __inline mve_pred16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmpneq_s8 (int8x16_t __a, int8x16_t __b) { @@ -3981,14 +3981,16 @@ __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_u8 (uint8x16_t __a, uint8x16_t __b) { - return __builtin_mve_vcaddq_rot90_uv16qi (__a, __b); + return (uint8x16_t) + __builtin_mve_vcaddq_rot90v16qi ((int8x16_t)__a, (int8x16_t)__b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_u8 (uint8x16_t __a, uint8x16_t __b) { - return __builtin_mve_vcaddq_rot270_uv16qi (__a, __b); + return (uint8x16_t) + __builtin_mve_vcaddq_rot270v16qi ((int8x16_t)__a, (int8x16_t)__b); } __extension__ extern __inline uint8x16_t @@ -4520,14 +4522,14 @@ __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_s8 (int8x16_t __a, int8x16_t __b) { - return __builtin_mve_vcaddq_rot90_sv16qi (__a, __b); + return __builtin_mve_vcaddq_rot90v16qi (__a, __b); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_s8 (int8x16_t __a, int8x16_t __b) { - return __builtin_mve_vcaddq_rot270_sv16qi (__a, __b); + return __builtin_mve_vcaddq_rot270v16qi (__a, __b); } __extension__ extern __inline int8x16_t @@ -4821,14 +4823,16 @@ __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_u16 (uint16x8_t __a, uint16x8_t __b) { - return __builtin_mve_vcaddq_rot90_uv8hi (__a, __b); + return (uint16x8_t) + __builtin_mve_vcaddq_rot90v8hi ((int16x8_t)__a, (int16x8_t)__b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_u16 (uint16x8_t __a, uint16x8_t __b) { - return __builtin_mve_vcaddq_rot270_uv8hi (__a, __b); + return (uint16x8_t) + __builtin_mve_vcaddq_rot270v8hi ((int16x8_t)__a, (int16x8_t)__b); } __extension__ extern __inline uint16x8_t @@ -5360,14 +5364,14 @@ __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vcaddq_rot90_sv8hi (__a, __b); + return __builtin_mve_vcaddq_rot90v8hi (__a, __b); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_s16 (int16x8_t __a, int16x8_t __b) { - return __builtin_mve_vcaddq_rot270_sv8hi (__a, __b); + return __builtin_mve_vcaddq_rot270v8hi (__a, __b); } __extension__ extern __inline int16x8_t @@ -5661,14 +5665,16 @@ __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_u32 (uint32x4_t __a, uint32x4_t __b) { - return __builtin_mve_vcaddq_rot90_uv4si (__a, __b); + return (uint32x4_t) + __builtin_mve_vcaddq_rot90v4si ((int32x4_t)__a, (int32x4_t)__b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_u32 (uint32x4_t __a, uint32x4_t __b) { - return __builtin_mve_vcaddq_rot270_uv4si (__a, __b); + return (uint32x4_t) + __builtin_mve_vcaddq_rot270v4si ((int32x4_t)__a, (int32x4_t)__b); } __extension__ extern __inline uint32x4_t @@ -6200,14 +6206,14 @@ __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vcaddq_rot90_sv4si (__a, __b); + return __builtin_mve_vcaddq_rot90v4si (__a, __b); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_s32 (int32x4_t __a, int32x4_t __b) { - return __builtin_mve_vcaddq_rot270_sv4si (__a, __b); + return __builtin_mve_vcaddq_rot270v4si (__a, __b); } __extension__ extern __inline int32x4_t @@ -17342,42 +17348,42 @@ __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b); + return __builtin_mve_vcmulq_rot90v8hf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b); + return __builtin_mve_vcmulq_rot270v8hf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b); + return __builtin_mve_vcmulq_rot180v8hf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcmulq_fv8hf (__a, __b); + return __builtin_mve_vcmulqv8hf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b); + return __builtin_mve_vcaddq_rot90v8hf (__a, __b); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b) { - return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b); + return __builtin_mve_vcaddq_rot270v8hf (__a, __b); } __extension__ extern __inline float16x8_t @@ -17594,42 +17600,42 @@ __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b); + return __builtin_mve_vcmulq_rot90v4sf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b); + return __builtin_mve_vcmulq_rot270v4sf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b); + return __builtin_mve_vcmulq_rot180v4sf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcmulq_fv4sf (__a, __b); + return __builtin_mve_vcmulqv4sf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot90v4sf (__a, __b); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b) { - return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b); + return __builtin_mve_vcaddq_rot270v4sf (__a, __b); } __extension__ extern __inline float32x4_t @@ -17784,28 +17790,28 @@ __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) { - return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c); + return __builtin_mve_vcmlaqv8hf (__a, __b, __c); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) { - return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot180v8hf (__a, __b, __c); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) { - return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot270v8hf (__a, __b, __c); } __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c) { - return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot90v8hf (__a, __b, __c); } __extension__ extern __inline float16x8_t @@ -18092,28 +18098,28 @@ __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) { - return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c); + return __builtin_mve_vcmlaqv4sf (__a, __b, __c); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) { - return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot180v4sf (__a, __b, __c); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) { - return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot270v4sf (__a, __b, __c); } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c) { - return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c); + return __builtin_mve_vcmlaq_rot90v4sf (__a, __b, __c); } __extension__ extern __inline float32x4_t diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index f38926f..460f6ba 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -1,5 +1,5 @@ /* MVE builtin definitions for Arm. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Arm. This file is part of GCC. @@ -125,8 +125,6 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot90_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcaddq_rot270_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) @@ -202,8 +200,6 @@ VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vhaddq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, veorq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_s, v16qi, v8hi, v4si) -VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vbrsrq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vbicq_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vandq_s, v16qi, v8hi, v4si) @@ -264,12 +260,6 @@ VAR2 (BINOP_NONE_NONE_NONE, vmaxnmq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vmaxnmavq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vmaxnmaq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, veorq_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vbicq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vandq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vaddq_n_f, v8hf, v4sf) @@ -470,10 +460,6 @@ VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmsq_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmasq_n_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_n_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vfmaq_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180_f, v8hf, v4sf) -VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrntq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vshrnbq_n_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_IMM, vrshrntq_n_s, v8hi, v4si) @@ -892,3 +878,15 @@ VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_vec_s, v16qi, v8hi, v4si) VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_carry_s, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_vec_u, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_carry_u, v16qi, v8hi, v4si) + +/* optabs without any suffixes. */ +VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot90, v16qi, v8hi, v4si, v8hf, v4sf) +VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot270, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq, v8hf, v4sf) diff --git a/gcc/config/arm/arm_mve_types.h b/gcc/config/arm/arm_mve_types.h index 554e285..8958f4e 100644 --- a/gcc/config/arm/arm_mve_types.h +++ b/gcc/config/arm/arm_mve_types.h @@ -1,6 +1,6 @@ /* Arm MVE intrinsics include file. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. Contributed by Arm. This file is part of GCC. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 9569e1a..dc28b92 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -1,6 +1,6 @@ /* ARM NEON intrinsics include file. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. @@ -2471,392 +2471,392 @@ __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_s8 (int8x8_t __a, int8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgev8qi (__a, __b); + return (uint8x8_t) (__a >= __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_s16 (int16x4_t __a, int16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgev4hi (__a, __b); + return (uint16x4_t) (__a >= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_s32 (int32x2_t __a, int32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgev2si (__a, __b); + return (uint32x2_t) (__a >= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_f32 (float32x2_t __a, float32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgev2sf (__a, __b); + return (uint32x2_t) (__a >= __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __a, (int8x8_t) __b); + return (uint8x8_t) (__a >= __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __a, (int16x4_t) __b); + return (uint16x4_t) (__a >= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcge_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __a, (int32x2_t) __b); + return (uint32x2_t) (__a >= __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_s8 (int8x16_t __a, int8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgev16qi (__a, __b); + return (uint8x16_t) (__a >= __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_s16 (int16x8_t __a, int16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgev8hi (__a, __b); + return (uint16x8_t) (__a >= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_s32 (int32x4_t __a, int32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgev4si (__a, __b); + return (uint32x4_t) (__a >= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_f32 (float32x4_t __a, float32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgev4sf (__a, __b); + return (uint32x4_t) (__a >= __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __a, (int8x16_t) __b); + return (uint8x16_t) (__a >= __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __a, (int16x8_t) __b); + return (uint16x8_t) (__a >= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgeq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __a, (int32x4_t) __b); + return (uint32x4_t) (__a >= __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_s8 (int8x8_t __a, int8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgev8qi (__b, __a); + return (uint8x8_t) (__a <= __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_s16 (int16x4_t __a, int16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgev4hi (__b, __a); + return (uint16x4_t) (__a <= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_s32 (int32x2_t __a, int32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgev2si (__b, __a); + return (uint32x2_t) (__a <= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_f32 (float32x2_t __a, float32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgev2sf (__b, __a); + return (uint32x2_t) (__a <= __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgeuv8qi ((int8x8_t) __b, (int8x8_t) __a); + return (uint8x8_t) (__a <= __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgeuv4hi ((int16x4_t) __b, (int16x4_t) __a); + return (uint16x4_t) (__a <= __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcle_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgeuv2si ((int32x2_t) __b, (int32x2_t) __a); + return (uint32x2_t) (__a <= __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_s8 (int8x16_t __a, int8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgev16qi (__b, __a); + return (uint8x16_t) (__a <= __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_s16 (int16x8_t __a, int16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgev8hi (__b, __a); + return (uint16x8_t) (__a <= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_s32 (int32x4_t __a, int32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgev4si (__b, __a); + return (uint32x4_t) (__a <= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_f32 (float32x4_t __a, float32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgev4sf (__b, __a); + return (uint32x4_t) (__a <= __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgeuv16qi ((int8x16_t) __b, (int8x16_t) __a); + return (uint8x16_t) (__a <= __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgeuv8hi ((int16x8_t) __b, (int16x8_t) __a); + return (uint16x8_t) (__a <= __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcleq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgeuv4si ((int32x4_t) __b, (int32x4_t) __a); + return (uint32x4_t) (__a <= __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_s8 (int8x8_t __a, int8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgtv8qi (__a, __b); + return (uint8x8_t) (__a > __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_s16 (int16x4_t __a, int16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgtv4hi (__a, __b); + return (uint16x4_t) (__a > __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_s32 (int32x2_t __a, int32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtv2si (__a, __b); + return (uint32x2_t) (__a > __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_f32 (float32x2_t __a, float32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtv2sf (__a, __b); + return (uint32x2_t) (__a > __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __a, (int8x8_t) __b); + return (__a > __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __a, (int16x4_t) __b); + return (__a > __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgt_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __a, (int32x2_t) __b); + return (__a > __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_s8 (int8x16_t __a, int8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgtv16qi (__a, __b); + return (uint8x16_t) (__a > __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_s16 (int16x8_t __a, int16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgtv8hi (__a, __b); + return (uint16x8_t) (__a > __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_s32 (int32x4_t __a, int32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtv4si (__a, __b); + return (uint32x4_t) (__a > __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_f32 (float32x4_t __a, float32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtv4sf (__a, __b); + return (uint32x4_t) (__a > __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __a, (int8x16_t) __b); + return (__a > __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __a, (int16x8_t) __b); + return (__a > __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcgtq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __a, (int32x4_t) __b); + return (__a > __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_s8 (int8x8_t __a, int8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgtv8qi (__b, __a); + return (uint8x8_t) (__a < __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_s16 (int16x4_t __a, int16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgtv4hi (__b, __a); + return (uint16x4_t) (__a < __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_s32 (int32x2_t __a, int32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtv2si (__b, __a); + return (uint32x2_t) (__a < __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_f32 (float32x2_t __a, float32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtv2sf (__b, __a); + return (uint32x2_t) (__a < __b); } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_u8 (uint8x8_t __a, uint8x8_t __b) { - return (uint8x8_t)__builtin_neon_vcgtuv8qi ((int8x8_t) __b, (int8x8_t) __a); + return (__a < __b); } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_u16 (uint16x4_t __a, uint16x4_t __b) { - return (uint16x4_t)__builtin_neon_vcgtuv4hi ((int16x4_t) __b, (int16x4_t) __a); + return (__a < __b); } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vclt_u32 (uint32x2_t __a, uint32x2_t __b) { - return (uint32x2_t)__builtin_neon_vcgtuv2si ((int32x2_t) __b, (int32x2_t) __a); + return (__a < __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_s8 (int8x16_t __a, int8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgtv16qi (__b, __a); + return (uint8x16_t) (__a < __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_s16 (int16x8_t __a, int16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgtv8hi (__b, __a); + return (uint16x8_t) (__a < __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_s32 (int32x4_t __a, int32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtv4si (__b, __a); + return (uint32x4_t) (__a < __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_f32 (float32x4_t __a, float32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtv4sf (__b, __a); + return (uint32x4_t) (__a < __b); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_u8 (uint8x16_t __a, uint8x16_t __b) { - return (uint8x16_t)__builtin_neon_vcgtuv16qi ((int8x16_t) __b, (int8x16_t) __a); + return (__a < __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_u16 (uint16x8_t __a, uint16x8_t __b) { - return (uint16x8_t)__builtin_neon_vcgtuv8hi ((int16x8_t) __b, (int16x8_t) __a); + return (__a < __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcltq_u32 (uint32x4_t __a, uint32x4_t __b) { - return (uint32x4_t)__builtin_neon_vcgtuv4si ((int32x4_t) __b, (int32x4_t) __a); + return (__a < __b); } __extension__ extern __inline uint32x2_t @@ -5714,56 +5714,56 @@ __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vneg_s8 (int8x8_t __a) { - return (int8x8_t)__builtin_neon_vnegv8qi (__a); + return -__a; } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vneg_s16 (int16x4_t __a) { - return (int16x4_t)__builtin_neon_vnegv4hi (__a); + return -__a; } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vneg_s32 (int32x2_t __a) { - return (int32x2_t)__builtin_neon_vnegv2si (__a); + return -__a; } __extension__ extern __inline float32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vneg_f32 (float32x2_t __a) { - return (float32x2_t)__builtin_neon_vnegv2sf (__a); + return -__a; } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vnegq_s8 (int8x16_t __a) { - return (int8x16_t)__builtin_neon_vnegv16qi (__a); + return -__a; } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vnegq_s16 (int16x8_t __a) { - return (int16x8_t)__builtin_neon_vnegv8hi (__a); + return -__a; } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vnegq_s32 (int32x4_t __a) { - return (int32x4_t)__builtin_neon_vnegv4si (__a); + return -__a; } __extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vnegq_f32 (float32x4_t __a) { - return (float32x4_t)__builtin_neon_vnegv4sf (__a); + return -__a; } __extension__ extern __inline int8x8_t @@ -5812,98 +5812,98 @@ __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_s8 (int8x8_t __a) { - return (int8x8_t)__builtin_neon_vmvnv8qi (__a); + return ~__a; } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_s16 (int16x4_t __a) { - return (int16x4_t)__builtin_neon_vmvnv4hi (__a); + return ~__a; } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_s32 (int32x2_t __a) { - return (int32x2_t)__builtin_neon_vmvnv2si (__a); + return ~__a; } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_u8 (uint8x8_t __a) { - return (uint8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a); + return ~__a; } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_u16 (uint16x4_t __a) { - return (uint16x4_t)__builtin_neon_vmvnv4hi ((int16x4_t) __a); + return ~__a; } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_u32 (uint32x2_t __a) { - return (uint32x2_t)__builtin_neon_vmvnv2si ((int32x2_t) __a); + return ~__a; } __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvn_p8 (poly8x8_t __a) { - return (poly8x8_t)__builtin_neon_vmvnv8qi ((int8x8_t) __a); + return (poly8x8_t) ~((int8x8_t) __a); } __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_s8 (int8x16_t __a) { - return (int8x16_t)__builtin_neon_vmvnv16qi (__a); + return ~__a; } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_s16 (int16x8_t __a) { - return (int16x8_t)__builtin_neon_vmvnv8hi (__a); + return ~__a; } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_s32 (int32x4_t __a) { - return (int32x4_t)__builtin_neon_vmvnv4si (__a); + return ~__a; } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_u8 (uint8x16_t __a) { - return (uint8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a); + return ~__a; } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_u16 (uint16x8_t __a) { - return (uint16x8_t)__builtin_neon_vmvnv8hi ((int16x8_t) __a); + return ~__a; } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_u32 (uint32x4_t __a) { - return (uint32x4_t)__builtin_neon_vmvnv4si ((int32x4_t) __a); + return ~__a; } __extension__ extern __inline poly8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vmvnq_p8 (poly8x16_t __a) { - return (poly8x16_t)__builtin_neon_vmvnv16qi ((int8x16_t) __a); + return (poly8x16_t) ~((int8x16_t) __a); } __extension__ extern __inline int8x8_t @@ -6531,7 +6531,7 @@ __extension__ extern __inline poly64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_p64 (uint64_t __a) { - return (poly64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a); + return (poly64x1_t) __a; } #pragma GCC pop_options @@ -6539,28 +6539,28 @@ __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_s8 (uint64_t __a) { - return (int8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); + return (int8x8_t) __a; } __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_s16 (uint64_t __a) { - return (int16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); + return (int16x4_t) __a; } __extension__ extern __inline int32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_s32 (uint64_t __a) { - return (int32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a); + return (int32x2_t) __a; } __extension__ extern __inline int64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_s64 (uint64_t __a) { - return (int64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a); + return (int64x1_t) {__a}; } #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) @@ -6576,49 +6576,49 @@ __extension__ extern __inline float32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_f32 (uint64_t __a) { - return (float32x2_t)__builtin_neon_vcreatev2sf ((__builtin_neon_di) __a); + return (float32x2_t) __a; } __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_u8 (uint64_t __a) { - return (uint8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); + return (uint8x8_t) __a; } __extension__ extern __inline uint16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_u16 (uint64_t __a) { - return (uint16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); + return (uint16x4_t) __a; } __extension__ extern __inline uint32x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_u32 (uint64_t __a) { - return (uint32x2_t)__builtin_neon_vcreatev2si ((__builtin_neon_di) __a); + return (uint32x2_t) __a; } __extension__ extern __inline uint64x1_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_u64 (uint64_t __a) { - return (uint64x1_t)__builtin_neon_vcreatedi ((__builtin_neon_di) __a); + return (uint64x1_t) {__a}; } __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_p8 (uint64_t __a) { - return (poly8x8_t)__builtin_neon_vcreatev8qi ((__builtin_neon_di) __a); + return (poly8x8_t) __a; } __extension__ extern __inline poly16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vcreate_p16 (uint64_t __a) { - return (poly16x4_t)__builtin_neon_vcreatev4hi ((__builtin_neon_di) __a); + return (poly16x4_t) __a; } __extension__ extern __inline int8x8_t @@ -16912,6 +16912,37 @@ vceq_p64 (poly64x1_t __a, poly64x1_t __b) return vreinterpret_u64_u32 (__m); } +__extension__ extern __inline uint64x1_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqz_p64 (poly64x1_t __a) +{ + poly64x1_t __b = vreinterpret_p64_u32 (vdup_n_u32 (0)); + return vceq_p64 (__a, __b); +} + +/* For vceqq_p64, we rely on vceq_p64 for each of the two elements. */ +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqq_p64 (poly64x2_t __a, poly64x2_t __b) +{ + poly64_t __high_a = vget_high_p64 (__a); + poly64_t __high_b = vget_high_p64 (__b); + uint64x1_t __high = vceq_p64 (__high_a, __high_b); + + poly64_t __low_a = vget_low_p64 (__a); + poly64_t __low_b = vget_low_p64 (__b); + uint64x1_t __low = vceq_p64 (__low_a, __low_b); + return vcombine_u64 (__low, __high); +} + +__extension__ extern __inline uint64x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vceqzq_p64 (poly64x2_t __a) +{ + poly64x2_t __b = vreinterpretq_p64_u32 (vdupq_n_u32 (0)); + return vceqq_p64 (__a, __b); +} + /* The vtst_p64 intrinsic does not map to a single instruction. We emulate it in way similar to vceq_p64 above but here we do a reduction with max since if any two corresponding bits diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 0ff0494..97e4f9c 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -1,5 +1,5 @@ /* NEON builtin definitions for ARM. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -126,10 +126,6 @@ VAR6 (BINOP, vhsubu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) VAR3 (BINOP, vrsubhn, v8hi, v4si, v2di) VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) -VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) -VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) -VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) -VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR2 (BINOP, vcage, v2sf, v4sf) VAR2 (BINOP, vcagt, v2sf, v4sf) VAR2 (BINOP, vcage, v4hf, v8hf) @@ -195,7 +191,6 @@ VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) VAR2 (UNOP, vabs, v8hf, v4hf) VAR2 (UNOP, vneg, v8hf, v4hf) VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) -VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) @@ -205,7 +200,6 @@ VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) VAR2 (UNOP, vrecpe, v8hf, v4hf) VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) VAR2 (UNOP, vrsqrte, v4hf, v8hf) -VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR2 (UNOP, vrnd, v8hf, v4hf) VAR2 (UNOP, vrnda, v8hf, v4hf) VAR2 (UNOP, vrndm, v8hf, v4hf) @@ -218,7 +212,6 @@ VAR10 (GETLANE, vget_lane, VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si) VAR10 (SETLANE, vset_lane, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) -VAR5 (UNOP, vcreate, v8qi, v4hi, v2si, v2sf, di) VAR10 (UNOP, vdup_n, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) VAR4 (UNOP, vdup_n, v8hf, v4hf, v8bf, v4bf) diff --git a/gcc/config/arm/arm_vfp_builtins.def b/gcc/config/arm/arm_vfp_builtins.def index 89e7fbc..6e1190d 100644 --- a/gcc/config/arm/arm_vfp_builtins.def +++ b/gcc/config/arm/arm_vfp_builtins.def @@ -1,5 +1,5 @@ /* VFP instruction builtin definitions. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index eddb9b2..7843340 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -1,5 +1,5 @@ /* Configuration file for ARM BPABI targets. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/common.md b/gcc/config/arm/common.md new file mode 100644 index 0000000..bd2dd60 --- /dev/null +++ b/gcc/config/arm/common.md @@ -0,0 +1,41 @@ +;; Common predicate definitions for ARM, Thumb and AArch64 +;; Copyright (C) 2020-2021 Free Software Foundation, Inc. +;; Contributed by Fujitsu Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; Return true if constant is CONST_INT >= 1 and <= 4 +(define_predicate "const_1_to_4_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 4)"))) + +;; Return true if constant is 2 or 4 or 8 or 16 +(define_predicate "const_2_4_8_16_operand" + (and (match_code "const_int") + (match_test (" INTVAL (op) == 2 + || INTVAL (op) == 4 + || INTVAL (op) == 8 + || INTVAL (op) == 16 ")))) + +;; Return true if shift type is lsl and amount is in[1,4]. +(define_predicate "alu_shift_operator_lsl_1_to_4" + (and (match_code "ashift") + (match_test "const_1_to_4_operand (XEXP (op, 1), mode)"))) + +;; Return true if the operand is register. +(define_predicate "alu_shift_reg_p" + (match_test "register_operand (XEXP (op, 1), mode)")) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 789e333..919f299 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for ARM and Thumb -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. @@ -310,7 +310,7 @@ "@internal In ARM/Thumb-2 state a vector of constant zeros." (and (match_code "const_vector") - (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) + (match_test "(TARGET_NEON || TARGET_HAVE_MVE) && op == CONST0_RTX (mode)"))) (define_constraint "Da" "@internal diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index 6b1d73b..4ccb5df 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A15 NEON pipeline description -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 3cd1c43..ce5456b 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A15 pipeline description -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com> @@ -78,7 +78,7 @@ (define_insn_reservation "cortex_a15_alu_shift" 3 (and (eq_attr "tune" "cortexa15") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ diff --git a/gcc/config/arm/cortex-a17-neon.md b/gcc/config/arm/cortex-a17-neon.md index 385735e..41d2461 100644 --- a/gcc/config/arm/cortex-a17-neon.md +++ b/gcc/config/arm/cortex-a17-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A17 NEON pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-a17.md b/gcc/config/arm/cortex-a17.md index ad524c6..f551163 100644 --- a/gcc/config/arm/cortex-a17.md +++ b/gcc/config/arm/cortex-a17.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A17 pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; @@ -47,7 +47,7 @@ (define_insn_reservation "cortex_a17_alu_shiftimm" 2 (and (eq_attr "tune" "cortexa17") - (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm, alus_shift_imm, + (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm, logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\ shift_reg, mov_shift,mvn_shift")) "ca17_alu") diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index fd34696..8b7504e 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A5 pipeline description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. @@ -70,7 +70,7 @@ (define_insn_reservation "cortex_a5_alu_shift" 2 (and (eq_attr "tune" "cortexa5") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index afa3b78..59e84b3 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A53 pipeline description -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; @@ -91,7 +91,7 @@ (define_insn_reservation "cortex_a53_alu_shift" 3 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "alu_shift_imm,alus_shift_imm, + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm, crc,logic_shift_imm,logics_shift_imm, alu_ext,alus_ext,bfm,bfx,extend,mvn_shift")) "cortex_a53_slot_any") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 93d756b..cf2c995 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A57 pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -313,7 +313,7 @@ (define_insn_reservation "cortex_a57_alu_shift" 3 (and (eq_attr "tune" "cortexa57") (eq_attr "type" "bfm,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) "ca57_mx") diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index 1106cf8..0cd926f 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A7 pipeline description -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; Based on cortex-a5.md which was originally contributed by CodeSourcery. @@ -143,7 +143,7 @@ (define_insn_reservation "cortex_a7_alu_shift" 2 (and (eq_attr "tune" "cortexa7") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md index 9ec30d3..77c785d 100644 --- a/gcc/config/arm/cortex-a8-neon.md +++ b/gcc/config/arm/cortex-a8-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A8 NEON scheduling description. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 9032cb3..97b3cff 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A8 scheduling description. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. @@ -95,7 +95,7 @@ (define_insn_reservation "cortex_a8_alu_shift" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend")) "cortex_a8_default") diff --git a/gcc/config/arm/cortex-a9-neon.md b/gcc/config/arm/cortex-a9-neon.md index 1ac1154..2801dde 100644 --- a/gcc/config/arm/cortex-a9-neon.md +++ b/gcc/config/arm/cortex-a9-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A9 pipeline description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; ;; Neon pipeline description contributed by ARM Ltd. ;; diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 3a880d7..4762226 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A9 pipeline description -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Originally written by CodeSourcery for VFP. ;; ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> @@ -93,7 +93,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") ;; An instruction using the shifter will go down E1. (define_insn_reservation "cortex_a9_dp_shift" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md index 9ddece4..1093405 100644 --- a/gcc/config/arm/cortex-m4-fpu.md +++ b/gcc/config/arm/cortex-m4-fpu.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M4 FPU pipeline description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 20037ca..96be6ec 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M4 pipeline description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. @@ -36,7 +36,7 @@ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\ shift_imm,shift_reg,extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-m7.md b/gcc/config/arm/cortex-m7.md index b616a95..866bdee 100644 --- a/gcc/config/arm/cortex-m7.md +++ b/gcc/config/arm/cortex-m7.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M7 pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -54,7 +54,7 @@ ;; Simple alu with inline shift operation. (define_insn_reservation "cortex_m7_alu_shift" 2 (and (eq_attr "tune" "cortexm7") - (eq_attr "type" "alu_shift_imm,alus_shift_imm")) + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm")) "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_shf+cm7_branch") ;; Only one ALU can be used for DSP instructions. diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index e8fad30..af58791 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -1,5 +1,5 @@ ;; ARM Cortex-R4 scheduling description. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. @@ -92,7 +92,7 @@ (define_insn_reservation "cortex_r4_alu_shift" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "cortex_r4_alu") diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md index 38c757c6..cc231b1 100644 --- a/gcc/config/arm/cortex-r4f.md +++ b/gcc/config/arm/cortex-r4f.md @@ -1,5 +1,5 @@ ;; ARM Cortex-R4F VFP pipeline description -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/crypto.def b/gcc/config/arm/crypto.def index 5cc953b..019108e 100644 --- a/gcc/config/arm/crypto.def +++ b/gcc/config/arm/crypto.def @@ -1,5 +1,5 @@ /* Cryptographic instruction builtin definitions. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 59cb105..752deb4 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -1,5 +1,5 @@ ;; ARMv8-A crypto patterns. -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index 85058f2..21ae2d7 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index ba530e8..8bea438 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. For ARM with ELF obj format. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> and Catherine Moore <clm@cygnus.com> diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 48d0e9e..fd50649 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -1,5 +1,5 @@ ;; Samsung Exynos M1 pipeline description -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -386,7 +386,7 @@ (define_insn_reservation "exynos_m1_alu_shift" 2 (and (eq_attr "tune" "exynosm1") (eq_attr "type" "alu_ext, alus_ext,\ - alu_shift_imm, alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm,\ logic_shift_imm, logics_shift_imm,\ mov_shift, mvn_shift")) "(em1_alu)") diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index e854be1..5cedfff 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -1,5 +1,5 @@ ;; Faraday FA526 Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; This file is part of GCC. @@ -74,7 +74,7 @@ (define_insn_reservation "526_alu_shift_op" 2 (and (eq_attr "tune" "fa526") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index d5dc24f..df8e568 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -1,5 +1,5 @@ ;; Faraday FA606TE Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. @@ -67,7 +67,7 @@ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 8901965..76f06a9 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -1,5 +1,5 @@ ;; Faraday FA626TE Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. @@ -80,7 +80,7 @@ (define_insn_reservation "626te_alu_shift_op" 2 (and (eq_attr "tune" "fa626,fa626te") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 4d52246..bb88a2a 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -1,5 +1,5 @@ ;; Faraday FA726TE Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. @@ -100,7 +100,7 @@ ;; it takes 3 cycles. (define_insn_reservation "726te_alu_shift_op" 3 (and (eq_attr "tune" "fa726te") - (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "extend,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 8fee678..b17dd14 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -1,5 +1,5 @@ ;; Faraday FA626TE Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. @@ -73,7 +73,7 @@ (define_insn_reservation "mp626_alu_shift_op" 2 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\ extend,\ mov_shift,mov_shift_reg,\ diff --git a/gcc/config/arm/freebsd.h b/gcc/config/arm/freebsd.h index 7f9eff5..8a970be 100644 --- a/gcc/config/arm/freebsd.h +++ b/gcc/config/arm/freebsd.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, FreeBSD/arm version. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/arm/fuchsia-elf.h b/gcc/config/arm/fuchsia-elf.h index 665801a..85975af 100644 --- a/gcc/config/arm/fuchsia-elf.h +++ b/gcc/config/arm/fuchsia-elf.h @@ -1,5 +1,5 @@ /* Configuration file for ARM Fuchsia ELF targets. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. Contributed by Google. This file is part of GCC. diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 592af35..43aab23 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1,5 +1,5 @@ ;; Code and mode itertator and attribute definitions for the ARM backend -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -1177,11 +1177,59 @@ (define_int_attr rot [(UNSPEC_VCADD90 "90") (UNSPEC_VCADD270 "270") + (UNSPEC_VCMUL "0") + (UNSPEC_VCMUL90 "90") + (UNSPEC_VCMUL180 "180") + (UNSPEC_VCMUL270 "270") (UNSPEC_VCMLA "0") (UNSPEC_VCMLA90 "90") (UNSPEC_VCMLA180 "180") (UNSPEC_VCMLA270 "270")]) +;; The complex operations when performed on a real complex number require two +;; instructions to perform the operation. e.g. complex multiplication requires +;; two VCMUL with a particular rotation value. +;; +;; These values can be looked up in rotsplit1 and rotsplit2. as an example +;; VCMUL needs the first instruction to use #0 and the second #90. +(define_int_attr rotsplit1 [(UNSPEC_VCMLA "0") + (UNSPEC_VCMLA_CONJ "0") + (UNSPEC_VCMUL "0") + (UNSPEC_VCMUL_CONJ "0") + (UNSPEC_VCMLA180 "180") + (UNSPEC_VCMLA180_CONJ "180")]) + +(define_int_attr rotsplit2 [(UNSPEC_VCMLA "90") + (UNSPEC_VCMLA_CONJ "270") + (UNSPEC_VCMUL "90") + (UNSPEC_VCMUL_CONJ "270") + (UNSPEC_VCMLA180 "270") + (UNSPEC_VCMLA180_CONJ "90")]) + +(define_int_attr conj_op [(UNSPEC_VCMLA180 "") + (UNSPEC_VCMLA180_CONJ "_conj") + (UNSPEC_VCMLA "") + (UNSPEC_VCMLA_CONJ "_conj") + (UNSPEC_VCMUL "") + (UNSPEC_VCMUL_CONJ "_conj")]) + +(define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90") + (UNSPEC_VCADD270 "_rot270") + (UNSPEC_VCMLA "") + (UNSPEC_VCMLA90 "_rot90") + (UNSPEC_VCMLA180 "_rot180") + (UNSPEC_VCMLA270 "_rot270") + (UNSPEC_VCMUL "") + (UNSPEC_VCMUL90 "_rot90") + (UNSPEC_VCMUL180 "_rot180") + (UNSPEC_VCMUL270 "_rot270")]) + +(define_int_iterator VCMUL [UNSPEC_VCMUL UNSPEC_VCMUL90 + UNSPEC_VCMUL180 UNSPEC_VCMUL270]) + +(define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a") + (UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")]) + (define_int_attr simd32_op [(UNSPEC_QADD8 "qadd8") (UNSPEC_QSUB8 "qsub8") (UNSPEC_SHADD8 "shadd8") (UNSPEC_SHSUB8 "shsub8") (UNSPEC_UHADD8 "uhadd8") (UNSPEC_UHSUB8 "uhsub8") @@ -1216,7 +1264,7 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") - (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") + (VREV64Q_U "u") (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") @@ -1232,13 +1280,10 @@ (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s") (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s") (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u") - (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VANDQ_S "s") - (VANDQ_U "u") (VBICQ_S "s") (VBICQ_U "u") - (VBRSRQ_N_S "s") (VBRSRQ_N_U "u") (VCADDQ_ROT270_S "s") - (VCADDQ_ROT270_U "u") (VCADDQ_ROT90_S "s") - (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCADDQ_ROT90_U "u") + (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VBRSRQ_N_S "s") + (VBRSRQ_N_U "u") (VCMPEQQ_S "s") (VCMPEQQ_U "u") (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") - (VCMPNEQ_N_U "u") (VEORQ_S "s") (VEORQ_U "u") + (VCMPNEQ_N_U "u") (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") @@ -1248,8 +1293,8 @@ (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s") (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u") (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s") - (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s") - (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u") + (VMULQ_U "u") + (VQADDQ_N_S "s") (VQADDQ_N_U "u") (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s") (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u") (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s") @@ -1477,7 +1522,6 @@ (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) -(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) @@ -1501,15 +1545,10 @@ (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U]) (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U]) (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S]) -(define_int_iterator VANDQ [VANDQ_U VANDQ_S]) -(define_int_iterator VBICQ [VBICQ_S VBICQ_U]) (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S]) -(define_int_iterator VCADDQ_ROT270 [VCADDQ_ROT270_S VCADDQ_ROT270_U]) -(define_int_iterator VCADDQ_ROT90 [VCADDQ_ROT90_U VCADDQ_ROT90_S]) (define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) (define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) (define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) -(define_int_iterator VEORQ [VEORQ_U VEORQ_S]) (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) @@ -1524,8 +1563,6 @@ (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S]) (define_int_iterator VMULQ [VMULQ_U VMULQ_S]) (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S]) -(define_int_iterator VORNQ [VORNQ_U VORNQ_S]) -(define_int_iterator VORRQ [VORRQ_S VORRQ_U]) (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S]) (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U]) (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U]) @@ -1715,3 +1752,13 @@ (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48]) (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48]) (define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U]) + +;; Define iterators for VCMLA operations +(define_int_iterator VCMLA_OP [UNSPEC_VCMLA + UNSPEC_VCMLA_CONJ + UNSPEC_VCMLA180 + UNSPEC_VCMLA180_CONJ]) + +;; Define iterators for VCMLA operations as MUL +(define_int_iterator VCMUL_OP [UNSPEC_VCMUL + UNSPEC_VCMUL_CONJ]) diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index bb20474..7714dd7 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -1,5 +1,5 @@ ;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/arm/iwmmxt2.md b/gcc/config/arm/iwmmxt2.md index 298bbf3d..b6779ce 100644 --- a/gcc/config/arm/iwmmxt2.md +++ b/gcc/config/arm/iwmmxt2.md @@ -1,5 +1,5 @@ ;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Written by Marvell, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md index 994be09..860d30a 100644 --- a/gcc/config/arm/ldmstm.md +++ b/gcc/config/arm/ldmstm.md @@ -1,7 +1,7 @@ /* ARM ldm/stm instruction patterns. This file was automatically generated using arm-ldmstm.ml. Please do not edit manually. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/arm/ldrdstrd.md b/gcc/config/arm/ldrdstrd.md index 08e05a4..d6e2be5 100644 --- a/gcc/config/arm/ldrdstrd.md +++ b/gcc/config/arm/ldrdstrd.md @@ -1,6 +1,6 @@ ;; ARM ldrd/strd peephole optimizations. ;; -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; Written by Greta Yorsh <greta.yorsh@arm.com> diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h index 5bdcfa0..85d0136 100644 --- a/gcc/config/arm/linux-eabi.h +++ b/gcc/config/arm/linux-eabi.h @@ -1,5 +1,5 @@ /* Configuration file for ARM GNU/Linux EABI targets. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h index 0ec3aa5..0c1c4e7 100644 --- a/gcc/config/arm/linux-elf.h +++ b/gcc/config/arm/linux-elf.h @@ -1,5 +1,5 @@ /* Definitions for ARM running Linux-based GNU systems using ELF - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> This file is part of GCC. diff --git a/gcc/config/arm/linux-gas.h b/gcc/config/arm/linux-gas.h index c201a0c..76e68c0 100644 --- a/gcc/config/arm/linux-gas.h +++ b/gcc/config/arm/linux-gas.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. ARM Linux-based GNU systems version. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Russell King <rmk92@ecs.soton.ac.uk>. This file is part of GCC. diff --git a/gcc/config/arm/marvell-f-iwmmxt.md b/gcc/config/arm/marvell-f-iwmmxt.md index 27a01ae..b85904f 100644 --- a/gcc/config/arm/marvell-f-iwmmxt.md +++ b/gcc/config/arm/marvell-f-iwmmxt.md @@ -1,5 +1,5 @@ ;; Marvell WMMX2 pipeline description -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Written by Marvell, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index c415e0d..9aeefde 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -1,5 +1,5 @@ ;; Marvell ARM Processor Pipeline Description -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Marvell. ;; This file is part of GCC. @@ -73,7 +73,7 @@ (define_insn_reservation "pj4_shift" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -84,7 +84,7 @@ (define_insn_reservation "pj4_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -96,7 +96,7 @@ (define_insn_reservation "pj4_alu_shift" 1 (and (eq_attr "tune" "marvell_pj4") (not (eq_attr "conds" "set")) - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -107,7 +107,7 @@ (define_insn_reservation "pj4_alu_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") (eq_attr "conds" "set") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\ extend,\ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) diff --git a/gcc/config/arm/mmintrin.h b/gcc/config/arm/mmintrin.h index e133f4f..83c8a19 100644 --- a/gcc/config/arm/mmintrin.h +++ b/gcc/config/arm/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index ecbaaa9..ec0ef7b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1,5 +1,5 @@ ;; Arm M-profile Vector Extension Machine Description -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -271,8 +271,7 @@ (define_insn "mve_vnegq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] - VNEGQ_F)) + (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vneg.f%#<V_sz_elem> %q0, %q1" @@ -422,8 +421,7 @@ (define_insn "mve_vnegq_s<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VNEGQ_S)) + (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" "vneg.s%#<V_sz_elem> %q0, %q1" @@ -433,16 +431,22 @@ ;; ;; [vmvnq_u, vmvnq_s]) ;; -(define_insn "mve_vmvnq_<supf><mode>" +(define_insn "mve_vmvnq_u<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VMVNQ)) + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmvn %q0, %q1" + "vmvn\t%q0, %q1" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vmvnq_s<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vdupq_n_u, vdupq_n_s]) @@ -759,6 +763,7 @@ ;; ;; [vshrq_n_s, vshrq_n_u]) ;; +;; Version that takes an immediate as operand 2. (define_insn "mve_vshrq_n_<supf><mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") @@ -771,6 +776,39 @@ [(set_attr "type" "mve_move") ]) +;; Versions that take constant vectors as operand 2 (with all elements +;; equal). +(define_insn "mve_vshrq_n_s<mode>_imm" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) + ] + "TARGET_HAVE_MVE" + { + return neon_output_shift_immediate ("vshr", 's', &operands[2], + <MODE>mode, + VALID_NEON_QREG_MODE (<MODE>mode), + true); + } + [(set_attr "type" "mve_move") +]) +(define_insn "mve_vshrq_n_u<mode>_imm" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) + ] + "TARGET_HAVE_MVE" + { + return neon_output_shift_immediate ("vshr", 'u', &operands[2], + <MODE>mode, + VALID_NEON_QREG_MODE (<MODE>mode), + true); + } + [(set_attr "type" "mve_move") +]) + ;; ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) ;; @@ -818,18 +856,7 @@ ;; ;; [vshlq_s, vshlq_u]) -;; -(define_insn "mve_vshlq_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VSHLQ)) - ] - "TARGET_HAVE_MVE" - "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") -]) +;; See vec-common.md ;; ;; [vabdq_s, vabdq_u]) @@ -894,33 +921,54 @@ ;; ;; [vandq_u, vandq_s]) ;; -(define_insn "mve_vandq_<supf><mode>" +;; signed and unsigned versions are the same: define the unsigned +;; insn, and use an expander for the signed one as we still reference +;; both names from arm_mve.h. +;; We use the same code as in neon.md (TODO: avoid this duplication). +(define_insn "mve_vandq_u<mode>" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VANDQ)) + (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") + (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") + (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL"))) ] "TARGET_HAVE_MVE" - "vand %q0, %q1, %q2" + "@ + vand\t%q0, %q1, %q2 + * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vandq_s<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "neon_inv_logic_op2"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vbicq_s, vbicq_u]) ;; -(define_insn "mve_vbicq_<supf><mode>" +(define_insn "mve_vbicq_u<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VBICQ)) + (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) + (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vbic %q0, %q1, %q2" + "vbic\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vbicq_s<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) + (match_operand:MVE_2 1 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) + ;; ;; [vbrsrq_n_u, vbrsrq_n_s]) ;; @@ -937,34 +985,28 @@ ]) ;; -;; [vcaddq_rot270_s, vcaddq_rot270_u]) +;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) ;; -(define_insn "mve_vcaddq_rot270_<supf><mode>" +(define_insn "mve_vcaddq<mve_rot><mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w")] - VCADDQ_ROT270)) + VCADD)) ] "TARGET_HAVE_MVE" - "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #270" + "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>" [(set_attr "type" "mve_move") ]) -;; -;; [vcaddq_rot90_u, vcaddq_rot90_s]) -;; -(define_insn "mve_vcaddq_rot90_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VCADDQ_ROT90)) - ] - "TARGET_HAVE_MVE" - "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #90" - [(set_attr "type" "mve_move") -]) +;; Auto vectorizer pattern for int vcadd +(define_expand "cadd<rot><mode>3" + [(set (match_operand:MVE_2 0 "register_operand") + (unspec:MVE_2 [(match_operand:MVE_2 1 "register_operand") + (match_operand:MVE_2 2 "register_operand")] + VCADD))] + "TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN" +) ;; ;; [vcmpcsq_n_u]) @@ -1194,17 +1236,24 @@ ;; ;; [veorq_u, veorq_s]) ;; -(define_insn "mve_veorq_<supf><mode>" +(define_insn "mve_veorq_u<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VEORQ)) + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "veor %q0, %q1, %q2" + "veor\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_veorq_s<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vhaddq_n_u, vhaddq_n_s]) @@ -1585,32 +1634,53 @@ ;; ;; [vornq_u, vornq_s]) ;; -(define_insn "mve_vornq_<supf><mode>" +(define_insn "mve_vornq_s<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VORNQ)) + (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) + (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vorn %q0, %q1, %q2" + "vorn\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vornq_u<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) + (match_operand:MVE_2 1 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) + ;; ;; [vorrq_s, vorrq_u]) ;; -(define_insn "mve_vorrq_<supf><mode>" +;; signed and unsigned versions are the same: define the unsigned +;; insn, and use an expander for the signed one as we still reference +;; both names from arm_mve.h. +;; We use the same code as in neon.md (TODO: avoid this duplication). +(define_insn "mve_vorrq_s<mode>" [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VORRQ)) + (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") + (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl"))) ] "TARGET_HAVE_MVE" - "vorr %q0, %q1, %q2" + "@ + vorr\t%q0, %q1, %q2 + * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vorrq_u<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "neon_logic_op2"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vqaddq_n_s, vqaddq_n_u]) @@ -2019,9 +2089,8 @@ (define_insn "mve_vandq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VANDQ_F)) + (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vand %q0, %q1, %q2" @@ -2034,9 +2103,8 @@ (define_insn "mve_vbicq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VBICQ_F)) + (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")) + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vbic %q0, %q1, %q2" @@ -2059,32 +2127,17 @@ ]) ;; -;; [vcaddq_rot270_f]) -;; -(define_insn "mve_vcaddq_rot270_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCADDQ_ROT270_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #270" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcaddq_rot90_f]) +;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) ;; -(define_insn "mve_vcaddq_rot90_f<mode>" +(define_insn "mve_vcaddq<mve_rot><mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] - VCADDQ_ROT90_F)) + VCADD)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #90" + "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" [(set_attr "type" "mve_move") ]) @@ -2269,62 +2322,17 @@ ]) ;; -;; [vcmulq_f]) +;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270]) ;; -(define_insn "mve_vcmulq_f<mode>" +(define_insn "mve_vcmulq<mve_rot><mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMULQ_F)) + VCMUL)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #0" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmulq_rot180_f]) -;; -(define_insn "mve_vcmulq_rot180_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMULQ_ROT180_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #180" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmulq_rot270_f]) -;; -(define_insn "mve_vcmulq_rot270_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMULQ_ROT270_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #270" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmulq_rot90_f]) -;; -(define_insn "mve_vcmulq_rot90_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMULQ_ROT90_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #90" + "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" [(set_attr "type" "mve_move") ]) @@ -2379,9 +2387,8 @@ (define_insn "mve_veorq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VEORQ_F)) + (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "veor %q0, %q1, %q2" @@ -2631,9 +2638,8 @@ (define_insn "mve_vornq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VORNQ_F)) + (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2 "s_register_operand" "w")) + (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vorn %q0, %q1, %q2" @@ -2646,9 +2652,8 @@ (define_insn "mve_vorrq_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VORRQ_F)) + (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vorr %q0, %q1, %q2" @@ -4098,66 +4103,21 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) ;; -;; [vcmlaq_f]) +;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270]) ;; -(define_insn "mve_vcmlaq_f<mode>" +(define_insn "mve_vcmlaq<mve_rot><mode>" [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w")] - VCMLAQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #0" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmlaq_rot180_f]) -;; -(define_insn "mve_vcmlaq_rot180_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w")] - VCMLAQ_ROT180_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #180" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmlaq_rot270_f]) -;; -(define_insn "mve_vcmlaq_rot270_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w")] - VCMLAQ_ROT270_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #270" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmlaq_rot90_f]) -;; -(define_insn "mve_vcmlaq_rot90_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w")] - VCMLAQ_ROT90_F)) + (set (match_operand:MVE_0 0 "s_register_operand" "=w,w") + (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0") + (unspec:MVE_0 + [(match_operand:MVE_0 2 "s_register_operand" "w,w") + (match_operand:MVE_0 3 "s_register_operand" "w,w")] + VCMLA))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #90" + "@ + vcmul.f%#<V_sz_elem> %q0, %q2, %q3, #<rot> + vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>" [(set_attr "type" "mve_move") ]) @@ -10896,3 +10856,26 @@ [(set_attr "type" "coproc") (set_attr "length" "8")] ) + +(define_insn "*movmisalign<mode>_mve_store" + [(set (match_operand:MVE_VLD_ST 0 "neon_permissive_struct_operand" "=Um") + (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")] + UNSPEC_MISALIGNED_ACCESS))] + "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) + && !BYTES_BIG_ENDIAN && unaligned_access" + "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0" + [(set_attr "type" "mve_store")] +) + + +(define_insn "*movmisalign<mode>_mve_load" + [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") + (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "neon_permissive_struct_operand" " Um")] + UNSPEC_MISALIGNED_ACCESS))] + "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) + && !BYTES_BIG_ENDIAN && unaligned_access" + "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1" + [(set_attr "type" "mve_load")] +) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 2d76769..fec2cc9 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1,5 +1,5 @@ ;; ARM NEON coprocessor Machine Description -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. @@ -280,31 +280,6 @@ neon_disambiguate_copy (operands, dest, src, 4); }) -(define_expand "movmisalign<mode>" - [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand") - (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")] - UNSPEC_MISALIGNED_ACCESS))] - "TARGET_NEON && !BYTES_BIG_ENDIAN && unaligned_access" -{ - rtx adjust_mem; - /* This pattern is not permitted to fail during expansion: if both arguments - are non-registers (e.g. memory := constant, which can be created by the - auto-vectorizer), force operand 1 into a register. */ - if (!s_register_operand (operands[0], <MODE>mode) - && !s_register_operand (operands[1], <MODE>mode)) - operands[1] = force_reg (<MODE>mode, operands[1]); - - if (s_register_operand (operands[0], <MODE>mode)) - adjust_mem = operands[1]; - else - adjust_mem = operands[0]; - - /* Legitimize address. */ - if (!neon_vector_mem_operand (adjust_mem, 2, true)) - XEXP (adjust_mem, 0) = force_reg (Pmode, XEXP (adjust_mem, 0)); - -}) - (define_insn "*movmisalign<mode>_neon_store" [(set (match_operand:VDX 0 "neon_permissive_struct_operand" "=Um") (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] @@ -690,7 +665,7 @@ (set_attr "predicable" "no")] ) -(define_insn "ior<mode>3" +(define_insn "ior<mode>3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") (match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))] @@ -712,7 +687,7 @@ ;; corresponds to the canonical form the middle-end expects to use for ;; immediate bitwise-ANDs. -(define_insn "and<mode>3" +(define_insn "and<mode>3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") (match_operand:VDQ 2 "neon_inv_logic_op2" "w,DL")))] @@ -747,7 +722,7 @@ [(set_attr "type" "neon_logic<q>")] ) -(define_insn "xor<mode>3" +(define_insn "xor<mode>3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w") (match_operand:VDQ 2 "s_register_operand" "w")))] @@ -756,7 +731,7 @@ [(set_attr "type" "neon_logic<q>")] ) -(define_insn "one_cmpl<mode>2" +(define_insn "one_cmpl<mode>2_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -775,7 +750,7 @@ (const_string "neon_abs<q>")))] ) -(define_insn "neg<mode>2" +(define_insn "neon_neg<mode>2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -786,7 +761,7 @@ (const_string "neon_neg<q>")))] ) -(define_insn "<absneg_str><mode>2" +(define_insn "neon_<absneg_str><mode>2" [(set (match_operand:VH 0 "s_register_operand" "=w") (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))] "TARGET_NEON_FP16INST" @@ -800,7 +775,7 @@ (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))] "TARGET_NEON_FP16INST" { - emit_insn (gen_<absneg_str><mode>2 (operands[0], operands[1])); + emit_insn (gen_neon_<absneg_str><mode>2 (operands[0], operands[1])); DONE; }) @@ -870,25 +845,6 @@ ; generic vectorizer code. It ends up creating a V2DI constructor with ; SImode elements. -(define_insn "vashl<mode>3" - [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w") - (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w") - (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")))] - "TARGET_NEON" - { - switch (which_alternative) - { - case 0: return "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"; - case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2], - <MODE>mode, - VALID_NEON_QREG_MODE (<MODE>mode), - true); - default: gcc_unreachable (); - } - } - [(set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")] -) - (define_insn "vashr<mode>3_imm" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") @@ -943,40 +899,6 @@ [(set_attr "type" "neon_shift_reg<q>")] ) -(define_expand "vashr<mode>3" - [(set (match_operand:VDQIW 0 "s_register_operand") - (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") - (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "TARGET_NEON" -{ - if (s_register_operand (operands[2], <MODE>mode)) - { - rtx neg = gen_reg_rtx (<MODE>mode); - emit_insn (gen_neg<mode>2 (neg, operands[2])); - emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg)); - } - else - emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "vlshr<mode>3" - [(set (match_operand:VDQIW 0 "s_register_operand") - (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") - (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] - "TARGET_NEON" -{ - if (s_register_operand (operands[2], <MODE>mode)) - { - rtx neg = gen_reg_rtx (<MODE>mode); - emit_insn (gen_neg<mode>2 (neg, operands[2])); - emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg)); - } - else - emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2])); - DONE; -}) - ;; 64-bit shifts ;; This pattern loads a 32-bit shift count into a 64-bit NEON register, @@ -2953,7 +2875,7 @@ (match_operand:VDQW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_neg<mode>2 (operands[0], operands[1])); + emit_insn (gen_neon_neg<mode>2 (operands[0], operands[1])); DONE; }) @@ -3030,6 +2952,25 @@ [(set_attr "type" "neon_fcmla")] ) +;; The complex mul operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cmul<conj_op><mode>3" + [(set (match_operand:VDF 0 "register_operand") + (unspec:VDF [(match_operand:VDF 1 "register_operand") + (match_operand:VDF 2 "register_operand")] + VCMUL_OP))] + "TARGET_COMPLEX && !BYTES_BIG_ENDIAN" +{ + rtx res1 = gen_reg_rtx (<MODE>mode); + rtx tmp = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + emit_insn (gen_neon_vcmla<rotsplit1><mode> (res1, tmp, + operands[2], operands[1])); + emit_insn (gen_neon_vcmla<rotsplit2><mode> (operands[0], res1, + operands[2], operands[1])); + DONE; +}) + ;; These instructions map to the __builtins for the Dot Product operations. (define_insn "neon_<sup>dot<vsi2qi>" @@ -3240,7 +3181,7 @@ (match_operand:VDQIW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[1])); + emit_insn (gen_one_cmpl<mode>2_neon (operands[0], operands[1])); DONE; }) diff --git a/gcc/config/arm/netbsd-eabi.h b/gcc/config/arm/netbsd-eabi.h index a441c47..c624a0b 100644 --- a/gcc/config/arm/netbsd-eabi.h +++ b/gcc/config/arm/netbsd-eabi.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/arm/netbsd-elf.h b/gcc/config/arm/netbsd-elf.h index 6851fb2..55cb93b 100644 --- a/gcc/config/arm/netbsd-elf.h +++ b/gcc/config/arm/netbsd-elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 9423e8a..6a7cc8b 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -1,5 +1,5 @@ # Manipulate the CPU, FPU and architecture descriptions for ARM. -# Copyright (C) 2017-2020 Free Software Foundation, Inc. +# Copyright (C) 2017-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -62,7 +62,7 @@ function boilerplate (style) { print cc "Generated automatically by parsecpu.awk from arm-cpus.in." print cc "Do not edit." print "" - print cc "Copyright (C) 2011-2020 Free Software Foundation, Inc." + print cc "Copyright (C) 2011-2021 Free Software Foundation, Inc." print "" print cc "This file is part of GCC." print "" diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 2144520..c661f01 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for ARM and Thumb -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. @@ -18,6 +18,8 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +(include "common.md") + (define_predicate "s_register_operand" (match_code "reg,subreg") { @@ -107,7 +109,7 @@ (define_predicate "imm_for_neon_inv_logic_operand" (match_code "const_vector") { - return (TARGET_NEON + return ((TARGET_NEON || TARGET_HAVE_MVE) && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); }) @@ -118,7 +120,7 @@ (define_predicate "imm_for_neon_logic_operand" (match_code "const_vector") { - return (TARGET_NEON + return ((TARGET_NEON || TARGET_HAVE_MVE) && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); }) diff --git a/gcc/config/arm/rtems.h b/gcc/config/arm/rtems.h index c955d1f..14cb4df 100644 --- a/gcc/config/arm/rtems.h +++ b/gcc/config/arm/rtems.h @@ -1,5 +1,5 @@ /* Definitions for RTEMS based ARM systems using EABI. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/semi.h b/gcc/config/arm/semi.h index 298ede0..76448d0 100644 --- a/gcc/config/arm/semi.h +++ b/gcc/config/arm/semi.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. ARM on semi-hosted platform - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Richard Earnshaw (richard.earnshaw@arm.com) This file is part of GCC. diff --git a/gcc/config/arm/symbian.h b/gcc/config/arm/symbian.h index ebc7f10..f074936 100644 --- a/gcc/config/arm/symbian.h +++ b/gcc/config/arm/symbian.h @@ -1,5 +1,5 @@ /* Configuration file for Symbian OS on ARM processors. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 78498d0..e4682c0 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -1,5 +1,5 @@ ;; Machine description for ARM processor synchronization primitives. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com) ;; 64bit Atomics by Dave Gilbert (david.gilbert@linaro.org) ;; diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 9deb4fb..8574ac3 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 1f7f169..5f69ee6 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -1,6 +1,6 @@ # Rules common to all arm targets # -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index 3d92bd2..d68def3 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2020 Free Software Foundation, Inc. +# Copyright (C) 1998-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-fuchsia b/gcc/config/arm/t-fuchsia index 41d430b..e4f481a 100644 --- a/gcc/config/arm/t-fuchsia +++ b/gcc/config/arm/t-fuchsia @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2020 Free Software Foundation, Inc. +# Copyright (C) 2017-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-linux-eabi b/gcc/config/arm/t-linux-eabi index ef6dc07..315eb41 100644 --- a/gcc/config/arm/t-linux-eabi +++ b/gcc/config/arm/t-linux-eabi @@ -1,4 +1,4 @@ -# Copyright (C) 2005-2020 Free Software Foundation, Inc. +# Copyright (C) 2005-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 3993436..ddc5033 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-phoenix b/gcc/config/arm/t-phoenix index 7ccdafd..006f8ce 100644 --- a/gcc/config/arm/t-phoenix +++ b/gcc/config/arm/t-phoenix @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index 16e368f..1959189 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-symbian b/gcc/config/arm/t-symbian index d1d3fe9..320c3fc 100644 --- a/gcc/config/arm/t-symbian +++ b/gcc/config/arm/t-symbian @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-vxworks b/gcc/config/arm/t-vxworks index e18c0ee..fefb152 100644 --- a/gcc/config/arm/t-vxworks +++ b/gcc/config/arm/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 56705c9..c98b59c 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1,5 +1,5 @@ ;; ARM Thumb-1 Machine Description -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 2a8fdf2..bd53bf3 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1,5 +1,5 @@ ;; ARM Thumb-2 Machine Description -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. @@ -1261,7 +1261,9 @@ (set_attr "shift" "1") (set_attr "length" "2") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift_imm") + (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")))] ) @@ -1530,7 +1532,7 @@ "orn%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") (set_attr "shift" "2") - (set_attr "type" "alu_shift_imm")] + (set_attr "autodetect_type" "alu_shift_operator4")] ) (define_peephole2 diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 83983452..b9514da 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -1,6 +1,6 @@ ;; Instruction Classification for ARM for GNU compiler. -;; Copyright (C) 1991-2020 Free Software Foundation, Inc. +;; Copyright (C) 1991-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. @@ -19,6 +19,19 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. +; The insn need to autodetect for specific type attribute +(define_attr "autodetect_type" + "none, + alu_shift_lsl_op2, + alu_shift_lsr_op2, + alu_shift_asr_op2, + alu_shift_mul_op3, + alu_shift_operator1, + alu_shift_operator2, + alu_shift_operator3, + alu_shift_operator4" + (const_string "none")) + ; TYPE attribute is used to classify instructions for use in scheduling. ; ; Instruction classification: @@ -39,16 +52,21 @@ ; or an immediate operand. This excludes ; MOV and MVN but includes MOVT. This also excludes ; DSP-kind instructions. This is also the default. -; alu_shift_imm any arithmetic instruction that has a source operand -; shifted by a constant. This excludes simple shifts. -; alu_shift_reg as alu_shift_imm, with the shift amount specified in a +; alu_shift_imm_lsl_1to4 +; any arithmetic instruction that has a source operand +; shifted left by a constant in range 1 to 4. This +; excludes simple shifts. +; alu_shift_imm_other +; as alu_shift_imm_lsl_1to4, with the shift type is LSR or +; ASR, or the shift amount is greater than or equal 5. +; alu_shift_reg as alu_shift_imm_*, with the shift amount specified in a ; register. ; alu_dsp_reg any DSP-kind instruction like QSUB8. ; alus_ext From ARMv8-A: as alu_ext, setting condition flags. ; AArch64 Only. ; alus_imm as alu_imm, setting condition flags. ; alus_sreg as alu_sreg, setting condition flags. -; alus_shift_imm as alu_shift_imm, setting condition flags. +; alus_shift_imm as alu_shift_imm_*, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags. ; bfm bitfield move operation. ; bfx bitfield extract operation. @@ -565,7 +583,8 @@ alu_ext,\ alu_imm,\ alu_sreg,\ - alu_shift_imm,\ + alu_shift_imm_lsl_1to4,\ + alu_shift_imm_other,\ alu_shift_reg,\ alu_dsp_reg,\ alus_ext,\ @@ -1106,7 +1125,43 @@ mve_move,\ mve_store,\ mve_load" - (const_string "untyped")) + (cond [(eq_attr "autodetect_type" "alu_shift_lsr_op2,alu_shift_asr_op2") + (const_string "alu_shift_imm_other") + (eq_attr "autodetect_type" "alu_shift_lsl_op2") + (if_then_else (match_operand 2 "const_1_to_4_operand") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_mul_op3") + (if_then_else (match_operand 3 "const_2_4_8_16_operand") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator1") + (if_then_else (match_operand 1 "alu_shift_reg_p") + (const_string "alu_shift_reg") + (if_then_else (match_operand 1 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other"))) + (eq_attr "autodetect_type" "alu_shift_operator2") + (if_then_else (match_operand 2 "alu_shift_reg_p") + (const_string "alu_shift_reg") + (if_then_else (match_operand 2 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other"))) + (eq_attr "autodetect_type" "alu_shift_operator3") + (if_then_else (match_operand 3 "alu_shift_reg_p") + (const_string "alu_shift_reg") + (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other"))) + (eq_attr "autodetect_type" "alu_shift_operator4") + (if_then_else (match_operand 4 "alu_shift_reg_p") + (const_string "alu_shift_reg") + (if_then_else (match_operand 4 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other"))) + ] + (const_string "untyped"))) + ; Is this an (integer side) multiply with a 32-bit (or smaller) result? (define_attr "mul32" "no,yes" diff --git a/gcc/config/arm/uclinux-eabi.h b/gcc/config/arm/uclinux-eabi.h index d870831..93750dd 100644 --- a/gcc/config/arm/uclinux-eabi.h +++ b/gcc/config/arm/uclinux-eabi.h @@ -1,5 +1,5 @@ /* Definitions for ARM EABI ucLinux - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Paul Brook <paul@codesourcery.com> This file is part of GCC. diff --git a/gcc/config/arm/uclinux-elf.h b/gcc/config/arm/uclinux-elf.h index 1b42aea..8a69c82 100644 --- a/gcc/config/arm/uclinux-elf.h +++ b/gcc/config/arm/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for ARM running ucLinux using ELF - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Philip Blundell <pb@nexus.co.uk> This file is part of GCC. diff --git a/gcc/config/arm/uclinuxfdpiceabi.h b/gcc/config/arm/uclinuxfdpiceabi.h index cd58e9b..d74b26c 100644 --- a/gcc/config/arm/uclinuxfdpiceabi.h +++ b/gcc/config/arm/uclinuxfdpiceabi.h @@ -1,5 +1,5 @@ /* Configuration file for ARM GNU/Linux FDPIC EABI targets. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by STMicroelectronics. This file is part of GCC. diff --git a/gcc/config/arm/unknown-elf.h b/gcc/config/arm/unknown-elf.h index 9ad2947..cca6f0e 100644 --- a/gcc/config/arm/unknown-elf.h +++ b/gcc/config/arm/unknown-elf.h @@ -1,5 +1,5 @@ /* Definitions for non-Linux based ARM systems using ELF - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> This file is part of GCC. diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index a3844e9..4d47ab7 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -1,5 +1,5 @@ ;; Unspec defintions. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. @@ -510,6 +510,13 @@ UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270 + UNSPEC_VCMLA_CONJ + UNSPEC_VCMLA180_CONJ + UNSPEC_VCMUL + UNSPEC_VCMUL90 + UNSPEC_VCMUL180 + UNSPEC_VCMUL270 + UNSPEC_VCMUL_CONJ UNSPEC_MATMUL_S UNSPEC_MATMUL_U UNSPEC_MATMUL_US @@ -530,7 +537,6 @@ VRNDMQ_F VRNDAQ_F VREV64Q_F - VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F @@ -549,9 +555,6 @@ VREV64Q_S VREV64Q_U VQABSQ_S - VNEGQ_S - VMVNQ_S - VMVNQ_U VDUPQ_N_U VDUPQ_N_S VCLZQ_U @@ -601,15 +604,10 @@ VADDQ_N_S VADDVAQ_S VADDVQ_P_S - VANDQ_S - VBICQ_S VBRSRQ_N_S - VCADDQ_ROT270_S - VCADDQ_ROT90_S VCMPEQQ_S VCMPEQQ_N_S VCMPNEQ_N_S - VEORQ_S VHADDQ_S VHADDQ_N_S VHSUBQ_S @@ -624,8 +622,6 @@ VMULLTQ_INT_S VMULQ_S VMULQ_N_S - VORNQ_S - VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S @@ -648,15 +644,10 @@ VADDQ_N_U VADDVAQ_U VADDVQ_P_U - VANDQ_U - VBICQ_U VBRSRQ_N_U - VCADDQ_ROT270_U - VCADDQ_ROT90_U VCMPEQQ_U VCMPEQQ_N_U VCMPNEQ_N_U - VEORQ_U VHADDQ_U VHADDQ_N_U VHSUBQ_U @@ -671,8 +662,6 @@ VMULLTQ_INT_U VMULQ_U VMULQ_N_U - VORNQ_U - VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U @@ -721,10 +710,6 @@ VABDQ_M_U VABDQ_F VADDQ_N_F - VANDQ_F - VBICQ_F - VCADDQ_ROT270_F - VCADDQ_ROT90_F VCMPEQQ_F VCMPEQQ_N_F VCMPGEQ_F @@ -737,11 +722,6 @@ VCMPLTQ_N_F VCMPNEQ_F VCMPNEQ_N_F - VCMULQ_F - VCMULQ_ROT180_F - VCMULQ_ROT270_F - VCMULQ_ROT90_F - VEORQ_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F @@ -752,8 +732,6 @@ VMINNMVQ_F VMULQ_F VMULQ_N_F - VORNQ_F - VORRQ_F VSUBQ_F VADDLVAQ_U VADDLVAQ_S @@ -914,7 +892,6 @@ VMLSLDAVAQ_S VQSHRUNBQ_N_S VQRSHRUNTQ_N_S - VCMLAQ_F VMINNMAQ_M_F VFMASQ_N_F VDUPQ_M_N_F @@ -936,14 +913,12 @@ VADDLVAQ_P_S VQMOVUNBQ_M_S VCMPLEQ_M_F - VCMLAQ_ROT180_F VMLSLDAVAXQ_S VRNDXQ_M_F VFMSQ_F VMINNMVQ_P_F VMAXNMVQ_P_F VPSELQ_F - VCMLAQ_ROT90_F VQMOVUNTQ_M_S VREV64Q_M_F VNEGQ_M_F @@ -956,7 +931,6 @@ VRMLALDAVHQ_P_S VRMLALDAVHXQ_P_S VCMPEQQ_M_N_F - VCMLAQ_ROT270_F VMAXNMAQ_M_F VRNDQ_M_F VMLALDAVQ_P_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 250e503..345ada0 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -1,5 +1,5 @@ ;; Machine Description for shared bits common to IWMMXT and Neon. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. @@ -172,3 +172,184 @@ GEN_INT (elem), operands[0])); DONE; }) + +(define_expand "and<mode>3" + [(set (match_operand:VDQ 0 "s_register_operand" "") + (and:VDQ (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:VDQ 2 "neon_inv_logic_op2" "")))] + "ARM_HAVE_<MODE>_ARITH" +) + +(define_expand "ior<mode>3" + [(set (match_operand:VDQ 0 "s_register_operand" "") + (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:VDQ 2 "neon_logic_op2" "")))] + "ARM_HAVE_<MODE>_ARITH" +) + +(define_expand "xor<mode>3" + [(set (match_operand:VDQ 0 "s_register_operand" "") + (xor:VDQ (match_operand:VDQ 1 "s_register_operand" "") + (match_operand:VDQ 2 "s_register_operand" "")))] + "ARM_HAVE_<MODE>_ARITH" +) + +(define_expand "one_cmpl<mode>2" + [(set (match_operand:VDQ 0 "s_register_operand") + (not:VDQ (match_operand:VDQ 1 "s_register_operand")))] + "ARM_HAVE_<MODE>_ARITH" +) + +(define_expand "neg<mode>2" + [(set (match_operand:VDQWH 0 "s_register_operand" "") + (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))] + "ARM_HAVE_<MODE>_ARITH" +) + +(define_expand "cadd<rot><mode>3" + [(set (match_operand:VF 0 "register_operand") + (unspec:VF [(match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand")] + VCADD))] + "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT + && ARM_HAVE_<MODE>_ARITH)) && !BYTES_BIG_ENDIAN" +) + +;; The complex mul operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cmul<conj_op><mode>3" + [(set (match_operand:VQ_HSF 0 "register_operand") + (unspec:VQ_HSF [(match_operand:VQ_HSF 1 "register_operand") + (match_operand:VQ_HSF 2 "register_operand")] + VCMUL_OP))] + "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT)) + && !BYTES_BIG_ENDIAN" +{ + rtx res1 = gen_reg_rtx (<MODE>mode); + if (TARGET_COMPLEX) + { + rtx tmp = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode)); + emit_insn (gen_arm_vcmla<rotsplit1><mode> (res1, tmp, + operands[2], operands[1])); + } + else + emit_insn (gen_arm_vcmla<rotsplit1><mode> (res1, CONST0_RTX (<MODE>mode), + operands[2], operands[1])); + + emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], res1, + operands[2], operands[1])); + DONE; +}) + +(define_expand "arm_vcmla<rot><mode>" + [(set (match_operand:VF 0 "register_operand") + (plus:VF (match_operand:VF 1 "register_operand") + (unspec:VF [(match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")] + VCMLA)))] + "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT + && ARM_HAVE_<MODE>_ARITH)) && !BYTES_BIG_ENDIAN" +) + +;; The complex mla/mls operations always need to expand to two instructions. +;; The first operation does half the computation and the second does the +;; remainder. Because of this, expand early. +(define_expand "cml<fcmac1><conj_op><mode>4" + [(set (match_operand:VF 0 "register_operand") + (plus:VF (match_operand:VF 1 "register_operand") + (unspec:VF [(match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")] + VCMLA_OP)))] + "(TARGET_COMPLEX || (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT + && ARM_HAVE_<MODE>_ARITH)) && !BYTES_BIG_ENDIAN" +{ + rtx tmp = gen_reg_rtx (<MODE>mode); + emit_insn (gen_arm_vcmla<rotsplit1><mode> (tmp, operands[1], + operands[3], operands[2])); + emit_insn (gen_arm_vcmla<rotsplit2><mode> (operands[0], tmp, + operands[3], operands[2])); + DONE; +}) + +(define_expand "movmisalign<mode>" + [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand") + (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")] + UNSPEC_MISALIGNED_ACCESS))] + "ARM_HAVE_<MODE>_LDST && !BYTES_BIG_ENDIAN && unaligned_access" +{ + rtx adjust_mem; + /* This pattern is not permitted to fail during expansion: if both arguments + are non-registers (e.g. memory := constant, which can be created by the + auto-vectorizer), force operand 1 into a register. */ + if (!s_register_operand (operands[0], <MODE>mode) + && !s_register_operand (operands[1], <MODE>mode)) + operands[1] = force_reg (<MODE>mode, operands[1]); + + if (s_register_operand (operands[0], <MODE>mode)) + adjust_mem = operands[1]; + else + adjust_mem = operands[0]; + + /* Legitimize address. */ + if (!neon_vector_mem_operand (adjust_mem, 2, true)) + XEXP (adjust_mem, 0) = force_reg (Pmode, XEXP (adjust_mem, 0)); +}) + +(define_insn "mve_vshlq_<supf><mode>" + [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w") + (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w") + (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")] + VSHLQ))] + "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" + "@ + vshl.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 + * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);" + [(set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")] +) + +(define_expand "vashl<mode>3" + [(set (match_operand:VDQIW 0 "s_register_operand" "") + (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") + (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "")))] + "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" +{ + emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], operands[2])); + DONE; +}) + +;; When operand 2 is an immediate, use the normal expansion to match +;; gen_vashr<mode>3_imm for Neon and gen_mve_vshrq_n_s<mode>_imm for +;; MVE. +(define_expand "vashr<mode>3" + [(set (match_operand:VDQIW 0 "s_register_operand") + (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") + (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] + "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" +{ + if (s_register_operand (operands[2], <MODE>mode)) + { + rtx neg = gen_reg_rtx (<MODE>mode); + emit_insn (gen_neg<mode>2 (neg, operands[2])); + emit_insn (gen_mve_vshlq_s<mode> (operands[0], operands[1], neg)); + DONE; + } +}) + +;; When operand 2 is an immediate, use the normal expansion to match +;; gen_vashr<mode>3_imm for Neon and gen_mve_vshrq_n_u<mode>_imm for +;; MVE. +(define_expand "vlshr<mode>3" + [(set (match_operand:VDQIW 0 "s_register_operand") + (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") + (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] + "ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT" +{ + if (s_register_operand (operands[2], <MODE>mode)) + { + rtx neg = gen_reg_rtx (<MODE>mode); + emit_insn (gen_neg<mode>2 (neg, operands[2])); + emit_insn (gen_mve_vshlq_u<mode> (operands[0], operands[1], neg)); + DONE; + } +}) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index e6c287c..f97af92 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1,5 +1,5 @@ ;; ARM VFP instruction patterns -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md index 4d849b9..0c45bcd 100644 --- a/gcc/config/arm/vfp11.md +++ b/gcc/config/arm/vfp11.md @@ -1,5 +1,5 @@ ;; ARM VFP11 pipeline description -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 487ec0f..b71bedb 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ARM with targeting the VXWorks run time environment. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by: Mike Stump <mrs@wrs.com> Brought up to date by CodeSourcery, LLC. diff --git a/gcc/config/arm/vxworks.opt b/gcc/config/arm/vxworks.opt index da28984..ed2ddf4 100644 --- a/gcc/config/arm/vxworks.opt +++ b/gcc/config/arm/vxworks.opt @@ -1,6 +1,6 @@ ; ARM VxWorks options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index a2f6b8a1..ae909bf 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -1,5 +1,5 @@ ;; Machine description for AppliedMicro xgene1 core. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Theobroma Systems Design und Consulting GmbH. ;; ;; This file is part of GCC. @@ -132,7 +132,7 @@ (define_insn_reservation "xgene1_alu" 1 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm,\ + (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,\ alu_ext,adc_reg,logic_imm,\ logic_reg,logic_shift_imm,clz,\ rbit,adr,mov_reg,shift_imm,\ diff --git a/gcc/config/avr/avr-arch.h b/gcc/config/avr/avr-arch.h index 7fb99a9..29834f4 100644 --- a/gcc/config/avr/avr-arch.h +++ b/gcc/config/avr/avr-arch.h @@ -1,6 +1,6 @@ /* Definitions of types that are used to store AVR architecture and device information. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c index 35f3e7e..fda56edc 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Anatoly Sokolov (aesok@post.ru) This file is part of GCC. diff --git a/gcc/config/avr/avr-devices.c b/gcc/config/avr/avr-devices.c index ac1427f..60efc3a 100644 --- a/gcc/config/avr/avr-devices.c +++ b/gcc/config/avr/avr-devices.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Anatoly Sokolov (aesok@post.ru) This file is part of GCC. diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md index adffd2b..1817c16 100644 --- a/gcc/config/avr/avr-dimode.md +++ b/gcc/config/avr/avr-dimode.md @@ -1,6 +1,6 @@ ;; Machine description for GNU compiler, ;; for Atmel AVR micro controllers. -;; Copyright (C) 1998-2020 Free Software Foundation, Inc. +;; Copyright (C) 1998-2021 Free Software Foundation, Inc. ;; Contributed by Georg Lay (avr@gjlay.de) ;; ;; This file is part of GCC. diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md index 737fe97..a3b49d5 100644 --- a/gcc/config/avr/avr-fixed.md +++ b/gcc/config/avr/avr-fixed.md @@ -1,6 +1,6 @@ ;; This file contains instructions that support fixed-point operations ;; for Atmel AVR micro controllers. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; Contributed by Sean D'Epagnier (sean@depagnier.com) ;; Georg-Johann Lay (avr@gjlay.de) diff --git a/gcc/config/avr/avr-log.c b/gcc/config/avr/avr-log.c index 8d8189b..a4dc0f6 100644 --- a/gcc/config/avr/avr-log.c +++ b/gcc/config/avr/avr-log.c @@ -1,5 +1,5 @@ /* Subroutines for log output for Atmel AVR back end. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def index 24046c3..37e4e9b 100644 --- a/gcc/config/avr/avr-mcus.def +++ b/gcc/config/avr/avr-mcus.def @@ -1,5 +1,5 @@ /* AVR MCUs. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr-modes.def b/gcc/config/avr/avr-modes.def index 6dba658..9a09317 100644 --- a/gcc/config/avr/avr-modes.def +++ b/gcc/config/avr/avr-modes.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr-passes.def b/gcc/config/avr/avr-passes.def index 87505d1..7c76e43 100644 --- a/gcc/config/avr/avr-passes.def +++ b/gcc/config/avr/avr-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for AVR. - Copyright (C) 2016-2020 Free Software Foundation, Inc. */ + Copyright (C) 2016-2021 Free Software Foundation, Inc. */ /* This file is part of GCC. diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 16c894c..9999945 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -1,6 +1,6 @@ /* Prototypes for exported functions defined in avr.c - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. diff --git a/gcc/config/avr/avr-stdint.h b/gcc/config/avr/avr-stdint.h index eb54c88..2f876e1 100644 --- a/gcc/config/avr/avr-stdint.h +++ b/gcc/config/avr/avr-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using newlib. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index 61168ed..3a250df 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for ATMEL AVR micro controllers - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index c723b8a..0026a66 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for ATMEL AVR at90s8515, ATmega103/103L, ATmega603/603L microcontrollers. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 41eb78c..478abc1 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -1,6 +1,6 @@ ;; Machine description for GNU compiler, ;; for ATMEL AVR micro controllers. -;; Copyright (C) 1998-2020 Free Software Foundation, Inc. +;; Copyright (C) 1998-2021 Free Software Foundation, Inc. ;; Contributed by Denis Chertykov (chertykov@gmail.com) ;; This file is part of GCC. diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index fac3114..e864734 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -1,6 +1,6 @@ ; Options for the ATMEL AVR port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. mcall-prologues -Target Report Mask(CALL_PROLOGUES) +Target Mask(CALL_PROLOGUES) Use subroutines for function prologues and epilogues. mmcu= @@ -27,7 +27,7 @@ Target RejectNegative Joined Var(avr_mmcu) MissingArgError(missing device or arc -mmcu=MCU Select the target MCU. mgas-isr-prologues -Target Report Var(avr_gasisr_prologues) UInteger Init(0) +Target Var(avr_gasisr_prologues) UInteger Init(0) Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues. mn-flash= @@ -35,100 +35,100 @@ Target RejectNegative Joined Var(avr_n_flash) UInteger Init(-1) Set the number of 64 KiB flash segments. mskip-bug -Target Report Mask(SKIP_BUG) +Target Mask(SKIP_BUG) Indicate presence of a processor erratum. mrmw -Target Report Mask(RMW) +Target Mask(RMW) Enable Read-Modify-Write (RMW) instructions support/use. mdeb -Target Report Undocumented Mask(ALL_DEBUG) +Target Undocumented Mask(ALL_DEBUG) mlog= Target RejectNegative Joined Undocumented Var(avr_log_details) mshort-calls -Target Report RejectNegative Mask(SHORT_CALLS) +Target RejectNegative Mask(SHORT_CALLS) Use RJMP / RCALL even though CALL / JMP are available. mint8 -Target Report Mask(INT8) +Target Mask(INT8) Use an 8-bit 'int' type. mno-interrupts -Target Report RejectNegative Mask(NO_INTERRUPTS) +Target RejectNegative Mask(NO_INTERRUPTS) Change the stack pointer without disabling interrupts. mbranch-cost= -Target Report Joined RejectNegative UInteger Var(avr_branch_cost) Init(0) +Target Joined RejectNegative UInteger Var(avr_branch_cost) Init(0) Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0. mmain-is-OS_task -Target Report Mask(MAIN_IS_OS_TASK) +Target Mask(MAIN_IS_OS_TASK) Treat main as if it had attribute OS_task. morder1 -Target Report Undocumented Mask(ORDER_1) +Target Undocumented Mask(ORDER_1) morder2 -Target Report Undocumented Mask(ORDER_2) +Target Undocumented Mask(ORDER_2) mtiny-stack -Target Report Mask(TINY_STACK) +Target Mask(TINY_STACK) Change only the low 8 bits of the stack pointer. mrelax -Target Report +Target Relax branches. mpmem-wrap-around -Target Report +Target Make the linker relaxation machine assume that a program counter wrap-around occurs. maccumulate-args -Target Report Mask(ACCUMULATE_OUTGOING_ARGS) +Target Mask(ACCUMULATE_OUTGOING_ARGS) Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf. mstrict-X -Target Report Var(avr_strict_X) Init(0) +Target Var(avr_strict_X) Init(0) When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. ;; For rationale behind -msp8 see explanation in avr.h. msp8 -Target Report RejectNegative Var(avr_sp8) Init(0) +Target RejectNegative Var(avr_sp8) Init(0) The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU. Waddr-space-convert -Warning C Report Var(avr_warn_addr_space_convert) Init(0) +Warning C Var(avr_warn_addr_space_convert) Init(0) Warn if the address space of an address is changed. Wmisspelled-isr -Warning C C++ Report Var(avr_warn_misspelled_isr) Init(1) +Warning C C++ Var(avr_warn_misspelled_isr) Init(1) Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default. mfract-convert-truncate -Target Report Mask(FRACT_CONV_TRUNC) +Target Mask(FRACT_CONV_TRUNC) Allow to use truncation instead of rounding towards zero for fractional fixed-point types. mabsdata -Target Report Mask(ABSDATA) +Target Mask(ABSDATA) Assume that all data in static storage can be accessed by LDS / STS. This option is only useful for reduced Tiny devices. mdouble= -Target Report Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e) +Target Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e) -mdouble=<BITS> Use <BITS> bits wide double type. mlong-double= -Target Report Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e) +Target Joined RejectNegative Var(avr_long_double) Init(0) Enum(avr_bits_e) -mlong-double=<BITS> Use <BITS> bits wide long double type. nodevicelib -Driver Target Report RejectNegative +Driver Target RejectNegative Do not link against the device-specific library lib<MCU>.a. nodevicespecs -Driver Target Report RejectNegative +Driver Target RejectNegative Do not use the device-specific specs file device-specs/specs-<MCU>. Enum diff --git a/gcc/config/avr/avrlibc.h b/gcc/config/avr/avrlibc.h index 8e4d696..068f6c3 100644 --- a/gcc/config/avr/avrlibc.h +++ b/gcc/config/avr/avrlibc.h @@ -1,6 +1,6 @@ /* Definitions of target machine for the GNU compiler collection for Atmel AVR micro controller if configured for AVR-Libc. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/builtins.def b/gcc/config/avr/builtins.def index 4e111e2..4e4b440 100644 --- a/gcc/config/avr/builtins.def +++ b/gcc/config/avr/builtins.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md index d7a8ae6..f653ee4 100644 --- a/gcc/config/avr/constraints.md +++ b/gcc/config/avr/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for ATMEL AVR micro controllers. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/avr/driver-avr.c b/gcc/config/avr/driver-avr.c index 8438904..b840c7d 100644 --- a/gcc/config/avr/driver-avr.c +++ b/gcc/config/avr/driver-avr.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay <avr@gjlay.de> This file is part of GCC. diff --git a/gcc/config/avr/elf.h b/gcc/config/avr/elf.h index 5dfa750..2f0eb0d 100644 --- a/gcc/config/avr/elf.h +++ b/gcc/config/avr/elf.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/gen-avr-mmcu-specs.c b/gcc/config/avr/gen-avr-mmcu-specs.c index 63ac782..b9e935b 100644 --- a/gcc/config/avr/gen-avr-mmcu-specs.c +++ b/gcc/config/avr/gen-avr-mmcu-specs.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1998-2020 Free Software Foundation, Inc. +/* Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Joern Rennecke This file is part of GCC. diff --git a/gcc/config/avr/gen-avr-mmcu-texi.c b/gcc/config/avr/gen-avr-mmcu-texi.c index a03c6bb..29252a5 100644 --- a/gcc/config/avr/gen-avr-mmcu-texi.c +++ b/gcc/config/avr/gen-avr-mmcu-texi.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. @@ -160,7 +160,7 @@ int main (void) size_t i, n_mcus = 0; const avr_mcu_t *mcu; - printf ("@c Copyright (C) 2012-2020 Free Software Foundation, Inc.\n"); + printf ("@c Copyright (C) 2012-2021 Free Software Foundation, Inc.\n"); printf ("@c This is part of the GCC manual.\n"); printf ("@c For copying conditions, see the file " "gcc/doc/include/fdl.texi.\n\n"); diff --git a/gcc/config/avr/genmultilib.awk b/gcc/config/avr/genmultilib.awk index 2d07c0e..efe41dd 100644 --- a/gcc/config/avr/genmultilib.awk +++ b/gcc/config/avr/genmultilib.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md index 2a06905..0b9a97d 100644 --- a/gcc/config/avr/predicates.md +++ b/gcc/config/avr/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for ATMEL AVR micro controllers. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/avr/specs.h b/gcc/config/avr/specs.h index bcad7bc..a0e09cb 100644 --- a/gcc/config/avr/specs.h +++ b/gcc/config/avr/specs.h @@ -1,6 +1,6 @@ /* Specs definitions for Atmel AVR back end. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/stdfix.h b/gcc/config/avr/stdfix.h index 4289bad..79c20fc 100644 --- a/gcc/config/avr/stdfix.h +++ b/gcc/config/avr/stdfix.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/t-avr b/gcc/config/avr/t-avr index 3e1a1ba..06a0a3a 100644 --- a/gcc/config/avr/t-avr +++ b/gcc/config/avr/t-avr @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2020 Free Software Foundation, Inc. +# Copyright (C) 2000-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/bfin-modes.def b/gcc/config/bfin/bfin-modes.def index 49f7d65..9d7780b 100644 --- a/gcc/config/bfin/bfin-modes.def +++ b/gcc/config/bfin/bfin-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Blackfin. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin-opts.h b/gcc/config/bfin/bfin-opts.h index 41f2acf..2ce1968 100644 --- a/gcc/config/bfin/bfin-opts.h +++ b/gcc/config/bfin/bfin-opts.h @@ -1,5 +1,5 @@ /* Definitions for the Blackfin port needed for option handling. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/bfin-protos.h b/gcc/config/bfin/bfin-protos.h index 03719aa..27c4e00 100644 --- a/gcc/config/bfin/bfin-protos.h +++ b/gcc/config/bfin/bfin-protos.h @@ -1,5 +1,5 @@ /* Prototypes for Blackfin functions used in the md file & elsewhere. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index d03b259..a000b7a 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -1,5 +1,5 @@ /* The Blackfin code generation auxiliary output file. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 0ebdc45..f282d05 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -1,5 +1,5 @@ /* Definitions for the Blackfin port. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index aecb813..1ec0bbb 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1,5 +1,5 @@ ;;- Machine description for Blackfin for GNU compiler -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; This file is part of GCC. diff --git a/gcc/config/bfin/bfin.opt b/gcc/config/bfin/bfin.opt index afda508..230778c 100644 --- a/gcc/config/bfin/bfin.opt +++ b/gcc/config/bfin/bfin.opt @@ -1,6 +1,6 @@ ; Options for the Blackfin port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -44,28 +44,28 @@ Target RejectNegative Joined Specify the name of the target CPU. momit-leaf-frame-pointer -Target Report Mask(OMIT_LEAF_FRAME_POINTER) +Target Mask(OMIT_LEAF_FRAME_POINTER) Omit frame pointer for leaf functions. mlow64k -Target Report Mask(LOW_64K) +Target Mask(LOW_64K) Program is entirely located in low 64k of memory. mcsync-anomaly -Target Report Var(bfin_csync_anomaly) Init(-1) +Target Var(bfin_csync_anomaly) Init(-1) Work around a hardware anomaly by adding a number of NOPs before a CSYNC or SSYNC instruction. mspecld-anomaly -Target Report Var(bfin_specld_anomaly) Init(-1) +Target Var(bfin_specld_anomaly) Init(-1) Avoid speculative loads to work around a hardware anomaly. mid-shared-library -Target Report Mask(ID_SHARED_LIBRARY) +Target Mask(ID_SHARED_LIBRARY) Enabled ID based shared library. mleaf-id-shared-library -Target Report Mask(LEAF_ID_SHARED_LIBRARY) +Target Mask(LEAF_ID_SHARED_LIBRARY) Generate code that won't be linked against any other ID shared libraries, but may be used as a shared library. @@ -74,45 +74,45 @@ Target RejectNegative Joined UInteger Var(bfin_library_id) ID of shared library to build. msep-data -Target Report Mask(SEP_DATA) +Target Mask(SEP_DATA) Enable separate data segment. mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Avoid generating pc-relative calls; use indirection. mfast-fp -Target Report Mask(FAST_FP) +Target Mask(FAST_FP) Link with the fast floating-point library. mfdpic -Target Report Mask(FDPIC) +Target Mask(FDPIC) Enable Function Descriptor PIC mode. minline-plt -Target Report Mask(INLINE_PLT) +Target Mask(INLINE_PLT) Enable inlining of PLT in function calls. mstack-check-l1 -Target Report Mask(STACK_CHECK_L1) +Target Mask(STACK_CHECK_L1) Do stack checking using bounds in L1 scratch memory. mmulticore -Target Report Mask(MULTICORE) +Target Mask(MULTICORE) Enable multicore support. mcorea -Target Report Mask(COREA) +Target Mask(COREA) Build for Core A. mcoreb -Target Report Mask(COREB) +Target Mask(COREB) Build for Core B. msdram -Target Report Mask(SDRAM) +Target Mask(SDRAM) Build for SDRAM. micplb -Target Report Mask(ICPLB) +Target Mask(ICPLB) Assume ICPLBs are enabled at runtime. diff --git a/gcc/config/bfin/constraints.md b/gcc/config/bfin/constraints.md index 69ab95a..04a73e9 100644 --- a/gcc/config/bfin/constraints.md +++ b/gcc/config/bfin/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Blackfin -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Analog Devices ;; This file is part of GCC. diff --git a/gcc/config/bfin/elf.h b/gcc/config/bfin/elf.h index 203ec5c..81b6082 100644 --- a/gcc/config/bfin/elf.h +++ b/gcc/config/bfin/elf.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2020 Free Software Foundation, Inc. +/* Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/linux.h b/gcc/config/bfin/linux.h index 9c882a7..64f1560 100644 --- a/gcc/config/bfin/linux.h +++ b/gcc/config/bfin/linux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md index 3a85691..d82e367 100644 --- a/gcc/config/bfin/predicates.md +++ b/gcc/config/bfin/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for the Blackfin. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; ;; This file is part of GCC. diff --git a/gcc/config/bfin/print-sysroot-suffix.sh b/gcc/config/bfin/print-sysroot-suffix.sh index a303d62..960c256 100644 --- a/gcc/config/bfin/print-sysroot-suffix.sh +++ b/gcc/config/bfin/print-sysroot-suffix.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # This file is part of GCC. # GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/bfin/rtems.h b/gcc/config/bfin/rtems.h index 8bdd8e0..6aa1527 100644 --- a/gcc/config/bfin/rtems.h +++ b/gcc/config/bfin/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a bfin - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Ralf Corsépius (ralf.corsepius@rtems.org). This file is part of GCC. diff --git a/gcc/config/bfin/sync.md b/gcc/config/bfin/sync.md index 176d86f..b1e4cbc 100644 --- a/gcc/config/bfin/sync.md +++ b/gcc/config/bfin/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for Blackfin synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; ;; This file is part of GCC. diff --git a/gcc/config/bfin/t-bfin-elf b/gcc/config/bfin/t-bfin-elf index ac10286..5a2cdfa 100644 --- a/gcc/config/bfin/t-bfin-elf +++ b/gcc/config/bfin/t-bfin-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2005-2020 Free Software Foundation, Inc. +# Copyright (C) 2005-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/t-bfin-linux b/gcc/config/bfin/t-bfin-linux index 4da409e..9a79826 100644 --- a/gcc/config/bfin/t-bfin-linux +++ b/gcc/config/bfin/t-bfin-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/t-bfin-uclinux b/gcc/config/bfin/t-bfin-uclinux index 136bc37..e6f75ee 100644 --- a/gcc/config/bfin/t-bfin-uclinux +++ b/gcc/config/bfin/t-bfin-uclinux @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/uclinux.h b/gcc/config/bfin/uclinux.h index d4e4f30..cfb3d78 100644 --- a/gcc/config/bfin/uclinux.h +++ b/gcc/config/bfin/uclinux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2020 Free Software Foundation, Inc. +/* Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf-helpers.h b/gcc/config/bpf/bpf-helpers.h index a615321..da088c4 100644 --- a/gcc/config/bpf/bpf-helpers.h +++ b/gcc/config/bpf/bpf-helpers.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf-opts.h b/gcc/config/bpf/bpf-opts.h index 2d23ae4..1bc930c 100644 --- a/gcc/config/bpf/bpf-opts.h +++ b/gcc/config/bpf/bpf-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for eBPF. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf-protos.h b/gcc/config/bpf/bpf-protos.h index 8732765..aeb5126 100644 --- a/gcc/config/bpf/bpf-protos.h +++ b/gcc/config/bpf/bpf-protos.h @@ -1,5 +1,5 @@ /* Definition of eBPF target for GNU compiler. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf.c b/gcc/config/bpf/bpf.c index 13181f2..126d4a2 100644 --- a/gcc/config/bpf/bpf.c +++ b/gcc/config/bpf/bpf.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation for eBPF. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf.h b/gcc/config/bpf/bpf.h index 359f389..9e2f526 100644 --- a/gcc/config/bpf/bpf.h +++ b/gcc/config/bpf/bpf.h @@ -1,5 +1,5 @@ /* Definition of the eBPF target for GCC. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index 8e7cf50..03830cc 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -1,5 +1,5 @@ ;; Machine description for eBPF. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt index 6aa8584..916b53c 100644 --- a/gcc/config/bpf/bpf.opt +++ b/gcc/config/bpf/bpf.opt @@ -1,6 +1,6 @@ ; Options for the eBPF compiler port. -; Copyright (C) 2019-2020 Free Software Foundation, Inc. +; Copyright (C) 2019-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -111,17 +111,17 @@ Enum(bpf_kernel) String(5.2) Value(LINUX_V5_2) ; Use xBPF extensions. mxbpf -Target Report Mask(XBPF) +Target Mask(XBPF) Generate xBPF. ; Selecting big endian or little endian targets. mbig-endian -Target RejectNegative Report Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Generate big-endian eBPF. mlittle-endian -Target RejectNegative Report InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Generate little-endian eBPF. mframe-limit= diff --git a/gcc/config/bpf/constraints.md b/gcc/config/bpf/constraints.md index 9e203be..66b7764 100644 --- a/gcc/config/bpf/constraints.md +++ b/gcc/config/bpf/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for eBPF. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/bpf/predicates.md b/gcc/config/bpf/predicates.md index ce3cbc6..5d670ab 100644 --- a/gcc/config/bpf/predicates.md +++ b/gcc/config/bpf/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for eBPF. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/c6x/c6x-isas.def b/gcc/config/c6x/c6x-isas.def index 4d8339a..e8225a76 100644 --- a/gcc/config/c6x/c6x-isas.def +++ b/gcc/config/c6x/c6x-isas.def @@ -1,5 +1,5 @@ /* C6X ISA names. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-modes.def b/gcc/config/c6x/c6x-modes.def index ff4e1d5..33dfc95 100644 --- a/gcc/config/c6x/c6x-modes.def +++ b/gcc/config/c6x/c6x-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for TI C6x. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-mult.md b/gcc/config/c6x/c6x-mult.md index c9249eb..f99e037 100644 --- a/gcc/config/c6x/c6x-mult.md +++ b/gcc/config/c6x/c6x-mult.md @@ -3,7 +3,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -424,7 +424,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-mult.md.in b/gcc/config/c6x/c6x-mult.md.in index a09eab4..405f76b 100644 --- a/gcc/config/c6x/c6x-mult.md.in +++ b/gcc/config/c6x/c6x-mult.md.in @@ -1,7 +1,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-opts.h b/gcc/config/c6x/c6x-opts.h index fef5601a..0b4fe67 100644 --- a/gcc/config/c6x/c6x-opts.h +++ b/gcc/config/c6x/c6x-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for TI C6X. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-protos.h b/gcc/config/c6x/c6x-protos.h index 92d6008..922c0c7 100644 --- a/gcc/config/c6x/c6x-protos.h +++ b/gcc/config/c6x/c6x-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in c6x.c. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-sched.md b/gcc/config/c6x/c6x-sched.md index 77cb956..f84786b 100644 --- a/gcc/config/c6x/c6x-sched.md +++ b/gcc/config/c6x/c6x-sched.md @@ -4,7 +4,7 @@ ;; Definitions for side 1, cross n ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -237,7 +237,7 @@ ;; Definitions for side 2, cross n ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -470,7 +470,7 @@ ;; Definitions for side 1, cross y ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -703,7 +703,7 @@ ;; Definitions for side 2, cross y ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-sched.md.in b/gcc/config/c6x/c6x-sched.md.in index 90e3c44..c52be86 100644 --- a/gcc/config/c6x/c6x-sched.md.in +++ b/gcc/config/c6x/c6x-sched.md.in @@ -1,5 +1,5 @@ ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-tables.opt b/gcc/config/c6x/c6x-tables.opt index a1ad036..a3f60c3 100644 --- a/gcc/config/c6x/c6x-tables.opt +++ b/gcc/config/c6x/c6x-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from c6x-isas.def. ; -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c index 78b2bff..f9ad1e5 100644 --- a/gcc/config/c6x/c6x.c +++ b/gcc/config/c6x/c6x.c @@ -1,5 +1,5 @@ /* Target Code for TI C6X - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/c6x.h b/gcc/config/c6x/c6x.h index d96f12e..9e0a20d 100644 --- a/gcc/config/c6x/c6x.h +++ b/gcc/config/c6x/c6x.h @@ -1,5 +1,5 @@ /* Target Definitions for TI C6X. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md index 17c0d16..9ac101a 100644 --- a/gcc/config/c6x/c6x.md +++ b/gcc/config/c6x/c6x.md @@ -1,5 +1,5 @@ ;; Machine description for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Jenner <andrew@codesourcery.com> ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. diff --git a/gcc/config/c6x/c6x.opt b/gcc/config/c6x/c6x.opt index 16867a6..7f8eb54 100644 --- a/gcc/config/c6x/c6x.opt +++ b/gcc/config/c6x/c6x.opt @@ -1,5 +1,5 @@ ; Option definitions for TI C6X. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; Contributed by Bernd Schmidt <bernds@codesourcery.com> ; Contributed by CodeSourcery. ; @@ -26,11 +26,11 @@ SourceInclude config/c6x/c6x-opts.h mbig-endian -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Use big-endian byte order. mlittle-endian -Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) Use little-endian byte order. msim @@ -59,7 +59,7 @@ Target Mask(DSBT) Compile for the DSBT shared library ABI. mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Avoid generating pc-relative calls; use indirection. march= diff --git a/gcc/config/c6x/c6x_intrinsics.h b/gcc/config/c6x/c6x_intrinsics.h index 43d46bd..0d70b22 100644 --- a/gcc/config/c6x/c6x_intrinsics.h +++ b/gcc/config/c6x/c6x_intrinsics.h @@ -1,6 +1,6 @@ /* Intrinsics for TI C6X. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/c6x/constraints.md b/gcc/config/c6x/constraints.md index 0e76b30..e8b37a9 100644 --- a/gcc/config/c6x/constraints.md +++ b/gcc/config/c6x/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for TI C6X. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Jenner <andrew@codesourcery.com> ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. diff --git a/gcc/config/c6x/elf-common.h b/gcc/config/c6x/elf-common.h index bb86034..f6003ef 100644 --- a/gcc/config/c6x/elf-common.h +++ b/gcc/config/c6x/elf-common.h @@ -1,5 +1,5 @@ /* ELF definitions for TI C6X - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/elf.h b/gcc/config/c6x/elf.h index 5c44468..1a20e96 100644 --- a/gcc/config/c6x/elf.h +++ b/gcc/config/c6x/elf.h @@ -1,5 +1,5 @@ /* ELF definitions for TI C6X - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/genmult.sh b/gcc/config/c6x/genmult.sh index 8bca103..8dd2aeb 100644 --- a/gcc/config/c6x/genmult.sh +++ b/gcc/config/c6x/genmult.sh @@ -2,7 +2,7 @@ # Generate c6x-mult.md from c6x-mult.md.in # The input file is passed as an argument. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. #This file is part of GCC. diff --git a/gcc/config/c6x/genopt.sh b/gcc/config/c6x/genopt.sh index ba4d224..ec654df 100644 --- a/gcc/config/c6x/genopt.sh +++ b/gcc/config/c6x/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate c6x-tables.opt from the lists in *.def. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from c6x-isas.def. ; -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/c6x/gensched.sh b/gcc/config/c6x/gensched.sh index 4459b2b..3cc1977 100644 --- a/gcc/config/c6x/gensched.sh +++ b/gcc/config/c6x/gensched.sh @@ -2,7 +2,7 @@ # Generate c6x-sched.md from c6x-sched.md.in # The input file is passed as an argument. -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. #This file is part of GCC. diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md index 329a762..88961b2 100644 --- a/gcc/config/c6x/predicates.md +++ b/gcc/config/c6x/predicates.md @@ -1,5 +1,5 @@ /* Predicates for TI C6X - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/sync.md b/gcc/config/c6x/sync.md index b60b38a..5057ea3 100644 --- a/gcc/config/c6x/sync.md +++ b/gcc/config/c6x/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for C6X synchronization instructions. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/c6x/t-c6x b/gcc/config/c6x/t-c6x index 7ea6c1d..6a42db1 100644 --- a/gcc/config/c6x/t-c6x +++ b/gcc/config/c6x/t-c6x @@ -1,5 +1,5 @@ # Target Makefile Fragment for TI C6X. -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # Contributed by CodeSourcery. # # This file is part of GCC. diff --git a/gcc/config/c6x/t-c6x-elf b/gcc/config/c6x/t-c6x-elf index 1d25ec6..69e440d 100644 --- a/gcc/config/c6x/t-c6x-elf +++ b/gcc/config/c6x/t-c6x-elf @@ -1,5 +1,5 @@ # Target Makefile Fragment for TI C6X using ELF. -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # Contributed by CodeSourcery. # # This file is part of GCC. diff --git a/gcc/config/c6x/uclinux-elf.h b/gcc/config/c6x/uclinux-elf.h index bd87e4c..635f547 100644 --- a/gcc/config/c6x/uclinux-elf.h +++ b/gcc/config/c6x/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for TI C6X running ucLinux using ELF - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/cr16/constraints.md b/gcc/config/cr16/constraints.md index d1da289..758716b 100644 --- a/gcc/config/cr16/constraints.md +++ b/gcc/config/cr16/constraints.md @@ -1,5 +1,5 @@ ;; Predicates of machine description for CR16. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; ;; This file is part of GCC. diff --git a/gcc/config/cr16/cr16-protos.h b/gcc/config/cr16/cr16-protos.h index 6ebc0b3..32f54e0 100644 --- a/gcc/config/cr16/cr16-protos.h +++ b/gcc/config/cr16/cr16-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in cr16.c - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c index bcbfc8f..079706f 100644 --- a/gcc/config/cr16/cr16.c +++ b/gcc/config/cr16/cr16.c @@ -1,5 +1,5 @@ /* Output routines for CR16 processor. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h index 4af90bf..ae90610 100644 --- a/gcc/config/cr16/cr16.h +++ b/gcc/config/cr16/cr16.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for CR16. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.md b/gcc/config/cr16/cr16.md index 3e9f5f7..5ec66ad 100644 --- a/gcc/config/cr16/cr16.md +++ b/gcc/config/cr16/cr16.md @@ -1,5 +1,5 @@ ;; GCC machine description for CR16. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; This file is part of GCC. diff --git a/gcc/config/cr16/cr16.opt b/gcc/config/cr16/cr16.opt index f82c1d6..6489c9e 100644 --- a/gcc/config/cr16/cr16.opt +++ b/gcc/config/cr16/cr16.opt @@ -1,5 +1,5 @@ ; Options for the National Semiconductor CR16 port of the compiler. -; Copyright (C) 2012-2020 Free Software Foundation, Inc. +; Copyright (C) 2012-2021 Free Software Foundation, Inc. ; Contributed by KPIT Cummins Infosystems Limited. ; ; This file is part of GCC. @@ -23,11 +23,11 @@ Target Use simulator runtime. mbit-ops -Target Report Mask(BIT_OPS) +Target Mask(BIT_OPS) Generate SBIT, CBIT instructions. mmac -Target Report Mask(MAC) +Target Mask(MAC) Support multiply accumulate instructions. mdebug-addr diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md index 3b8b73f..5248833 100644 --- a/gcc/config/cr16/predicates.md +++ b/gcc/config/cr16/predicates.md @@ -1,5 +1,5 @@ ;; Predicates of machine description for CR16. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; ;; This file is part of GCC. diff --git a/gcc/config/cr16/t-cr16 b/gcc/config/cr16/t-cr16 index e18a15a..646f73c 100644 --- a/gcc/config/cr16/t-cr16 +++ b/gcc/config/cr16/t-cr16 @@ -1,5 +1,5 @@ # CR16 Target Makefile -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by KPIT Cummins Infosystems Limited. # # This file is part of GCC. diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index e177a3c..a230e78 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for CRIS. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/cris-modes.def b/gcc/config/cris/cris-modes.def index 874e4c1..41fa309 100644 --- a/gcc/config/cris/cris-modes.def +++ b/gcc/config/cris/cris-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for CRIS. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/cris/cris-passes.def b/gcc/config/cris/cris-passes.def index db3c74d..983813c 100644 --- a/gcc/config/cris/cris-passes.def +++ b/gcc/config/cris/cris-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for Visium. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index 053bba9..16e2952 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Axis Communications. This file is part of GCC. diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 59cbcee..48ea855 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Axis Communications. Written by Hans-Peter Nilsson. This file is part of GCC. diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 2a938fe..d691da9 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Axis Communications. Written by Hans-Peter Nilsson. This file is part of GCC. diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index efafb5b..0fd29f9 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -1,5 +1,5 @@ ;; GCC machine description for CRIS cpu cores. -;; Copyright (C) 1998-2020 Free Software Foundation, Inc. +;; Copyright (C) 1998-2021 Free Software Foundation, Inc. ;; Contributed by Axis Communications. ;; This file is part of GCC. diff --git a/gcc/config/cris/cris.opt b/gcc/config/cris/cris.opt index e574a0a..ec0f5c4 100644 --- a/gcc/config/cris/cris.opt +++ b/gcc/config/cris/cris.opt @@ -1,6 +1,6 @@ ; Options for the CRIS port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -41,111 +41,111 @@ ; driver-like program that gets a mapping of I/O registers (all ; on the same page, including the TLB registers). mmul-bug-workaround -Target Report Mask(MUL_BUG) +Target Mask(MUL_BUG) Work around bug in multiplication instruction. ; TARGET_ETRAX4_ADD: Instruction-set additions from Etrax 4 and up. ; (Just "lz".) metrax4 -Target Report Mask(ETRAX4_ADD) +Target Mask(ETRAX4_ADD) Compile for ETRAX 4 (CRIS v3). ; See cris_handle_option. metrax100 -Target Report RejectNegative +Target RejectNegative Compile for ETRAX 100 (CRIS v8). ; See cris_handle_option. mno-etrax100 -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented mpdebug -Target Report Mask(PDEBUG) +Target Mask(PDEBUG) Emit verbose debug information in assembly code. ; TARGET_CCINIT: Whether to use condition-codes generated by ; insns other than the immediately preceding compare/test insn. ; Used to check for errors in notice_update_cc. mcc-init -Target Report Mask(CCINIT) +Target Mask(CCINIT) Do not use condition codes from normal instructions. ; TARGET_SIDE_EFFECT_PREFIXES: Whether to use side-effect ; patterns. Used to debug the [rx=ry+i] type patterns. mside-effects -Target Report RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented +Target RejectNegative Mask(SIDE_EFFECT_PREFIXES) Undocumented mno-side-effects -Target Report RejectNegative InverseMask(SIDE_EFFECT_PREFIXES) +Target RejectNegative InverseMask(SIDE_EFFECT_PREFIXES) Do not emit addressing modes with side-effect assignment. ; TARGET_STACK_ALIGN: Whether to *keep* (not force) alignment of ; stack at 16 (or 32, depending on TARGET_ALIGN_BY_32) bits. mstack-align -Target Report RejectNegative Mask(STACK_ALIGN) Undocumented +Target RejectNegative Mask(STACK_ALIGN) Undocumented mno-stack-align -Target Report RejectNegative InverseMask(STACK_ALIGN) +Target RejectNegative InverseMask(STACK_ALIGN) Do not tune stack alignment. ; TARGET_DATA_ALIGN: Whether to do alignment on individual ; modifiable objects. mdata-align -Target Report RejectNegative Mask(DATA_ALIGN) Undocumented +Target RejectNegative Mask(DATA_ALIGN) Undocumented mno-data-align -Target Report RejectNegative InverseMask(DATA_ALIGN) +Target RejectNegative InverseMask(DATA_ALIGN) Do not tune writable data alignment. ; TARGET_CONST_ALIGN: Whether to do alignment on individual ; non-modifiable objects. mconst-align -Target Report RejectNegative Mask(CONST_ALIGN) Undocumented +Target RejectNegative Mask(CONST_ALIGN) Undocumented mno-const-align -Target Report RejectNegative InverseMask(CONST_ALIGN) +Target RejectNegative InverseMask(CONST_ALIGN) Do not tune code and read-only data alignment. ; See cris_handle_option. m32-bit -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented ; See cris_handle_option. m32bit -Target Report RejectNegative +Target RejectNegative Align code and data to 32 bits. ; See cris_handle_option. m16-bit -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented ; See cris_handle_option. m16bit -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented ; See cris_handle_option. m8-bit -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented ; See cris_handle_option. m8bit -Target Report RejectNegative +Target RejectNegative Don't align items in code or data. ; TARGET_PROLOGUE_EPILOGUE: Whether or not to omit function ; prologue and epilogue. mprologue-epilogue -Target Report RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented +Target RejectNegative Mask(PROLOGUE_EPILOGUE) Undocumented mno-prologue-epilogue -Target Report RejectNegative InverseMask(PROLOGUE_EPILOGUE) +Target RejectNegative InverseMask(PROLOGUE_EPILOGUE) Do not emit function prologue or epilogue. ; We have to handle this m-option here since we can't wash it ; off in both CC1_SPEC and CC1PLUS_SPEC. mbest-lib-options -Target Report RejectNegative +Target RejectNegative Use the most feature-enabling options allowed by other options. ; FIXME: The following comment relates to gcc before cris.opt. @@ -154,37 +154,37 @@ Use the most feature-enabling options allowed by other options. ; gcc.c to forget it, if there's a "later" -mbest-lib-options. ; Kludgy, but needed for some multilibbed files. moverride-best-lib-options -Target Report RejectNegative +Target RejectNegative Override -mbest-lib-options. mcpu= -Target Report RejectNegative Joined Undocumented Var(cris_cpu_str) +Target RejectNegative Joined Undocumented Var(cris_cpu_str) march= -Target Report RejectNegative Joined Var(cris_cpu_str) +Target RejectNegative Joined Var(cris_cpu_str) -march=ARCH Generate code for the specified chip or CPU version. mtune= -Target Report RejectNegative Joined Var(cris_tune_str) +Target RejectNegative Joined Var(cris_tune_str) -mtune=ARCH Tune alignment for the specified chip or CPU version. mmax-stackframe= -Target Report RejectNegative Joined Var(cris_max_stackframe_str) +Target RejectNegative Joined Var(cris_max_stackframe_str) -mmax-stackframe=SIZE Warn when a stackframe is larger than the specified size. max-stackframe= -Target Report RejectNegative Joined Undocumented Var(cris_max_stackframe_str) +Target RejectNegative Joined Undocumented Var(cris_max_stackframe_str) mtrap-using-break8 -Target Report Var(cris_trap_using_break8) Init(2) +Target Var(cris_trap_using_break8) Init(2) Emit traps as \"break 8\", default for CRIS v3 and up. If disabled, calls to abort() are used. mtrap-unaligned-atomic -Target Report Var(cris_trap_unaligned_atomic) Init(2) +Target Var(cris_trap_unaligned_atomic) Init(2) Emit checks causing \"break 8\" instructions to execute when applying atomic builtins on misaligned memory. munaligned-atomic-may-use-library -Target Report Var(cris_atomics_calling_libfunc) Init(2) +Target Var(cris_atomics_calling_libfunc) Init(2) Handle atomic builtins that may be applied to unaligned data by calling library functions. Overrides -mtrap-unaligned-atomic. ; TARGET_SVINTO: Currently this just affects alignment. FIXME: diff --git a/gcc/config/cris/elf.opt b/gcc/config/cris/elf.opt index 103c712..133b524 100644 --- a/gcc/config/cris/elf.opt +++ b/gcc/config/cris/elf.opt @@ -1,6 +1,6 @@ ; ELF-specific options for the CRIS port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. melf -Target Report RejectNegative Undocumented +Target RejectNegative Undocumented sim Driver JoinedOrMissing diff --git a/gcc/config/cris/predicates.md b/gcc/config/cris/predicates.md index 2b55c05..f745052 100644 --- a/gcc/config/cris/predicates.md +++ b/gcc/config/cris/predicates.md @@ -1,5 +1,5 @@ ;; Operand and operator predicates for the GCC CRIS port. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/sync.md b/gcc/config/cris/sync.md index 70640db..8634e7c 100644 --- a/gcc/config/cris/sync.md +++ b/gcc/config/cris/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for CRIS atomic memory sequences. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/t-cris b/gcc/config/cris/t-cris index eb4411e..bab91de 100644 --- a/gcc/config/cris/t-cris +++ b/gcc/config/cris/t-cris @@ -3,7 +3,7 @@ # # The Makefile fragment to include when compiling gcc et al for CRIS. # -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/cris/t-elfmulti b/gcc/config/cris/t-elfmulti index 84eb7a7..fcc5c2f 100644 --- a/gcc/config/cris/t-elfmulti +++ b/gcc/config/cris/t-elfmulti @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md index b9990b7..6067d3d 100644 --- a/gcc/config/csky/constraints.md +++ b/gcc/config/csky/constraints.md @@ -1,5 +1,5 @@ ;; Constraints for C-SKY. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky-elf.h b/gcc/config/csky/csky-elf.h index a79d757..0a3b1f8 100644 --- a/gcc/config/csky/csky-elf.h +++ b/gcc/config/csky/csky-elf.h @@ -1,5 +1,5 @@ /* Declarations for bare-metal C-SKY targets. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky-linux-elf.h b/gcc/config/csky/csky-linux-elf.h index cf587ae..58a1f39 100644 --- a/gcc/config/csky/csky-linux-elf.h +++ b/gcc/config/csky/csky-linux-elf.h @@ -1,5 +1,5 @@ /* Declarations for C-SKY targets running Linux. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky-protos.h b/gcc/config/csky/csky-protos.h index 2c02399..7a2e23e 100644 --- a/gcc/config/csky/csky-protos.h +++ b/gcc/config/csky/csky-protos.h @@ -1,5 +1,5 @@ /* Prototype declarations for the C-SKY back end. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c index 3b03f3f..cdb95fe 100644 --- a/gcc/config/csky/csky.c +++ b/gcc/config/csky/csky.c @@ -1,5 +1,5 @@ /* GCC backend functions for C-SKY targets. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h index 190a668..c7590ab 100644 --- a/gcc/config/csky/csky.h +++ b/gcc/config/csky/csky.h @@ -1,5 +1,5 @@ /* Declarations for the C-SKY back end. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md index 78c9b80..8bb3b2b 100644 --- a/gcc/config/csky/csky.md +++ b/gcc/config/csky/csky.md @@ -1,5 +1,5 @@ ;; Machine description for C-SKY processors. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky.opt b/gcc/config/csky/csky.opt index 505a764..8ddad73 100644 --- a/gcc/config/csky/csky.opt +++ b/gcc/config/csky/csky.opt @@ -1,5 +1,5 @@ ;; Command-line options for the C-SKY back end. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. @@ -27,7 +27,7 @@ config/csky/csky_opts.h ; For backward compatibility only. march=ck803s -Target Report Var(flag_arch_ck803s) Undocumented +Target Var(flag_arch_ck803s) Undocumented march= Target RejectNegative ToLower Joined Enum(csky_arch) Var(csky_arch_option) Save @@ -40,18 +40,18 @@ Specify the target processor. ;; Endianness options. mbig-endian -Target RejectNegative Report Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Generate big-endian code. EB -Target RejectNegative Report Alias(mbig-endian) Undocumented +Target RejectNegative Alias(mbig-endian) Undocumented mlittle-endian -Target RejectNegative Report InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Generate little-endian code. EL -Target RejectNegative Report Alias(mlittle-endian) Undocumented +Target RejectNegative Alias(mlittle-endian) Undocumented ;; Floating point options. These affect code generation but not ;; assembly. @@ -90,11 +90,11 @@ Target RejectNegative Joined Enum(csky_fpu) Var(csky_fpu_index) Init(TARGET_FPU_ Specify the target floating-point hardware/format. mdouble-float -Target Report Var(TARGET_DOUBLE_FLOAT) Init(-1) +Target Var(TARGET_DOUBLE_FLOAT) Init(-1) Generate C-SKY FPU double float instructions (default for hard float). mfdivdu -Target Report Var(TARGET_FDIVDU) Init(-1) +Target Var(TARGET_FDIVDU) Init(-1) Generate frecipd/fsqrtd/fdivd instructions (default for hard float). ;; Instruction set extensions. Most of these don't affect code @@ -102,95 +102,95 @@ Generate frecipd/fsqrtd/fdivd instructions (default for hard float). ;; There are builtin preprocessor defines for each of these. melrw -Target Report Var(TARGET_ELRW) Init(-1) +Target Var(TARGET_ELRW) Init(-1) Enable the extended LRW instruction (default for CK801). mistack -Target Report Mask(ISTACK) +Target Mask(ISTACK) Enable interrupt stack instructions. mmp -Target Report RejectNegative Mask(MP) +Target RejectNegative Mask(MP) Enable multiprocessor instructions. mcp -Target Report RejectNegative Mask(CP) +Target RejectNegative Mask(CP) Enable coprocessor instructions. mcache -Target Report RejectNegative Mask(CACHE) +Target RejectNegative Mask(CACHE) Enable cache prefetch instructions. msecurity -Target Report RejectNegative Mask(SECURITY) +Target RejectNegative Mask(SECURITY) Enable C-SKY SECURE instructions. mmac -Target Report RejectNegative Alias(msecurity) Undocumented +Target RejectNegative Alias(msecurity) Undocumented mtrust -Target Report RejectNegative Mask(TRUST) +Target RejectNegative Mask(TRUST) Enable C-SKY TRUST instructions. mdsp -Target Report RejectNegative Var(TARGET_DSP) +Target RejectNegative Var(TARGET_DSP) Enable C-SKY DSP instructions. medsp -Target Report RejectNegative Mask(EDSP) +Target RejectNegative Mask(EDSP) Enable C-SKY Enhanced DSP instructions. mvdsp -Target Report RejectNegative Mask(VDSP) +Target RejectNegative Mask(VDSP) Enable C-SKY Vector DSP instructions. ;; Code generation options not passed to the assembler. mdiv -Target Report Var(TARGET_DIV) Init(-1) +Target Var(TARGET_DIV) Init(-1) Generate divide instructions. msmart -Target Report Var(TARGET_MINI_REGISTERS) Init(-1) +Target Var(TARGET_MINI_REGISTERS) Init(-1) Generate code for Smart Mode. mhigh-registers -Target Report Var(TARGET_HIGH_REGISTERS) Init(-1) +Target Var(TARGET_HIGH_REGISTERS) Init(-1) Enable use of R16-R31 (default). manchor -Target Report Var(TARGET_ANCHOR) +Target Var(TARGET_ANCHOR) Generate code using global anchor symbol addresses. mpushpop -Target Report Var(TARGET_PUSHPOP) Init(1) +Target Var(TARGET_PUSHPOP) Init(1) Generate push/pop instructions (default). mmultiple-stld -Target Report Var(TARGET_MULTIPLE_STLD) Init(-1) +Target Var(TARGET_MULTIPLE_STLD) Init(-1) Generate stm/ldm instructions (default). mstm -Target Report Alias(mmultiple-stld) Undocumented +Target Alias(mmultiple-stld) Undocumented mconstpool -Target Report Var(TARGET_CONSTANT_POOL) Init(-1) +Target Var(TARGET_CONSTANT_POOL) Init(-1) Generate constant pools in the compiler instead of assembler. mstack-size -Target Report Var(TARGET_STACK_SIZE) Init(0) +Target Var(TARGET_STACK_SIZE) Init(0) Emit .stack_size directives. mccrt -Target Report Var(TARGET_LIBCCRT) Init(0) +Target Var(TARGET_LIBCCRT) Init(0) Generate code for C-SKY compiler runtime instead of libgcc. mbranch-cost= -Target Report Joined RejectNegative UInteger Var(csky_branch_cost) Init(1) +Target Joined RejectNegative UInteger Var(csky_branch_cost) Init(1) Set the branch costs to roughly the specified number of instructions. msched-prolog -Target Report Var(flag_sched_prolog) Init(0) +Target Var(flag_sched_prolog) Init(0) Permit scheduling of function prologue and epilogue sequences. msim diff --git a/gcc/config/csky/csky_cores.def b/gcc/config/csky/csky_cores.def index c18fa79..8309e99 100644 --- a/gcc/config/csky/csky_cores.def +++ b/gcc/config/csky/csky_cores.def @@ -1,5 +1,5 @@ /* Architecture and core descriptions for the C-SKY back end. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky_genopt.sh b/gcc/config/csky/csky_genopt.sh index 7825416..dc6e53f 100644 --- a/gcc/config/csky/csky_genopt.sh +++ b/gcc/config/csky/csky_genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate csky_tables.opt from the lists in *.def. -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # # This file is part of GCC. @@ -23,7 +23,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by csky_genopt.sh from csky_cores.def. -; Copyright (C) 2018-2020 Free Software Foundation, Inc. +; Copyright (C) 2018-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/csky/csky_insn_dsp.md b/gcc/config/csky/csky_insn_dsp.md index 7461115..be12bc2 100644 --- a/gcc/config/csky/csky_insn_dsp.md +++ b/gcc/config/csky/csky_insn_dsp.md @@ -1,5 +1,5 @@ ;; C-SKY DSP instruction descriptions. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_insn_fpu.md b/gcc/config/csky/csky_insn_fpu.md index 700208e..c1e78af 100644 --- a/gcc/config/csky/csky_insn_fpu.md +++ b/gcc/config/csky/csky_insn_fpu.md @@ -1,5 +1,5 @@ ;; C-SKY FPU instruction descriptions. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_isa.def b/gcc/config/csky/csky_isa.def index 42c896a..5edce16 100644 --- a/gcc/config/csky/csky_isa.def +++ b/gcc/config/csky/csky_isa.def @@ -1,5 +1,5 @@ /* ISA feature descriptions for the C-SKY back end. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky_isa.h b/gcc/config/csky/csky_isa.h index 2245a4e..be61c26 100644 --- a/gcc/config/csky/csky_isa.h +++ b/gcc/config/csky/csky_isa.h @@ -1,5 +1,5 @@ /* ISA feature enumerations for C-SKY targets. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky_opts.h b/gcc/config/csky/csky_opts.h index 7ee56be..19d18c9 100644 --- a/gcc/config/csky/csky_opts.h +++ b/gcc/config/csky/csky_opts.h @@ -1,5 +1,5 @@ /* Processor and arch enumerations for C-SKY targets. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by C-SKY Microsystems and Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/csky/csky_pipeline_ck801.md b/gcc/config/csky/csky_pipeline_ck801.md index c6fec4e..f9b3386 100644 --- a/gcc/config/csky/csky_pipeline_ck801.md +++ b/gcc/config/csky/csky_pipeline_ck801.md @@ -1,5 +1,5 @@ ;; Scheduler information for C-SKY CK801 processors. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_pipeline_ck802.md b/gcc/config/csky/csky_pipeline_ck802.md index 5f6db23..bf1c2a7 100644 --- a/gcc/config/csky/csky_pipeline_ck802.md +++ b/gcc/config/csky/csky_pipeline_ck802.md @@ -1,5 +1,5 @@ ;; Instruction scheduling information for C-SKY CK802 processors. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_pipeline_ck803.md b/gcc/config/csky/csky_pipeline_ck803.md index 8357454..40a5ee8 100644 --- a/gcc/config/csky/csky_pipeline_ck803.md +++ b/gcc/config/csky/csky_pipeline_ck803.md @@ -1,5 +1,5 @@ ;; Scheduler information for C-SKY CK803 processors. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_pipeline_ck810.md b/gcc/config/csky/csky_pipeline_ck810.md index 416bda9..e43260b 100644 --- a/gcc/config/csky/csky_pipeline_ck810.md +++ b/gcc/config/csky/csky_pipeline_ck810.md @@ -1,5 +1,5 @@ ;; Instruction scheduling information for C-SKY CK810 processors. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/csky_tables.opt b/gcc/config/csky/csky_tables.opt index f7202b2..3501f90 100644 --- a/gcc/config/csky/csky_tables.opt +++ b/gcc/config/csky/csky_tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by csky_genopt.sh from csky_cores.def. -; Copyright (C) 2018-2020 Free Software Foundation, Inc. +; Copyright (C) 2018-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md index dfccfd3..4ffecb0 100644 --- a/gcc/config/csky/predicates.md +++ b/gcc/config/csky/predicates.md @@ -1,5 +1,5 @@ ;; Predicates for C-SKY. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by C-SKY Microsystems and Mentor Graphics. ;; ;; This file is part of GCC. diff --git a/gcc/config/csky/print-sysroot-suffix.sh b/gcc/config/csky/print-sysroot-suffix.sh index 04db7e7..4840bc6 100644 --- a/gcc/config/csky/print-sysroot-suffix.sh +++ b/gcc/config/csky/print-sysroot-suffix.sh @@ -2,7 +2,7 @@ # Script to generate SYSROOT_SUFFIX_SPEC equivalent to MULTILIB_OSDIRNAMES # Arguments are MULTILIB_OSDIRNAMES, MULTILIB_OPTIONS and MULTILIB_MATCHES. -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # This file is part of GCC. diff --git a/gcc/config/csky/t-csky b/gcc/config/csky/t-csky index ab38fd6..2c9ae9d 100644 --- a/gcc/config/csky/t-csky +++ b/gcc/config/csky/t-csky @@ -1,6 +1,6 @@ # Make rules for all C-SKY targets. # -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # # This file is part of GCC. diff --git a/gcc/config/csky/t-csky-elf b/gcc/config/csky/t-csky-elf index 62a2d83..bbdf286 100644 --- a/gcc/config/csky/t-csky-elf +++ b/gcc/config/csky/t-csky-elf @@ -1,6 +1,6 @@ # Multilib configuration for csky*-elf. # -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # # This file is part of GCC. diff --git a/gcc/config/csky/t-csky-linux b/gcc/config/csky/t-csky-linux index f4d656a..9435b7a 100644 --- a/gcc/config/csky/t-csky-linux +++ b/gcc/config/csky/t-csky-linux @@ -1,6 +1,6 @@ # Multilib configuration for csky*-linux-*. # -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # # This file is part of GCC. diff --git a/gcc/config/csky/t-sysroot-suffix b/gcc/config/csky/t-sysroot-suffix index 04bf8dd..d891f69 100644 --- a/gcc/config/csky/t-sysroot-suffix +++ b/gcc/config/csky/t-sysroot-suffix @@ -1,6 +1,6 @@ # Makefile fragment for C-SKY sysroot suffix. # -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by C-SKY Microsystems and Mentor Graphics. # # This file is part of GCC. diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index 9617230..b0424a9 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -1,5 +1,5 @@ /* Darwin support needed only by C/C++ frontends. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/darwin-d.c b/gcc/config/darwin-d.c index ced07ce..afc32da 100644 --- a/gcc/config/darwin-d.c +++ b/gcc/config/darwin-d.c @@ -1,5 +1,5 @@ /* Darwin support needed only by D front-end. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 8ae3000..3d7768f 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -1,5 +1,5 @@ /* Additional functions for the GCC driver on Darwin native. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -43,13 +43,13 @@ static const char * validate_macosx_version_min (const char *version_str) { size_t version_len; - unsigned long major, minor, tiny = 0; + unsigned long major, minor = 0, tiny = 0; char *end; const char *old_version = version_str; bool need_rewrite = false; version_len = strlen (version_str); - if (version_len < 4) /* The minimum would be 10.x */ + if (version_len < 2) /* The minimum would be 11 */ return NULL; /* Version string must consist of digits and periods only. */ @@ -63,18 +63,27 @@ validate_macosx_version_min (const char *version_str) need_rewrite = true; major = strtoul (version_str, &end, 10); - version_str = end + ((*end == '.') ? 1 : 0); if (major < 10 || major > 11 ) /* MacOS 10 and 11 are known. */ return NULL; - /* Version string components must be present and numeric. */ - if (!ISDIGIT (version_str[0])) + /* Skip a separating period, if there's one. */ + version_str = end + ((*end == '.') ? 1 : 0); + + if (major == 11 && *end != '\0' && !ISDIGIT (version_str[0])) + /* For MacOS 11, we allow just the major number, but if the minor is + there it must be numeric. */ + return NULL; + else if (major == 11 && *end == '\0') + /* We will rewrite 11 => 11.0.0. */ + need_rewrite = true; + else if (major == 10 && (*end == '\0' || !ISDIGIT (version_str[0]))) + /* Otherwise, minor version components must be present and numeric. */ return NULL; /* If we have one or more leading zeros on a component, then rewrite the version string. */ - if (version_str[0] == '0' && version_str[1] != '\0' + if (*end != '\0' && version_str[0] == '0' && version_str[1] != '\0' && version_str[1] != '.') need_rewrite = true; @@ -149,9 +158,22 @@ darwin_find_version_from_kernel (void) if (*version_p++ != '.') goto parse_failed; - /* Darwin20 sees a transition to macOS 11. */ + /* Darwin20 sees a transition to macOS 11. In this, it seems that the + mapping to macOS minor version is now shifted to the kernel minor + version - 1 (at least for the initial releases). At this stage, we + don't know what macOS version will correspond to Darwin21. */ if (major_vers >= 20) - asprintf (&new_flag, "11.%02d.00", major_vers - 20); + { + int minor_vers = *version_p++ - '0'; + if (ISDIGIT (*version_p)) + minor_vers = minor_vers * 10 + (*version_p++ - '0'); + if (*version_p++ != '.') + goto parse_failed; + if (minor_vers > 0) + minor_vers -= 1; /* Kernel 20.3 => macOS 11.2. */ + /* It's not yet clear whether patch level will be considered. */ + asprintf (&new_flag, "11.%02d.00", minor_vers); + } else if (major_vers - 4 <= 4) /* On 10.4 and earlier, the old linker is used which does not support three-component system versions. @@ -207,7 +229,7 @@ darwin_default_min_version (void) const char *checked = validate_macosx_version_min (new_flag); if (checked == NULL) { - warning (0, "couldn%'t understand version %s", new_flag); + warning (0, "could not understand version %s", new_flag); return NULL; } new_flag = xstrndup (checked, strlen (checked)); diff --git a/gcc/config/darwin-f.c b/gcc/config/darwin-f.c index 0168665..1330cdc 100644 --- a/gcc/config/darwin-f.c +++ b/gcc/config/darwin-f.c @@ -1,5 +1,5 @@ /* Darwin support needed only by Fortran frontends. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Daniel Franke. This file is part of GCC. diff --git a/gcc/config/darwin-ppc-ldouble-patch.def b/gcc/config/darwin-ppc-ldouble-patch.def index 7120382..1feda53 100644 --- a/gcc/config/darwin-ppc-ldouble-patch.def +++ b/gcc/config/darwin-ppc-ldouble-patch.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h index 3f222c3..2120eb6 100644 --- a/gcc/config/darwin-protos.h +++ b/gcc/config/darwin-protos.h @@ -1,5 +1,5 @@ /* Prototypes. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin-sections.def b/gcc/config/darwin-sections.def index 65bf5ad..8be8962 100644 --- a/gcc/config/darwin-sections.def +++ b/gcc/config/darwin-sections.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2020 Free Software Foundation, Inc. +/* Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 3265e3e..119f319 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -1,5 +1,5 @@ /* Functions for generic Darwin as target machine for GNU C compiler. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index da40a08..5a9fb43f 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -230,6 +230,7 @@ extern GTY(()) int darwin_ms_struct; %{%:sanitize(address): -lasan } \ %{%:sanitize(undefined): -lubsan } \ %(link_ssp) \ + %:version-compare(>< 10.6 10.7 mmacosx-version-min= -ld10-uwfef.o) \ %(link_gcc_c_sequence) \ }}}\ %{!nostdlib:%{!r:%{!nostartfiles:%E}}} %{T*} %{F*} "\ @@ -241,22 +242,32 @@ extern GTY(()) int darwin_ms_struct; #define DSYMUTIL "\ndsymutil" +/* Spec that controls whether the debug linker is run automatically for + a link step. This needs to be done if there is a source file on the + command line which will result in a temporary object (and debug is + enabled). */ + #define DSYMUTIL_SPEC \ "%{!fdump=*:%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ %{v} \ - %{gdwarf-2:%{!gstabs*:%{%:debug-level-gt(0): -idsym}}}\ - %{.c|.cc|.C|.cpp|.cp|.c++|.cxx|.CPP|.m|.mm: \ - %{gdwarf-2:%{!gstabs*:%{%:debug-level-gt(0): -dsym}}}}}}}}}}}" + %{g*:%{!gstabs*:%{%:debug-level-gt(0): -idsym}}}\ + %{.c|.cc|.C|.cpp|.cp|.c++|.cxx|.CPP|.m|.mm|.s|.f|.f90|\ + .f95|.f03|.f77|.for|.F|.F90|.F95|.F03: \ + %{g*:%{!gstabs*:%{%:debug-level-gt(0): -dsym}}}}}}}}}}}" #define LINK_COMMAND_SPEC LINK_COMMAND_SPEC_A DSYMUTIL_SPEC /* Tell collect2 to run dsymutil for us as necessary. */ #define COLLECT_RUN_DSYMUTIL 1 -/* We only want one instance of %G, since libSystem (Darwin's -lc) does not depend - on libgcc. */ +/* Fix PR47558 by linking against libSystem ahead of libgcc. See also + PR 80556 and the fallout from this. */ + #undef LINK_GCC_C_SEQUENCE_SPEC -#define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L}" +#define LINK_GCC_C_SEQUENCE_SPEC \ +"%{!static:%{!static-libgcc: \ + %:version-compare(>= 10.6 mmacosx-version-min= -lSystem) } } \ + %G %{!nolibc:%L}" /* ld64 supports a sysroot, it just has a different name and there's no easy way to check for it at config time. */ @@ -472,22 +483,31 @@ extern GTY(()) int darwin_ms_struct; %{Zforce_cpusubtype_ALL:-force_cpusubtype_ALL} \ %{static}" ASM_MMACOSX_VERSION_MIN_SPEC -/* Default ASM_DEBUG_SPEC. Darwin's as cannot currently produce dwarf - debugging data. */ - +#ifdef HAVE_AS_STABS_DIRECTIVE +/* We only pass a debug option to the assembler if that supports stabs, since + dwarf is not uniformly supported in the assemblers. */ #define ASM_DEBUG_SPEC "%{g*:%{%:debug-level-gt(0):%{!gdwarf*:--gstabs}}}" -#define ASM_DEBUG_OPTION_SPEC "" +#else +#define ASM_DEBUG_SPEC "" +#endif + +#undef ASM_DEBUG_OPTION_SPEC +#define ASM_DEBUG_OPTION_SPEC "" + #define ASM_FINAL_SPEC \ "%{gsplit-dwarf:%ngsplit-dwarf is not supported on this platform} %<gsplit-dwarf" -/* We still allow output of STABS if the assembler supports it. */ +/* We now require C++11 to bootstrap and newer tools than those based on + stabs, so require DWARF-2, even if stabs is supported by the assembler. */ + +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +#define DARWIN_PREFER_DWARF +#define DWARF2_DEBUGGING_INFO 1 + #ifdef HAVE_AS_STABS_DIRECTIVE #define DBX_DEBUGGING_INFO 1 -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #endif -#define DWARF2_DEBUGGING_INFO 1 - #define DEBUG_FRAME_SECTION "__DWARF,__debug_frame,regular,debug" #define DEBUG_INFO_SECTION "__DWARF,__debug_info,regular,debug" #define DEBUG_ABBREV_SECTION "__DWARF,__debug_abbrev,regular,debug" @@ -1060,6 +1080,9 @@ extern void darwin_driver_init (unsigned int *,struct cl_decoded_option **); #undef SUPPORTS_INIT_PRIORITY #define SUPPORTS_INIT_PRIORITY 0 +#undef STACK_CHECK_STATIC_BUILTIN +#define STACK_CHECK_STATIC_BUILTIN 1 + /* When building cross-compilers (and native crosses) we shall default to providing an osx-version-min of this unless overridden by the User. 10.5 is the only version that fully supports all our archs so that's the @@ -1071,16 +1094,20 @@ extern void darwin_driver_init (unsigned int *,struct cl_decoded_option **); /* Later versions of ld64 support coalescing weak code/data without requiring that they be placed in specially identified sections. This is the earliest _tested_ version known to support this so far. */ -#define MIN_LD64_NO_COAL_SECTS "236.4" +#define MIN_LD64_NO_COAL_SECTS "236.3" /* From at least version 62.1, ld64 can build symbol indirection stubs as needed, and there is no need for the compiler to emit them. */ #define MIN_LD64_OMIT_STUBS "62.1" +/* If we have no definition for the linker version, pick the minimum version + that will bootstrap the compiler. */ #ifndef LD64_VERSION -#define LD64_VERSION "62.1" -#else -#define DEF_LD64 LD64_VERSION +# ifndef DEF_LD64 +# define LD64_VERSION "85.2.1" +# else +# define LD64_VERSION DEF_LD64 +# endif #endif #endif /* CONFIG_DARWIN_H */ diff --git a/gcc/config/darwin.opt b/gcc/config/darwin.opt index 5b75536..23f3593 100644 --- a/gcc/config/darwin.opt +++ b/gcc/config/darwin.opt @@ -1,6 +1,6 @@ ; Processor-independent options for Darwin. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -30,7 +30,7 @@ dependency-file C ObjC C++ ObjC++ Separate Alias(MF) MissingArgError(missing filename after %qs) fapple-kext -Target Report C++ Var(flag_apple_kext) +Target C++ Var(flag_apple_kext) Generate code for darwin loadable kernel extensions. iframework @@ -38,28 +38,28 @@ Target RejectNegative C ObjC C++ ObjC++ Joined Separate -iframework <dir> Add <dir> to the end of the system framework include path. mconstant-cfstrings -Target Report Var(darwin_constant_cfstrings) Init(1) +Target Var(darwin_constant_cfstrings) Init(1) Generate compile-time CFString objects. Wnonportable-cfstrings -Target Report Var(darwin_warn_nonportable_cfstrings) Init(1) Warning +Target Var(darwin_warn_nonportable_cfstrings) Init(1) Warning Warn if constant CFString objects contain non-portable characters. ; Use new-style pic stubs if this is true, x86 only so far. matt-stubs -Target Report Var(darwin_macho_att_stub) Init(1) +Target Var(darwin_macho_att_stub) Init(1) Generate AT&T-style stubs for Mach-O. mdynamic-no-pic -Target Common Report Mask(MACHO_DYNAMIC_NO_PIC) +Target Common Mask(MACHO_DYNAMIC_NO_PIC) Generate code suitable for executables (NOT shared libs). mfix-and-continue -Target Report Var(darwin_fix_and_continue) +Target Var(darwin_fix_and_continue) Generate code suitable for fast turn around debugging. mkernel -Target Report Var(flag_mkernel) +Target Var(flag_mkernel) Generate code for the kernel or loadable kernel extensions. ; The Init here is for the convenience of GCC developers, so that cc1 @@ -67,24 +67,24 @@ Generate code for the kernel or loadable kernel extensions. ; driver will always pass a -mmacosx-version-min, so in normal use the ; Init is never used. mmacosx-version-min= -Target RejectNegative Joined Report Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION) +Target RejectNegative Joined Var(darwin_macosx_version_min) Init(DEF_MIN_OSX_VERSION) The earliest macOS version on which this program will run. ; Really, only relevant to PowerPC which has a 4 byte bool by default. mone-byte-bool -Target RejectNegative Report Var(darwin_one_byte_bool) +Target RejectNegative Var(darwin_one_byte_bool) Set sizeof(bool) to 1. msymbol-stubs -Target Report Var(darwin_symbol_stubs) Init(0) +Target Var(darwin_symbol_stubs) Init(0) Force generation of external symbol indirection stubs. ; Some code-gen may be improved / adjusted if the linker is sufficiently modern. mtarget-linker= -Target RejectNegative Joined Report Alias(mtarget-linker) +Target RejectNegative Joined Alias(mtarget-linker) mtarget-linker -Target RejectNegative Joined Separate Report Var(darwin_target_linker) Init(LD64_VERSION) +Target RejectNegative Joined Separate Var(darwin_target_linker) Init(LD64_VERSION) -mtarget-linker <version> Specify that ld64 <version> is the toolchain linker for the current invocation. ; Driver options. diff --git a/gcc/config/darwin10.h b/gcc/config/darwin10.h deleted file mode 100644 index d1a33a3..0000000 --- a/gcc/config/darwin10.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2009-2020 Free Software Foundation, Inc. - Contributed by Jack Howarth <howarth@bromo.med.uc.edu>. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -/* Fix PR47558 by linking against libSystem ahead of libgcc_ext. */ - -#undef LINK_GCC_C_SEQUENCE_SPEC -#define LINK_GCC_C_SEQUENCE_SPEC \ -"%{!static:%{!static-libgcc: \ - %:version-compare(>= 10.6 mmacosx-version-min= -lSystem) } } \ - %{!nostdlib:%:version-compare(>< 10.6 10.7 mmacosx-version-min= -ld10-uwfef.o)} \ - %G %{!nolibc:%L}" - -#undef DEF_MIN_OSX_VERSION -#define DEF_MIN_OSX_VERSION "10.6" - -#ifndef LD64_VERSION -#undef DEF_LD64 -#define DEF_LD64 "97.7" -#endif diff --git a/gcc/config/darwin12.h b/gcc/config/darwin12.h deleted file mode 100644 index b397703..0000000 --- a/gcc/config/darwin12.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2009-2020 Free Software Foundation, Inc. - Contributed by Jack Howarth <howarth.at.gcc@gmail.com>. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#undef DEF_MIN_OSX_VERSION -#define DEF_MIN_OSX_VERSION "10.8" - -#ifndef LD64_VERSION -#undef DEF_LD64 -#define DEF_LD64 "236.4" -#endif diff --git a/gcc/config/darwin9.h b/gcc/config/darwin9.h deleted file mode 100644 index 787aca7..0000000 --- a/gcc/config/darwin9.h +++ /dev/null @@ -1,62 +0,0 @@ -/* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2006-2020 Free Software Foundation, Inc. - Contributed by Apple Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -/* Prefer DWARF2. */ -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -#define DARWIN_PREFER_DWARF - -/* Since DWARF2 is default, conditions for running dsymutil are different. */ -#undef DSYMUTIL_SPEC -#define DSYMUTIL_SPEC \ - "%{!fdump=*:%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ - %{v} \ - %{g*:%{!gstabs*:%{%:debug-level-gt(0): -idsym}}}\ - %{.c|.cc|.C|.cpp|.cp|.c++|.cxx|.CPP|.m|.mm|.s|.f|.f90|.f95|.f03|.f77|.for|.F|.F90|.F95|.F03: \ - %{g*:%{!gstabs*:%{%:debug-level-gt(0): -dsym}}}}}}}}}}}" - -/* Tell collect2 to run dsymutil for us as necessary. */ -#define COLLECT_RUN_DSYMUTIL 1 - -/* Only ask as for debug data if the debug style is stabs (since as doesn't - yet generate dwarf.) */ - -#undef ASM_DEBUG_SPEC -#define ASM_DEBUG_SPEC "%{g*:%{%:debug-level-gt(0):%{gstabs:--gstabs}}}" - -#undef ASM_DEBUG_OPTION_SPEC -#define ASM_DEBUG_OPTION_SPEC "" - -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ - do { \ - unsigned HOST_WIDE_INT _new_size = (SIZE); \ - fprintf ((FILE), "\t.comm "); \ - assemble_name ((FILE), (NAME)); \ - if (_new_size == 0) _new_size = 1; \ - fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ - _new_size, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \ - } while (0) - -#undef DEF_MIN_OSX_VERSION -#define DEF_MIN_OSX_VERSION "10.5" - -#undef STACK_CHECK_STATIC_BUILTIN -#define STACK_CHECK_STATIC_BUILTIN 1 diff --git a/gcc/config/dbx.h b/gcc/config/dbx.h index 739d67b..b270a07 100644 --- a/gcc/config/dbx.h +++ b/gcc/config/dbx.h @@ -1,5 +1,5 @@ /* Prefer DBX (stabs) debugging information. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/dbxcoff.h b/gcc/config/dbxcoff.h index dbe9f67..d491cff 100644 --- a/gcc/config/dbxcoff.h +++ b/gcc/config/dbxcoff.h @@ -1,5 +1,5 @@ /* Definitions needed when using stabs embedded in COFF sections. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/dbxelf.h b/gcc/config/dbxelf.h index e555994..161f872 100644 --- a/gcc/config/dbxelf.h +++ b/gcc/config/dbxelf.h @@ -1,5 +1,5 @@ /* Definitions needed when using stabs embedded in ELF sections. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/default-c.c b/gcc/config/default-c.c index c29b0cc..dd34fbf 100644 --- a/gcc/config/default-c.c +++ b/gcc/config/default-c.c @@ -1,5 +1,5 @@ /* Default C-family target hooks initializer. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/default-d.c b/gcc/config/default-d.c index ea831d0..522f192 100644 --- a/gcc/config/default-d.c +++ b/gcc/config/default-d.c @@ -1,5 +1,5 @@ /* Default D language target hooks initializer. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/dragonfly-d.c b/gcc/config/dragonfly-d.c index 70ec820..76f4cc0 100644 --- a/gcc/config/dragonfly-d.c +++ b/gcc/config/dragonfly-d.c @@ -1,5 +1,5 @@ /* DragonFly support needed only by D front-end. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/dragonfly-stdint.h b/gcc/config/dragonfly-stdint.h index 3b313e6..cf771b4 100644 --- a/gcc/config/dragonfly-stdint.h +++ b/gcc/config/dragonfly-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types for DragonFly systems. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/dragonfly.h b/gcc/config/dragonfly.h index 01f6908..b60e67e 100644 --- a/gcc/config/dragonfly.h +++ b/gcc/config/dragonfly.h @@ -1,5 +1,5 @@ /* Base configuration file for all DragonFly targets. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/dragonfly.opt b/gcc/config/dragonfly.opt index 3c5f630..01b06d5 100644 --- a/gcc/config/dragonfly.opt +++ b/gcc/config/dragonfly.opt @@ -1,6 +1,6 @@ ; DragonFly BSD options. -; Copyright (C) 2014-2020 Free Software Foundation, Inc. +; Copyright (C) 2014-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h index d8f169f..7a736cc 100644 --- a/gcc/config/elfos.h +++ b/gcc/config/elfos.h @@ -1,6 +1,6 @@ /* elfos.h -- operating system specific defines to be used when targeting GCC for some generic ELF system - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Based on svr4.h contributed by Ron Guilmette (rfg@netcom.com). This file is part of GCC. diff --git a/gcc/config/epiphany/constraints.md b/gcc/config/epiphany/constraints.md index bb0317c..0bf5f0d 100644 --- a/gcc/config/epiphany/constraints.md +++ b/gcc/config/epiphany/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Adaptiva epiphany -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-modes.def b/gcc/config/epiphany/epiphany-modes.def index 4fc4682..d322b3f 100644 --- a/gcc/config/epiphany/epiphany-modes.def +++ b/gcc/config/epiphany/epiphany-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Adapteva Epiphany cpu. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-protos.h b/gcc/config/epiphany/epiphany-protos.h index 1d05b09..2ccc3f5 100644 --- a/gcc/config/epiphany/epiphany-protos.h +++ b/gcc/config/epiphany/epiphany-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, EPIPHANY cpu. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-sched.md b/gcc/config/epiphany/epiphany-sched.md index df83cb8..6f549ca 100644 --- a/gcc/config/epiphany/epiphany-sched.md +++ b/gcc/config/epiphany/epiphany-sched.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for EPIPHANY -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index 818bbf0..b60daa7 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the EPIPHANY cpu. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h index 676fc63..e94df63 100644 --- a/gcc/config/epiphany/epiphany.h +++ b/gcc/config/epiphany/epiphany.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Argonaut EPIPHANY cpu. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md index c18d74d..9e621cd 100644 --- a/gcc/config/epiphany/epiphany.md +++ b/gcc/config/epiphany/epiphany.md @@ -1,5 +1,5 @@ ;; Machine description of the Adaptiva epiphany cpu for GNU C compiler -;; Copyright (C) 1994-2020 Free Software Foundation, Inc. +;; Copyright (C) 1994-2021 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.opt b/gcc/config/epiphany/epiphany.opt index dd194a6..c63bf3e 100644 --- a/gcc/config/epiphany/epiphany.opt +++ b/gcc/config/epiphany/epiphany.opt @@ -1,6 +1,6 @@ ; Options for the Adapteva EPIPHANY port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Embecosm on behalf of Adapteva, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany_intrinsics.h b/gcc/config/epiphany/epiphany_intrinsics.h index 0cdd3c6..e64bb21 100644 --- a/gcc/config/epiphany/epiphany_intrinsics.h +++ b/gcc/config/epiphany/epiphany_intrinsics.h @@ -1,5 +1,5 @@ /* Epiphany intrinsic functions - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/mode-switch-use.c b/gcc/config/epiphany/mode-switch-use.c index 1591e19..4b44513 100644 --- a/gcc/config/epiphany/mode-switch-use.c +++ b/gcc/config/epiphany/mode-switch-use.c @@ -1,6 +1,6 @@ /* Insert USEs in instructions that require mode switching. This should probably be merged into mode-switching.c . - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md index a7d7cbb..684ff52 100644 --- a/gcc/config/epiphany/predicates.md +++ b/gcc/config/epiphany/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for code generation on the EPIPHANY cpu. -;; Copyright (C) 1994-2020 Free Software Foundation, Inc. +;; Copyright (C) 1994-2021 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/epiphany/resolve-sw-modes.c b/gcc/config/epiphany/resolve-sw-modes.c index 398efc5..64061d2 100644 --- a/gcc/config/epiphany/resolve-sw-modes.c +++ b/gcc/config/epiphany/resolve-sw-modes.c @@ -1,5 +1,5 @@ /* Mode switching cleanup pass for the EPIPHANY cpu. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/rtems.h b/gcc/config/epiphany/rtems.h index b317de1..76006ca 100644 --- a/gcc/config/epiphany/rtems.h +++ b/gcc/config/epiphany/rtems.h @@ -1,5 +1,5 @@ /* Definitions for RTEMS based EPIPHANY systems. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/t-epiphany b/gcc/config/epiphany/t-epiphany index 900a49e..6db9e84 100644 --- a/gcc/config/epiphany/t-epiphany +++ b/gcc/config/epiphany/t-epiphany @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2020 Free Software Foundation, Inc. +# Copyright (C) 1997-2021 Free Software Foundation, Inc. # Contributed by Embecosm on behalf of Adapteva, Inc. # # This file is part of GCC. diff --git a/gcc/config/flat.h b/gcc/config/flat.h index 2d00df7..1880236 100644 --- a/gcc/config/flat.h +++ b/gcc/config/flat.h @@ -1,5 +1,5 @@ /* Defines to be used for targets that support flat executables. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/fr30/constraints.md b/gcc/config/fr30/constraints.md index eaa153a..96ab5e9 100644 --- a/gcc/config/fr30/constraints.md +++ b/gcc/config/fr30/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the FR30. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/fr30/fr30-protos.h b/gcc/config/fr30/fr30-protos.h index a16e139..8f1482e 100644 --- a/gcc/config/fr30/fr30-protos.h +++ b/gcc/config/fr30/fr30-protos.h @@ -1,5 +1,5 @@ /* Prototypes for fr30.c functions used in the md file & elsewhere. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index ffbb921..b1814a5 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -1,5 +1,5 @@ /* FR30 specific functions. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index 5d725b0..e6f560a 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -1,7 +1,7 @@ /*{{{ Comment. */ /* Definitions of FR30 target. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index 23b3e5b..d1733d0 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -1,5 +1,5 @@ ;; FR30 machine description. -;; Copyright (C) 1998-2020 Free Software Foundation, Inc. +;; Copyright (C) 1998-2021 Free Software Foundation, Inc. ;; Contributed by Cygnus Solutions. ;; This file is part of GCC. diff --git a/gcc/config/fr30/fr30.opt b/gcc/config/fr30/fr30.opt index 0a65cc4..cf0402e 100644 --- a/gcc/config/fr30/fr30.opt +++ b/gcc/config/fr30/fr30.opt @@ -1,6 +1,6 @@ ; Options for the FR30 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. msmall-model -Target Report Mask(SMALL_MODEL) +Target Mask(SMALL_MODEL) Assume small address space. mno-lsim diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md index 3e02253..b64ba7c 100644 --- a/gcc/config/fr30/predicates.md +++ b/gcc/config/fr30/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for FR30. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/freebsd-d.c b/gcc/config/freebsd-d.c index d79d82b..425ca83 100644 --- a/gcc/config/freebsd-d.c +++ b/gcc/config/freebsd-d.c @@ -1,5 +1,5 @@ /* FreeBSD support needed only by D front-end. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/freebsd-nthr.h b/gcc/config/freebsd-nthr.h index 78e6302..0164569 100644 --- a/gcc/config/freebsd-nthr.h +++ b/gcc/config/freebsd-nthr.h @@ -1,5 +1,5 @@ /* FreeBSD configuration setting for FreeBSD systems. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Loren J. Rittle <ljrittle@acm.org> This file is part of GCC. diff --git a/gcc/config/freebsd-spec.h b/gcc/config/freebsd-spec.h index 6003647..2b49261 100644 --- a/gcc/config/freebsd-spec.h +++ b/gcc/config/freebsd-spec.h @@ -1,5 +1,5 @@ /* Base configuration file for all FreeBSD targets. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/freebsd-stdint.h b/gcc/config/freebsd-stdint.h index 6778754..f0c5515 100644 --- a/gcc/config/freebsd-stdint.h +++ b/gcc/config/freebsd-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types for FreeBSD systems. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Gerald Pfeifer <gerald@pfeifer.com>. This file is part of GCC. diff --git a/gcc/config/freebsd.h b/gcc/config/freebsd.h index 4b5140b..f6f267b 100644 --- a/gcc/config/freebsd.h +++ b/gcc/config/freebsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all FreeBSD targets. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/freebsd.opt b/gcc/config/freebsd.opt index 45e0f4a..eed8224 100644 --- a/gcc/config/freebsd.opt +++ b/gcc/config/freebsd.opt @@ -1,6 +1,6 @@ ; FreeBSD options. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/frv/constraints.md b/gcc/config/frv/constraints.md index af32431..382ec97 100644 --- a/gcc/config/frv/constraints.md +++ b/gcc/config/frv/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for FRV. -;; Copyright (C) 2001-2020 Free Software Foundation, Inc. +;; Copyright (C) 2001-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/frv/frv-asm.h b/gcc/config/frv/frv-asm.h index 29fdbd7..cf7fa7c 100644 --- a/gcc/config/frv/frv-asm.h +++ b/gcc/config/frv/frv-asm.h @@ -1,5 +1,5 @@ /* Assembler Support. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-modes.def b/gcc/config/frv/frv-modes.def index 45a6272..47c62a1 100644 --- a/gcc/config/frv/frv-modes.def +++ b/gcc/config/frv/frv-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for FRV. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-opts.h b/gcc/config/frv/frv-opts.h index eb8ebd2..389565c 100644 --- a/gcc/config/frv/frv-opts.h +++ b/gcc/config/frv/frv-opts.h @@ -1,5 +1,5 @@ /* Frv option-handling defitions. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-protos.h b/gcc/config/frv/frv-protos.h index 8d61359..8d79d73 100644 --- a/gcc/config/frv/frv-protos.h +++ b/gcc/config/frv/frv-protos.h @@ -1,5 +1,5 @@ /* Frv prototypes. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 125346d..8201a20 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1997-2020 Free Software Foundation, Inc. +/* Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 450b22e..6509195 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -1,5 +1,5 @@ /* Target macros for the FRV port of GCC. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md index 896993d..a2aa1b2 100644 --- a/gcc/config/frv/frv.md +++ b/gcc/config/frv/frv.md @@ -1,5 +1,5 @@ ;; Frv Machine Description -;; Copyright (C) 1999-2020 Free Software Foundation, Inc. +;; Copyright (C) 1999-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat, Inc. ;; This file is part of GCC. diff --git a/gcc/config/frv/frv.opt b/gcc/config/frv/frv.opt index 4b4fe70..506af29 100644 --- a/gcc/config/frv/frv.opt +++ b/gcc/config/frv/frv.opt @@ -1,6 +1,6 @@ ; Options for the FR-V port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -26,19 +26,19 @@ Variable frv_cpu_t frv_cpu_type = CPU_TYPE macc-4 -Target Report RejectNegative Mask(ACC_4) +Target RejectNegative Mask(ACC_4) Use 4 media accumulators. macc-8 -Target Report RejectNegative InverseMask(ACC_4, ACC_8) +Target RejectNegative InverseMask(ACC_4, ACC_8) Use 8 media accumulators. malign-labels -Target Report Mask(ALIGN_LABELS) +Target Mask(ALIGN_LABELS) Enable label alignment optimizations. malloc-cc -Target Report RejectNegative Mask(ALLOC_CC) +Target RejectNegative Mask(ALLOC_CC) Dynamically allocate cc registers. ; We used to default the branch cost to 2, but it was changed it to 1 to avoid @@ -49,7 +49,7 @@ Target RejectNegative Joined UInteger Var(frv_branch_cost_int) Init(1) Set the cost of branches. mcond-exec -Target Report Mask(COND_EXEC) +Target Mask(COND_EXEC) Enable conditional execution other than moves/scc. mcond-exec-insns= @@ -61,7 +61,7 @@ Target RejectNegative Joined UInteger Var(frv_condexec_temps) Init(4) Change the number of temporary registers that are available to conditionally-executed sequences. mcond-move -Target Report Mask(COND_MOVE) +Target Mask(COND_MOVE) Enable conditional moves. mcpu= @@ -118,75 +118,75 @@ mdebug-stack Target Undocumented Var(TARGET_DEBUG_STACK) mdouble -Target Report Mask(DOUBLE) +Target Mask(DOUBLE) Use fp double instructions. mdword -Target Report Mask(DWORD) +Target Mask(DWORD) Change the ABI to allow double word insns. mfdpic -Target Report Mask(FDPIC) +Target Mask(FDPIC) Enable Function Descriptor PIC mode. mfixed-cc -Target Report RejectNegative InverseMask(ALLOC_CC, FIXED_CC) +Target RejectNegative InverseMask(ALLOC_CC, FIXED_CC) Just use icc0/fcc0. mfpr-32 -Target Report RejectNegative Mask(FPR_32) +Target RejectNegative Mask(FPR_32) Only use 32 FPRs. mfpr-64 -Target Report RejectNegative InverseMask(FPR_32, FPR_64) +Target RejectNegative InverseMask(FPR_32, FPR_64) Use 64 FPRs. mgpr-32 -Target Report RejectNegative Mask(GPR_32) +Target RejectNegative Mask(GPR_32) Only use 32 GPRs. mgpr-64 -Target Report RejectNegative InverseMask(GPR_32, GPR_64) +Target RejectNegative InverseMask(GPR_32, GPR_64) Use 64 GPRs. mgprel-ro -Target Report Mask(GPREL_RO) +Target Mask(GPREL_RO) Enable use of GPREL for read-only data in FDPIC. mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Use hardware floating point. minline-plt -Target Report Mask(INLINE_PLT) +Target Mask(INLINE_PLT) Enable inlining of PLT in function calls. mlibrary-pic -Target Report Mask(LIBPIC) +Target Mask(LIBPIC) Enable PIC support for building libraries. mlinked-fp -Target Report Mask(LINKED_FP) +Target Mask(LINKED_FP) Follow the EABI linkage requirements. mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Disallow direct calls to global functions. mmedia -Target Report Mask(MEDIA) +Target Mask(MEDIA) Use media instructions. mmuladd -Target Report Mask(MULADD) +Target Mask(MULADD) Use multiply add/subtract instructions. mmulti-cond-exec -Target Report Mask(MULTI_CE) +Target Mask(MULTI_CE) Enable optimizing &&/|| in conditional execution. mnested-cond-exec -Target Report Mask(NESTED_CE) +Target Mask(NESTED_CE) Enable nested conditional execution optimizations. ; Not used by the compiler proper. @@ -195,15 +195,15 @@ Target RejectNegative Do not mark ABI switches in e_flags. moptimize-membar -Target Report Mask(OPTIMIZE_MEMBAR) +Target Mask(OPTIMIZE_MEMBAR) Remove redundant membars. mpack -Target Report Mask(PACK) +Target Mask(PACK) Pack VLIW instructions. mscc -Target Report Mask(SCC) +Target Mask(SCC) Enable setting GPRs to the result of comparisons. msched-lookahead= @@ -211,15 +211,15 @@ Target RejectNegative Joined UInteger Var(frv_sched_lookahead) Init(4) Change the amount of scheduler lookahead. msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target RejectNegative Mask(SOFT_FLOAT) Use software floating point. mTLS -Target Report RejectNegative Mask(BIG_TLS) +Target RejectNegative Mask(BIG_TLS) Assume a large TLS segment. mtls -Target Report RejectNegative InverseMask(BIG_TLS) +Target RejectNegative InverseMask(BIG_TLS) Do not assume a large TLS segment. ; Not used by the compiler proper. @@ -233,5 +233,5 @@ Target RejectNegative Link with the library-pic libraries. mvliw-branch -Target Report Mask(VLIW_BRANCH) +Target Mask(VLIW_BRANCH) Allow branches to be packed with other instructions. diff --git a/gcc/config/frv/linux.h b/gcc/config/frv/linux.h index ce725cb..d6d8bb8 100644 --- a/gcc/config/frv/linux.h +++ b/gcc/config/frv/linux.h @@ -1,5 +1,5 @@ /* Target macros for the FRV Linux port of GCC. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md index 706b590..5cd3da4 100644 --- a/gcc/config/frv/predicates.md +++ b/gcc/config/frv/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Frv. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/frv/t-frv b/gcc/config/frv/t-frv index bdfde2b..619e3d0 100644 --- a/gcc/config/frv/t-frv +++ b/gcc/config/frv/t-frv @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/frv/t-linux b/gcc/config/frv/t-linux index ea53add..9292dfc 100644 --- a/gcc/config/frv/t-linux +++ b/gcc/config/frv/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md index 088732f..38292c6 100644 --- a/gcc/config/ft32/constraints.md +++ b/gcc/config/ft32/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for FT32 -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/ft32-protos.h b/gcc/config/ft32/ft32-protos.h index 243c7f3..7026a2f 100644 --- a/gcc/config/ft32/ft32-protos.h +++ b/gcc/config/ft32/ft32-protos.h @@ -1,5 +1,5 @@ /* Prototypes for ft32.c functions used in the md file & elsewhere. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c index 0dc12d2..82f773c 100644 --- a/gcc/config/ft32/ft32.c +++ b/gcc/config/ft32/ft32.c @@ -1,5 +1,5 @@ /* Target Code for ft32 - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by FTDI <support@ftdi.com> This file is part of GCC. diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h index 962cce8..f8d0763 100644 --- a/gcc/config/ft32/ft32.h +++ b/gcc/config/ft32/ft32.h @@ -1,5 +1,5 @@ /* Target Definitions for ft32. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by FTDI <support@ftdi.com> This file is part of GCC. diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md index 1a2380f..95ff3d9 100644 --- a/gcc/config/ft32/ft32.md +++ b/gcc/config/ft32/ft32.md @@ -1,5 +1,5 @@ ;; Machine description for FT32 -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/ft32.opt b/gcc/config/ft32/ft32.opt index cabe4b2..f84d9f26 100644 --- a/gcc/config/ft32/ft32.opt +++ b/gcc/config/ft32/ft32.opt @@ -1,6 +1,6 @@ ; Options for the FT32 port of the compiler. -; Copyright (C) 2015-2020 Free Software Foundation, Inc. +; Copyright (C) 2015-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,25 +19,25 @@ ; <http://www.gnu.org/licenses/>. msim -Target Report Mask(SIM) +Target Mask(SIM) Target the software simulator. mlra -Target Report Var(ft32_lra_flag) Init(0) Save +Target Var(ft32_lra_flag) Init(0) Save Use LRA instead of reload. mnodiv -Target Report Mask(NODIV) +Target Mask(NODIV) Avoid use of the DIV and MOD instructions. mft32b -Target Report Mask(FT32B) +Target Mask(FT32B) Target the FT32B architecture. mcompress -Target Report Mask(COMPRESS) +Target Mask(COMPRESS) Enable FT32B code compression. mnopm -Target Report Mask(NOPM) +Target Mask(NOPM) Avoid placing any readable data in program memory. diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md index 54e5c56..8d666c0 100644 --- a/gcc/config/ft32/predicates.md +++ b/gcc/config/ft32/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for FT32 -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/t-ft32 b/gcc/config/ft32/t-ft32 index cdb50f9..e89ad12 100644 --- a/gcc/config/ft32/t-ft32 +++ b/gcc/config/ft32/t-ft32 @@ -1,5 +1,5 @@ # Target Makefile Fragment for ft32 -# Copyright (C) 2015-2020 Free Software Foundation, Inc. +# Copyright (C) 2015-2021 Free Software Foundation, Inc. # Contributed by FTDI <support@ftdi.com> # # This file is part of GCC. diff --git a/gcc/config/fuchsia.h b/gcc/config/fuchsia.h index f7a0f9e..54602dc 100644 --- a/gcc/config/fuchsia.h +++ b/gcc/config/fuchsia.h @@ -1,5 +1,5 @@ /* Base configuration file for all Fuchsia targets. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. Contributed by Google. This file is part of GCC. diff --git a/gcc/config/fused-madd.opt b/gcc/config/fused-madd.opt index 4782522..3c937da 100644 --- a/gcc/config/fused-madd.opt +++ b/gcc/config/fused-madd.opt @@ -1,6 +1,6 @@ ; -mfused-madd option (some targets only). ; -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/g.opt b/gcc/config/g.opt index 4c93869..ea10eb8 100644 --- a/gcc/config/g.opt +++ b/gcc/config/g.opt @@ -1,6 +1,6 @@ ; -G option (small data, some targets only). -; Copyright (C) 2003-2020 Free Software Foundation, Inc. +; Copyright (C) 2003-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/gcn/constraints.md b/gcc/config/gcn/constraints.md index dd6615b..c0fb5a8 100644 --- a/gcc/config/gcn/constraints.md +++ b/gcc/config/gcn/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for GCN. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/gcn/driver-gcn.c b/gcc/config/gcn/driver-gcn.c index 46e07f4..b193276 100644 --- a/gcc/config/gcn/driver-gcn.c +++ b/gcc/config/gcn/driver-gcn.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/gcn/gcn-builtins.def b/gcc/config/gcn/gcn-builtins.def index 1456175..e5e6154 100644 --- a/gcc/config/gcn/gcn-builtins.def +++ b/gcc/config/gcn/gcn-builtins.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn-hsa.h b/gcc/config/gcn/gcn-hsa.h index cb29172..61cdb31 100644 --- a/gcc/config/gcn/gcn-hsa.h +++ b/gcc/config/gcn/gcn-hsa.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn-modes.def b/gcc/config/gcn/gcn-modes.def index 2d5c737..ed3387c 100644 --- a/gcc/config/gcn/gcn-modes.def +++ b/gcc/config/gcn/gcn-modes.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn-opts.h b/gcc/config/gcn/gcn-opts.h index 8eefb7a..ed9b451 100644 --- a/gcc/config/gcn/gcn-opts.h +++ b/gcc/config/gcn/gcn-opts.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn-protos.h b/gcc/config/gcn/gcn-protos.h index 92b1a60..dc9331c 100644 --- a/gcc/config/gcn/gcn-protos.h +++ b/gcc/config/gcn/gcn-protos.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn-run.c b/gcc/config/gcn/gcn-run.c index 31f14f3..0e9538f 100644 --- a/gcc/config/gcn/gcn-run.c +++ b/gcc/config/gcn/gcn-run.c @@ -1,7 +1,7 @@ /* Run a stand-alone AMD GCN kernel. Copyright 2017 Mentor Graphics Corporation - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/gcn/gcn-tree.c b/gcc/config/gcn/gcn-tree.c index 4304f13..8f27099 100644 --- a/gcc/config/gcn/gcn-tree.c +++ b/gcc/config/gcn/gcn-tree.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index e4d7f2a..beefcf7 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free @@ -2185,7 +2185,7 @@ [(set_attr "type" "vop3a") (set_attr "length" "8,8")]) -(define_insn "subdf" +(define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "= v, v") (minus:DF (match_operand:DF 1 "gcn_alu_operand" "vSvB, v") @@ -2351,9 +2351,9 @@ (define_insn "recip<mode>2<exec>" [(set (match_operand:V_FP 0 "register_operand" "= v") - (div:V_FP - (vec_duplicate:V_FP (float:<SCALAR_MODE> (const_int 1))) - (match_operand:V_FP 1 "gcn_alu_operand" "vSvB")))] + (unspec:V_FP + [(match_operand:V_FP 1 "gcn_alu_operand" "vSvB")] + UNSPEC_RCP))] "" "v_rcp%i0\t%0, %1" [(set_attr "type" "vop1") @@ -2361,9 +2361,9 @@ (define_insn "recip<mode>2" [(set (match_operand:FP 0 "register_operand" "= v") - (div:FP - (float:FP (const_int 1)) - (match_operand:FP 1 "gcn_alu_operand" "vSvB")))] + (unspec:FP + [(match_operand:FP 1 "gcn_alu_operand" "vSvB")] + UNSPEC_RCP))] "" "v_rcp%i0\t%0, %1" [(set_attr "type" "vop1") @@ -2382,28 +2382,39 @@ (match_operand:V_FP 2 "gcn_valu_src0_operand")] "flag_reciprocal_math" { - rtx two = gcn_vec_constant (<MODE>mode, - const_double_from_real_value (dconst2, <SCALAR_MODE>mode)); + rtx one = gcn_vec_constant (<MODE>mode, + const_double_from_real_value (dconst1, <SCALAR_MODE>mode)); rtx initrcp = gen_reg_rtx (<MODE>mode); rtx fma = gen_reg_rtx (<MODE>mode); rtx rcp; + rtx num = operands[1], denom = operands[2]; - bool is_rcp = (GET_CODE (operands[1]) == CONST_VECTOR + bool is_rcp = (GET_CODE (num) == CONST_VECTOR && real_identical (CONST_DOUBLE_REAL_VALUE - (CONST_VECTOR_ELT (operands[1], 0)), &dconstm1)); + (CONST_VECTOR_ELT (num, 0)), &dconstm1)); if (is_rcp) rcp = operands[0]; else rcp = gen_reg_rtx (<MODE>mode); - emit_insn (gen_recip<mode>2 (initrcp, operands[2])); - emit_insn (gen_fma<mode>4_negop2 (fma, initrcp, operands[2], two)); - emit_insn (gen_mul<mode>3 (rcp, initrcp, fma)); + emit_insn (gen_recip<mode>2 (initrcp, denom)); + emit_insn (gen_fma<mode>4_negop2 (fma, initrcp, denom, one)); + emit_insn (gen_fma<mode>4 (rcp, fma, initrcp, initrcp)); if (!is_rcp) - emit_insn (gen_mul<mode>3 (operands[0], operands[1], rcp)); + { + rtx div_est = gen_reg_rtx (<MODE>mode); + rtx fma2 = gen_reg_rtx (<MODE>mode); + rtx fma3 = gen_reg_rtx (<MODE>mode); + rtx fma4 = gen_reg_rtx (<MODE>mode); + emit_insn (gen_mul<mode>3 (div_est, num, rcp)); + emit_insn (gen_fma<mode>4_negop2 (fma2, div_est, denom, num)); + emit_insn (gen_fma<mode>4 (fma3, fma2, rcp, div_est)); + emit_insn (gen_fma<mode>4_negop2 (fma4, fma3, denom, num)); + emit_insn (gen_fma<mode>4 (operands[0], fma4, rcp, fma3)); + } DONE; }) @@ -2414,10 +2425,11 @@ (match_operand:FP 2 "gcn_valu_src0_operand")] "flag_reciprocal_math" { - rtx two = const_double_from_real_value (dconst2, <MODE>mode); + rtx one = const_double_from_real_value (dconst1, <MODE>mode); rtx initrcp = gen_reg_rtx (<MODE>mode); rtx fma = gen_reg_rtx (<MODE>mode); rtx rcp; + rtx num = operands[1], denom = operands[2]; bool is_rcp = (GET_CODE (operands[1]) == CONST_DOUBLE && real_identical (CONST_DOUBLE_REAL_VALUE (operands[1]), @@ -2428,12 +2440,22 @@ else rcp = gen_reg_rtx (<MODE>mode); - emit_insn (gen_recip<mode>2 (initrcp, operands[2])); - emit_insn (gen_fma<mode>4_negop2 (fma, initrcp, operands[2], two)); - emit_insn (gen_mul<mode>3 (rcp, initrcp, fma)); + emit_insn (gen_recip<mode>2 (initrcp, denom)); + emit_insn (gen_fma<mode>4_negop2 (fma, initrcp, denom, one)); + emit_insn (gen_fma<mode>4 (rcp, fma, initrcp, initrcp)); if (!is_rcp) - emit_insn (gen_mul<mode>3 (operands[0], operands[1], rcp)); + { + rtx div_est = gen_reg_rtx (<MODE>mode); + rtx fma2 = gen_reg_rtx (<MODE>mode); + rtx fma3 = gen_reg_rtx (<MODE>mode); + rtx fma4 = gen_reg_rtx (<MODE>mode); + emit_insn (gen_mul<mode>3 (div_est, num, rcp)); + emit_insn (gen_fma<mode>4_negop2 (fma2, div_est, denom, num)); + emit_insn (gen_fma<mode>4 (fma3, fma2, rcp, div_est)); + emit_insn (gen_fma<mode>4_negop2 (fma4, fma3, denom, num)); + emit_insn (gen_fma<mode>4 (operands[0], fma4, rcp, fma3)); + } DONE; }) diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index e868a8d..2351b24 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free @@ -2137,10 +2137,6 @@ gcn_conditional_register_usage (void) fixed_regs[cfun->machine->args.reg[WORK_ITEM_ID_Y_ARG]] = 1; if (cfun->machine->args.reg[WORK_ITEM_ID_Z_ARG] >= 0) fixed_regs[cfun->machine->args.reg[WORK_ITEM_ID_Z_ARG]] = 1; - - if (TARGET_GCN5_PLUS) - /* v0 is always zero, for global nul-offsets. */ - fixed_regs[VGPR_REGNO (0)] = 1; } /* Determine if a load or store is valid, according to the register classes @@ -3986,13 +3982,14 @@ gcn_vectorize_vec_perm_const (machine_mode vmode, rtx dst, for (unsigned int i = 0; i < nelt; ++i) perm[i] = sel[i] & (2 * nelt - 1); + src0 = force_reg (vmode, src0); + src1 = force_reg (vmode, src1); + /* Make life a bit easier by swapping operands if necessary so that the first element always comes from src0. */ if (perm[0] >= nelt) { - rtx temp = src0; - src0 = src1; - src1 = temp; + std::swap (src0, src1); for (unsigned int i = 0; i < nelt; ++i) if (perm[i] < nelt) @@ -4254,7 +4251,8 @@ gcn_expand_reduc_scalar (machine_mode mode, rtx src, int unspec) || unspec == UNSPEC_SMAX_DPP_SHR || unspec == UNSPEC_UMIN_DPP_SHR || unspec == UNSPEC_UMAX_DPP_SHR) - && mode == V64DImode) + && (mode == V64DImode + || mode == V64DFmode)) || (unspec == UNSPEC_PLUS_DPP_SHR && mode == V64DFmode)); rtx_code code = (unspec == UNSPEC_SMIN_DPP_SHR ? SMIN @@ -4501,6 +4499,8 @@ gcn_md_reorg (void) df_insn_rescan_all (); } + df_live_add_problem (); + df_live_set_all_dirty (); df_analyze (); /* This pass ensures that the EXEC register is set correctly, according @@ -4522,6 +4522,17 @@ gcn_md_reorg (void) int64_t curr_exec = 0; /* 0 here means 'the value is that of EXEC after last_exec_def is executed'. */ + bitmap live_in = DF_LR_IN (bb); + bool exec_live_on_entry = false; + if (bitmap_bit_p (live_in, EXEC_LO_REG) + || bitmap_bit_p (live_in, EXEC_HI_REG)) + { + if (dump_file) + fprintf (dump_file, "EXEC reg is live on entry to block %d\n", + (int) bb->index); + exec_live_on_entry = true; + } + FOR_BB_INSNS_SAFE (bb, insn, curr) { if (!NONDEBUG_INSN_P (insn)) @@ -4660,6 +4671,8 @@ gcn_md_reorg (void) exec_lo_def_p == exec_hi_def_p ? "full" : "partial", INSN_UID (insn)); } + + exec_live_on_entry = false; } COPY_REG_SET (&live, DF_LR_OUT (bb)); @@ -4669,7 +4682,7 @@ gcn_md_reorg (void) at the end of the block. */ if ((REGNO_REG_SET_P (&live, EXEC_LO_REG) || REGNO_REG_SET_P (&live, EXEC_HI_REG)) - && (!curr_exec_known || !curr_exec_explicit)) + && (!curr_exec_known || !curr_exec_explicit || exec_live_on_entry)) { rtx_insn *end_insn = BB_END (bb); diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h index f63e7df..eba4646 100644 --- a/gcc/config/gcn/gcn.h +++ b/gcc/config/gcn/gcn.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2016-2020 Free Software Foundation, Inc. +/* Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 763e770..b5f895a 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free @@ -80,7 +80,8 @@ UNSPEC_MOV_DPP_SHR UNSPEC_MOV_FROM_LANE63 UNSPEC_GATHER - UNSPEC_SCATTER]) + UNSPEC_SCATTER + UNSPEC_RCP]) ;; }}} ;; {{{ Attributes diff --git a/gcc/config/gcn/gcn.opt b/gcc/config/gcn/gcn.opt index b1ea56e..7fd84f8 100644 --- a/gcc/config/gcn/gcn.opt +++ b/gcc/config/gcn/gcn.opt @@ -1,6 +1,6 @@ ; Options for the GCN port of the compiler. -; Copyright (C) 2016-2020 Free Software Foundation, Inc. +; Copyright (C) 2016-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -43,31 +43,31 @@ Target RejectNegative Joined ToLower Enum(gpu_type) Var(gcn_tune) Init(PROCESSOR Specify the name of the target GPU. m32 -Target Report RejectNegative InverseMask(ABI64) +Target RejectNegative InverseMask(ABI64) Generate code for a 32-bit ABI. m64 -Target Report RejectNegative Mask(ABI64) +Target RejectNegative Mask(ABI64) Generate code for a 64-bit ABI. mgomp -Target Report RejectNegative +Target RejectNegative Enable OpenMP GPU offloading. bool flag_bypass_init_error = false mbypass-init-error -Target Report RejectNegative Var(flag_bypass_init_error) +Target RejectNegative Var(flag_bypass_init_error) bool flag_worker_partitioning = false macc-experimental-workers -Target Report Var(flag_worker_partitioning) Init(0) +Target Var(flag_worker_partitioning) Init(0) int stack_size_opt = -1 mstack-size= -Target Report RejectNegative Joined UInteger Var(stack_size_opt) Init(-1) +Target RejectNegative Joined UInteger Var(stack_size_opt) Init(-1) -mstack-size=<number> Set the private segment size per wave-front, in bytes. Wopenacc-dims diff --git a/gcc/config/gcn/mkoffload.c b/gcc/config/gcn/mkoffload.c index fad0fb3..eb1c717 100644 --- a/gcc/config/gcn/mkoffload.c +++ b/gcc/config/gcn/mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for AMD GCN. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -755,11 +755,6 @@ main (int argc, char **argv) FILE *cfile = stdout; const char *outname = 0; - const char *gcn_s1_name; - const char *gcn_s2_name; - const char *gcn_o_name; - const char *gcn_cfile_name; - progname = "mkoffload"; diagnostic_initialize (global_dc, 0); @@ -905,145 +900,158 @@ main (int argc, char **argv) if (!dumppfx) dumppfx = outname; - const char *mko_dumpbase = concat (dumppfx, ".mkoffload", NULL); - const char *hsaco_dumpbase = concat (dumppfx, ".mkoffload.hsaco", NULL); gcn_dumpbase = concat (dumppfx, ".c", NULL); + const char *gcn_cfile_name; if (save_temps) - { - gcn_s1_name = concat (mko_dumpbase, ".1.s", NULL); - gcn_s2_name = concat (mko_dumpbase, ".2.s", NULL); - gcn_o_name = hsaco_dumpbase; - gcn_cfile_name = gcn_dumpbase; - } + gcn_cfile_name = gcn_dumpbase; else - { - gcn_s1_name = make_temp_file (".mkoffload.1.s"); - gcn_s2_name = make_temp_file (".mkoffload.2.s"); - gcn_o_name = make_temp_file (".mkoffload.hsaco"); - gcn_cfile_name = make_temp_file (".c"); - } - obstack_ptr_grow (&files_to_cleanup, gcn_s1_name); - obstack_ptr_grow (&files_to_cleanup, gcn_s2_name); - obstack_ptr_grow (&files_to_cleanup, gcn_o_name); + gcn_cfile_name = make_temp_file (".c"); obstack_ptr_grow (&files_to_cleanup, gcn_cfile_name); - obstack_ptr_grow (&cc_argv_obstack, "-dumpdir"); - obstack_ptr_grow (&cc_argv_obstack, ""); - obstack_ptr_grow (&cc_argv_obstack, "-dumpbase"); - obstack_ptr_grow (&cc_argv_obstack, mko_dumpbase); - obstack_ptr_grow (&cc_argv_obstack, "-dumpbase-ext"); - obstack_ptr_grow (&cc_argv_obstack, ""); - - obstack_ptr_grow (&cc_argv_obstack, "-o"); - obstack_ptr_grow (&cc_argv_obstack, gcn_s1_name); - obstack_ptr_grow (&cc_argv_obstack, NULL); - const char **cc_argv = XOBFINISH (&cc_argv_obstack, const char **); - - /* Build arguments for assemble/link pass. */ - struct obstack ld_argv_obstack; - obstack_init (&ld_argv_obstack); - obstack_ptr_grow (&ld_argv_obstack, driver); - - /* Extract early-debug information from the input objects. - This loop finds all the inputs that end ".o" and aren't the output. */ - int dbgcount = 0; - for (int ix = 1; ix != argc; ix++) + cfile = fopen (gcn_cfile_name, "w"); + if (!cfile) + fatal_error (input_location, "cannot open '%s'", gcn_cfile_name); + + /* Currently, we only support offloading in 64-bit configurations. */ + if (offload_abi == OFFLOAD_ABI_LP64) { - if (!strcmp (argv[ix], "-o") && ix + 1 != argc) - ++ix; + const char *mko_dumpbase = concat (dumppfx, ".mkoffload", NULL); + const char *hsaco_dumpbase = concat (dumppfx, ".mkoffload.hsaco", NULL); + + const char *gcn_s1_name; + const char *gcn_s2_name; + const char *gcn_o_name; + if (save_temps) + { + gcn_s1_name = concat (mko_dumpbase, ".1.s", NULL); + gcn_s2_name = concat (mko_dumpbase, ".2.s", NULL); + gcn_o_name = hsaco_dumpbase; + } else { - if (strcmp (argv[ix] + strlen(argv[ix]) - 2, ".o") == 0) + gcn_s1_name = make_temp_file (".mkoffload.1.s"); + gcn_s2_name = make_temp_file (".mkoffload.2.s"); + gcn_o_name = make_temp_file (".mkoffload.hsaco"); + } + obstack_ptr_grow (&files_to_cleanup, gcn_s1_name); + obstack_ptr_grow (&files_to_cleanup, gcn_s2_name); + obstack_ptr_grow (&files_to_cleanup, gcn_o_name); + + obstack_ptr_grow (&cc_argv_obstack, "-dumpdir"); + obstack_ptr_grow (&cc_argv_obstack, ""); + obstack_ptr_grow (&cc_argv_obstack, "-dumpbase"); + obstack_ptr_grow (&cc_argv_obstack, mko_dumpbase); + obstack_ptr_grow (&cc_argv_obstack, "-dumpbase-ext"); + obstack_ptr_grow (&cc_argv_obstack, ""); + + obstack_ptr_grow (&cc_argv_obstack, "-o"); + obstack_ptr_grow (&cc_argv_obstack, gcn_s1_name); + obstack_ptr_grow (&cc_argv_obstack, NULL); + const char **cc_argv = XOBFINISH (&cc_argv_obstack, const char **); + + /* Build arguments for assemble/link pass. */ + struct obstack ld_argv_obstack; + obstack_init (&ld_argv_obstack); + obstack_ptr_grow (&ld_argv_obstack, driver); + + /* Extract early-debug information from the input objects. + This loop finds all the inputs that end ".o" and aren't the output. */ + int dbgcount = 0; + for (int ix = 1; ix != argc; ix++) + { + if (!strcmp (argv[ix], "-o") && ix + 1 != argc) + ++ix; + else { - char *dbgobj; - if (save_temps) - { - char buf[10]; - sprintf (buf, "%d", dbgcount++); - dbgobj = concat (dumppfx, ".mkoffload.dbg", buf, ".o", NULL); - } - else - dbgobj = make_temp_file (".mkoffload.dbg.o"); - - /* If the copy fails then just ignore it. */ - if (copy_early_debug_info (argv[ix], dbgobj)) + if (strcmp (argv[ix] + strlen(argv[ix]) - 2, ".o") == 0) { - obstack_ptr_grow (&ld_argv_obstack, dbgobj); - obstack_ptr_grow (&files_to_cleanup, dbgobj); + char *dbgobj; + if (save_temps) + { + char buf[10]; + sprintf (buf, "%d", dbgcount++); + dbgobj = concat (dumppfx, ".mkoffload.dbg", buf, ".o", NULL); + } + else + dbgobj = make_temp_file (".mkoffload.dbg.o"); + + /* If the copy fails then just ignore it. */ + if (copy_early_debug_info (argv[ix], dbgobj)) + { + obstack_ptr_grow (&ld_argv_obstack, dbgobj); + obstack_ptr_grow (&files_to_cleanup, dbgobj); + } + else + free (dbgobj); } - else - free (dbgobj); } } + obstack_ptr_grow (&ld_argv_obstack, gcn_s2_name); + obstack_ptr_grow (&ld_argv_obstack, "-lgomp"); + + for (int i = 1; i < argc; i++) + if (strncmp (argv[i], "-l", 2) == 0 + || strncmp (argv[i], "-Wl", 3) == 0 + || strncmp (argv[i], "-march", 6) == 0) + obstack_ptr_grow (&ld_argv_obstack, argv[i]); + + obstack_ptr_grow (&cc_argv_obstack, "-dumpdir"); + obstack_ptr_grow (&cc_argv_obstack, ""); + obstack_ptr_grow (&cc_argv_obstack, "-dumpbase"); + obstack_ptr_grow (&cc_argv_obstack, hsaco_dumpbase); + obstack_ptr_grow (&cc_argv_obstack, "-dumpbase-ext"); + obstack_ptr_grow (&cc_argv_obstack, ""); + + obstack_ptr_grow (&ld_argv_obstack, "-o"); + obstack_ptr_grow (&ld_argv_obstack, gcn_o_name); + obstack_ptr_grow (&ld_argv_obstack, NULL); + const char **ld_argv = XOBFINISH (&ld_argv_obstack, const char **); + + /* Clean up unhelpful environment variables. */ + char *execpath = getenv ("GCC_EXEC_PREFIX"); + char *cpath = getenv ("COMPILER_PATH"); + char *lpath = getenv ("LIBRARY_PATH"); + unsetenv ("GCC_EXEC_PREFIX"); + unsetenv ("COMPILER_PATH"); + unsetenv ("LIBRARY_PATH"); + + /* Run the compiler pass. */ + fork_execute (cc_argv[0], CONST_CAST (char **, cc_argv), true, ".gcc_args"); + obstack_free (&cc_argv_obstack, NULL); + + in = fopen (gcn_s1_name, "r"); + if (!in) + fatal_error (input_location, "cannot open intermediate gcn asm file"); + + out = fopen (gcn_s2_name, "w"); + if (!out) + fatal_error (input_location, "cannot open '%s'", gcn_s2_name); + + process_asm (in, out, cfile); + + fclose (in); + fclose (out); + + /* Run the assemble/link pass. */ + fork_execute (ld_argv[0], CONST_CAST (char **, ld_argv), true, ".ld_args"); + obstack_free (&ld_argv_obstack, NULL); + + in = fopen (gcn_o_name, "r"); + if (!in) + fatal_error (input_location, "cannot open intermediate gcn obj file"); + + process_obj (in, cfile); + + fclose (in); + + xputenv (concat ("GCC_EXEC_PREFIX=", execpath, NULL)); + xputenv (concat ("COMPILER_PATH=", cpath, NULL)); + xputenv (concat ("LIBRARY_PATH=", lpath, NULL)); } - obstack_ptr_grow (&ld_argv_obstack, gcn_s2_name); - obstack_ptr_grow (&ld_argv_obstack, "-lgomp"); - for (int i = 1; i < argc; i++) - if (strncmp (argv[i], "-l", 2) == 0 - || strncmp (argv[i], "-Wl", 3) == 0 - || strncmp (argv[i], "-march", 6) == 0) - obstack_ptr_grow (&ld_argv_obstack, argv[i]); - - obstack_ptr_grow (&cc_argv_obstack, "-dumpdir"); - obstack_ptr_grow (&cc_argv_obstack, ""); - obstack_ptr_grow (&cc_argv_obstack, "-dumpbase"); - obstack_ptr_grow (&cc_argv_obstack, hsaco_dumpbase); - obstack_ptr_grow (&cc_argv_obstack, "-dumpbase-ext"); - obstack_ptr_grow (&cc_argv_obstack, ""); - - obstack_ptr_grow (&ld_argv_obstack, "-o"); - obstack_ptr_grow (&ld_argv_obstack, gcn_o_name); - obstack_ptr_grow (&ld_argv_obstack, NULL); - const char **ld_argv = XOBFINISH (&ld_argv_obstack, const char **); - - /* Clean up unhelpful environment variables. */ - char *execpath = getenv ("GCC_EXEC_PREFIX"); - char *cpath = getenv ("COMPILER_PATH"); - char *lpath = getenv ("LIBRARY_PATH"); - unsetenv ("GCC_EXEC_PREFIX"); - unsetenv ("COMPILER_PATH"); - unsetenv ("LIBRARY_PATH"); - - /* Run the compiler pass. */ - fork_execute (cc_argv[0], CONST_CAST (char **, cc_argv), true, ".gcc_args"); - obstack_free (&cc_argv_obstack, NULL); - - in = fopen (gcn_s1_name, "r"); - if (!in) - fatal_error (input_location, "cannot open intermediate gcn asm file"); - - out = fopen (gcn_s2_name, "w"); - if (!out) - fatal_error (input_location, "cannot open '%s'", gcn_s2_name); - - cfile = fopen (gcn_cfile_name, "w"); - if (!cfile) - fatal_error (input_location, "cannot open '%s'", gcn_cfile_name); - - process_asm (in, out, cfile); - - fclose (in); - fclose (out); - - /* Run the assemble/link pass. */ - fork_execute (ld_argv[0], CONST_CAST (char **, ld_argv), true, ".ld_args"); - obstack_free (&ld_argv_obstack, NULL); - - in = fopen (gcn_o_name, "r"); - if (!in) - fatal_error (input_location, "cannot open intermediate gcn obj file"); - - process_obj (in, cfile); - - fclose (in); fclose (cfile); - xputenv (concat ("GCC_EXEC_PREFIX=", execpath, NULL)); - xputenv (concat ("COMPILER_PATH=", cpath, NULL)); - xputenv (concat ("LIBRARY_PATH=", lpath, NULL)); - compile_native (gcn_cfile_name, outname, collect_gcc, fPIC, fpic); return 0; diff --git a/gcc/config/gcn/offload.h b/gcc/config/gcn/offload.h index a843596..0ee1d3c 100644 --- a/gcc/config/gcn/offload.h +++ b/gcc/config/gcn/offload.h @@ -1,6 +1,6 @@ /* Support for AMD GCN offloading. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/gcn/predicates.md b/gcc/config/gcn/predicates.md index 91e5ca1..6bace02 100644 --- a/gcc/config/gcn/predicates.md +++ b/gcc/config/gcn/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for GCN. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/gcn/t-gcn-hsa b/gcc/config/gcn/t-gcn-hsa index 16d243c..bf47da7 100644 --- a/gcc/config/gcn/t-gcn-hsa +++ b/gcc/config/gcn/t-gcn-hsa @@ -1,4 +1,4 @@ -# Copyright (C) 2016-2020 Free Software Foundation, Inc. +# Copyright (C) 2016-2021 Free Software Foundation, Inc. # # This file is free software; you can redistribute it and/or modify it under # the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/glibc-c.c b/gcc/config/glibc-c.c index 3705b8c..e178e13 100644 --- a/gcc/config/glibc-c.c +++ b/gcc/config/glibc-c.c @@ -1,5 +1,5 @@ /* C-family target hooks initializer for targets possibly using glibc. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/glibc-d.c b/gcc/config/glibc-d.c index 7eb9e31..092c5d8 100644 --- a/gcc/config/glibc-d.c +++ b/gcc/config/glibc-d.c @@ -1,5 +1,5 @@ /* Glibc support needed only by D front-end. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h index ef578e5..c8d7ba1 100644 --- a/gcc/config/glibc-stdint.h +++ b/gcc/config/glibc-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using GNU libc or uClibc. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h index 9295024..5ebbf42 100644 --- a/gcc/config/gnu-user.h +++ b/gcc/config/gnu-user.h @@ -1,7 +1,7 @@ /* Definitions for systems using, at least optionally, a GNU (glibc-based) userspace or other userspace with libc derived from glibc (e.g. uClibc) or for which similar specs are appropriate. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org). diff --git a/gcc/config/gnu-user.opt b/gcc/config/gnu-user.opt index d521978..e51c8f2 100644 --- a/gcc/config/gnu-user.opt +++ b/gcc/config/gnu-user.opt @@ -1,6 +1,6 @@ ; Options for systems using gnu-user.h. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/gnu.h b/gcc/config/gnu.h index d6d5e98..7950bd1 100644 --- a/gcc/config/gnu.h +++ b/gcc/config/gnu.h @@ -1,7 +1,7 @@ /* Configuration common to all targets running the GNU system. */ /* -Copyright (C) 1994-2020 Free Software Foundation, Inc. +Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md index 1d80152..9f7b1a9 100644 --- a/gcc/config/h8300/constraints.md +++ b/gcc/config/h8300/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas H8/300. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/elf.h b/gcc/config/h8300/elf.h index 06844a5..0d9f582 100644 --- a/gcc/config/h8300/elf.h +++ b/gcc/config/h8300/elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 version generating elf - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/genmova.sh b/gcc/config/h8300/genmova.sh index 8ab018f..c8a8ab4 100644 --- a/gcc/config/h8300/genmova.sh +++ b/gcc/config/h8300/genmova.sh @@ -2,7 +2,7 @@ # Generate mova.md, a file containing patterns that can be implemented # using the h8sx mova instruction. -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ echo ";; -*- buffer-read-only: t -*-" echo ";; Generated automatically from genmova.sh" -echo ";; Copyright (C) 2004-2020 Free Software Foundation, Inc." +echo ";; Copyright (C) 2004-2021 Free Software Foundation, Inc." echo ";;" echo ";; This file is part of GCC." echo ";;" diff --git a/gcc/config/h8300/h8300-modes.def b/gcc/config/h8300/h8300-modes.def index 2f36c7e..23b777b 100644 --- a/gcc/config/h8300/h8300-modes.def +++ b/gcc/config/h8300/h8300-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h index 2d90036..c5667b3 100644 --- a/gcc/config/h8300/h8300-protos.h +++ b/gcc/config/h8300/h8300-protos.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 version - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 31e23b2..0ae8030 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Renesas H8/300. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h index 99d85ff..b1fbcc5 100644 --- a/gcc/config/h8300/h8300.h +++ b/gcc/config/h8300/h8300.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 (generic) - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index 932f74e..9a42547 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1,5 +1,5 @@ ;; GCC machine description for Renesas H8/300 -;; Copyright (C) 1992-2020 Free Software Foundation, Inc. +;; Copyright (C) 1992-2021 Free Software Foundation, Inc. ;; Contributed by Steve Chamberlain (sac@cygnus.com), ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.opt b/gcc/config/h8300/h8300.opt index e527346..a838ab6 100644 --- a/gcc/config/h8300/h8300.opt +++ b/gcc/config/h8300/h8300.opt @@ -1,6 +1,6 @@ ; Options for the Renesas H8/300 port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/h8300/linux.h b/gcc/config/h8300/linux.h index 9621c47..50beab6 100644 --- a/gcc/config/h8300/linux.h +++ b/gcc/config/h8300/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 (linux variant) - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Yoshinori Sato <ysato@users.sourceforge.jp> This file is part of GCC. diff --git a/gcc/config/h8300/mova.md b/gcc/config/h8300/mova.md index cdcd4b8..d6b8377 100644 --- a/gcc/config/h8300/mova.md +++ b/gcc/config/h8300/mova.md @@ -1,6 +1,6 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically from genmova.sh -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md index 7c4e12a..f4e3ed4 100644 --- a/gcc/config/h8300/predicates.md +++ b/gcc/config/h8300/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas H8/300. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/t-h8300 b/gcc/config/h8300/t-h8300 index 62d2700..7b742b5 100644 --- a/gcc/config/h8300/t-h8300 +++ b/gcc/config/h8300/t-h8300 @@ -1,4 +1,4 @@ -# Copyright (C) 1993-2020 Free Software Foundation, Inc. +# Copyright (C) 1993-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/h8300/t-linux b/gcc/config/h8300/t-linux index b236d6c..7771f21 100644 --- a/gcc/config/h8300/t-linux +++ b/gcc/config/h8300/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2015-2020 Free Software Foundation, Inc. +# Copyright (C) 2015-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/host-darwin.c b/gcc/config/host-darwin.c index c862935..1816c61 100644 --- a/gcc/config/host-darwin.c +++ b/gcc/config/host-darwin.c @@ -1,5 +1,5 @@ /* Darwin host-specific hook definitions. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-darwin.h b/gcc/config/host-darwin.h index fe65908..4acae9c 100644 --- a/gcc/config/host-darwin.h +++ b/gcc/config/host-darwin.h @@ -1,5 +1,5 @@ /* Darwin host-specific hook definitions. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-hpux.c b/gcc/config/host-hpux.c index ae3a559..6009810 100644 --- a/gcc/config/host-hpux.c +++ b/gcc/config/host-hpux.c @@ -1,5 +1,5 @@ /* HP-UX host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-linux.c b/gcc/config/host-linux.c index 26872544..34945f1 100644 --- a/gcc/config/host-linux.c +++ b/gcc/config/host-linux.c @@ -1,5 +1,5 @@ /* Linux host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-netbsd.c b/gcc/config/host-netbsd.c index 2f486be..818ecb2 100644 --- a/gcc/config/host-netbsd.c +++ b/gcc/config/host-netbsd.c @@ -1,5 +1,5 @@ /* NetBSD host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-openbsd.c b/gcc/config/host-openbsd.c index da068c4..c5f8944 100644 --- a/gcc/config/host-openbsd.c +++ b/gcc/config/host-openbsd.c @@ -1,5 +1,5 @@ /* OpenBSD host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-solaris.c b/gcc/config/host-solaris.c index d133c6e..556e9cf 100644 --- a/gcc/config/host-solaris.c +++ b/gcc/config/host-solaris.c @@ -1,5 +1,5 @@ /* Solaris host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/hpux11.opt b/gcc/config/hpux11.opt index f43b028..db16edf 100644 --- a/gcc/config/hpux11.opt +++ b/gcc/config/hpux11.opt @@ -1,6 +1,6 @@ ; HP-UX 11 options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/adxintrin.h b/gcc/config/i386/adxintrin.h index 6dffe45..e514e74 100644 --- a/gcc/config/i386/adxintrin.h +++ b/gcc/config/i386/adxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ammintrin.h b/gcc/config/i386/ammintrin.h index 88d6f46..a071a49 100644 --- a/gcc/config/i386/ammintrin.h +++ b/gcc/config/i386/ammintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/amxbf16intrin.h b/gcc/config/i386/amxbf16intrin.h index 77cc395..8c24cdd 100644 --- a/gcc/config/i386/amxbf16intrin.h +++ b/gcc/config/i386/amxbf16intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/amxint8intrin.h b/gcc/config/i386/amxint8intrin.h index f4e410b..180c243 100644 --- a/gcc/config/i386/amxint8intrin.h +++ b/gcc/config/i386/amxint8intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/amxtileintrin.h b/gcc/config/i386/amxtileintrin.h index 41fb9a5..16c8b6e 100644 --- a/gcc/config/i386/amxtileintrin.h +++ b/gcc/config/i386/amxtileintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index 903b9da..ae71b85 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/atom.md b/gcc/config/i386/atom.md index 32507c0..c862174 100644 --- a/gcc/config/i386/atom.md +++ b/gcc/config/i386/atom.md @@ -1,5 +1,5 @@ ;; Atom Scheduling -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/att.h b/gcc/config/i386/att.h index fb2ed05..885c06a 100644 --- a/gcc/config/i386/att.h +++ b/gcc/config/i386/att.h @@ -1,5 +1,5 @@ /* Definitions for AT&T assembler syntax for the Intel 80386. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index e29c532..96ee310 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx5124fmapsintrin.h b/gcc/config/i386/avx5124fmapsintrin.h index 4f0c793..d34a38e 100644 --- a/gcc/config/i386/avx5124fmapsintrin.h +++ b/gcc/config/i386/avx5124fmapsintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx5124vnniwintrin.h b/gcc/config/i386/avx5124vnniwintrin.h index e9f7ec2..f143312 100644 --- a/gcc/config/i386/avx5124vnniwintrin.h +++ b/gcc/config/i386/avx5124vnniwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bf16intrin.h b/gcc/config/i386/avx512bf16intrin.h index 572eb0c..9afc6bd 100644 --- a/gcc/config/i386/avx512bf16intrin.h +++ b/gcc/config/i386/avx512bf16intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bf16vlintrin.h b/gcc/config/i386/avx512bf16vlintrin.h index edb30e1..6dd396d 100644 --- a/gcc/config/i386/avx512bf16vlintrin.h +++ b/gcc/config/i386/avx512bf16vlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bitalgintrin.h b/gcc/config/i386/avx512bitalgintrin.h index 498d5d8..24bf0da 100644 --- a/gcc/config/i386/avx512bitalgintrin.h +++ b/gcc/config/i386/avx512bitalgintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h index 3da05e1..489e70e 100644 --- a/gcc/config/i386/avx512bwintrin.h +++ b/gcc/config/i386/avx512bwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512cdintrin.h b/gcc/config/i386/avx512cdintrin.h index 17427a9..24abc3c 100644 --- a/gcc/config/i386/avx512cdintrin.h +++ b/gcc/config/i386/avx512cdintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index fd61b70..51c0b12 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512erintrin.h b/gcc/config/i386/avx512erintrin.h index 6ec8ee2..99b7d66 100644 --- a/gcc/config/i386/avx512erintrin.h +++ b/gcc/config/i386/avx512erintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index 6342fde..515ee0c 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmaintrin.h b/gcc/config/i386/avx512ifmaintrin.h index dd3aaa7..53c00bd 100644 --- a/gcc/config/i386/avx512ifmaintrin.h +++ b/gcc/config/i386/avx512ifmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h index 0bf403c..3760853 100644 --- a/gcc/config/i386/avx512ifmavlintrin.h +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512pfintrin.h b/gcc/config/i386/avx512pfintrin.h index 6227039..1adc850 100644 --- a/gcc/config/i386/avx512pfintrin.h +++ b/gcc/config/i386/avx512pfintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmi2intrin.h b/gcc/config/i386/avx512vbmi2intrin.h index 5114d4d..f31ba97 100644 --- a/gcc/config/i386/avx512vbmi2intrin.h +++ b/gcc/config/i386/avx512vbmi2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmi2vlintrin.h b/gcc/config/i386/avx512vbmi2vlintrin.h index 3ab44ae..f65c022 100644 --- a/gcc/config/i386/avx512vbmi2vlintrin.h +++ b/gcc/config/i386/avx512vbmi2vlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmiintrin.h b/gcc/config/i386/avx512vbmiintrin.h index bb26234..92f203b 100644 --- a/gcc/config/i386/avx512vbmiintrin.h +++ b/gcc/config/i386/avx512vbmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h index f3c346a..73ffb37 100644 --- a/gcc/config/i386/avx512vbmivlintrin.h +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h index b4b1d7f..3c4dc58 100644 --- a/gcc/config/i386/avx512vlbwintrin.h +++ b/gcc/config/i386/avx512vlbwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index ec9b95e..2301d72 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h index 99666c7..0b0889e 100644 --- a/gcc/config/i386/avx512vlintrin.h +++ b/gcc/config/i386/avx512vlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vnniintrin.h b/gcc/config/i386/avx512vnniintrin.h index bf76409..7919618 100644 --- a/gcc/config/i386/avx512vnniintrin.h +++ b/gcc/config/i386/avx512vnniintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vnnivlintrin.h b/gcc/config/i386/avx512vnnivlintrin.h index 3845b03..53ba115 100644 --- a/gcc/config/i386/avx512vnnivlintrin.h +++ b/gcc/config/i386/avx512vnnivlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vp2intersectintrin.h b/gcc/config/i386/avx512vp2intersectintrin.h index f368d83..8473514 100644 --- a/gcc/config/i386/avx512vp2intersectintrin.h +++ b/gcc/config/i386/avx512vp2intersectintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vp2intersectvlintrin.h b/gcc/config/i386/avx512vp2intersectvlintrin.h index f657840..8677412 100644 --- a/gcc/config/i386/avx512vp2intersectvlintrin.h +++ b/gcc/config/i386/avx512vp2intersectvlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h b/gcc/config/i386/avx512vpopcntdqintrin.h index 967d01b..f98a390 100644 --- a/gcc/config/i386/avx512vpopcntdqintrin.h +++ b/gcc/config/i386/avx512vpopcntdqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vpopcntdqvlintrin.h b/gcc/config/i386/avx512vpopcntdqvlintrin.h index 6890004..9decca0 100644 --- a/gcc/config/i386/avx512vpopcntdqvlintrin.h +++ b/gcc/config/i386/avx512vpopcntdqvlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxintrin.h b/gcc/config/i386/avxintrin.h index fd5cf6a..5dbe259 100644 --- a/gcc/config/i386/avxintrin.h +++ b/gcc/config/i386/avxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxmath.h b/gcc/config/i386/avxmath.h index 7091f3e..891853b 100644 --- a/gcc/config/i386/avxmath.h +++ b/gcc/config/i386/avxmath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2020 Free Software Foundation, Inc. +/* Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxvnniintrin.h b/gcc/config/i386/avxvnniintrin.h index de7e6a9..9abdbc9 100644 --- a/gcc/config/i386/avxvnniintrin.h +++ b/gcc/config/i386/avxvnniintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bdver1.md b/gcc/config/i386/bdver1.md index ba87a0c..db4b390 100644 --- a/gcc/config/i386/bdver1.md +++ b/gcc/config/i386/bdver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/bdver3.md b/gcc/config/i386/bdver3.md index 6fdcf43..3a56f57 100644 --- a/gcc/config/i386/bdver3.md +++ b/gcc/config/i386/bdver3.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/biarch64.h b/gcc/config/i386/biarch64.h index 433443d..7fd935e 100644 --- a/gcc/config/i386/biarch64.h +++ b/gcc/config/i386/biarch64.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to 64bit mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/biarchx32.h b/gcc/config/i386/biarchx32.h index 0651522..6dbadd4 100644 --- a/gcc/config/i386/biarchx32.h +++ b/gcc/config/i386/biarchx32.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to x32 mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmi2intrin.h b/gcc/config/i386/bmi2intrin.h index 9fdd08c..6b23e4e 100644 --- a/gcc/config/i386/bmi2intrin.h +++ b/gcc/config/i386/bmi2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index 5bd712a..439d81c 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2020 Free Software Foundation, Inc. +/* Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmmintrin.h b/gcc/config/i386/bmmintrin.h index 4e8d786..ffa438d 100644 --- a/gcc/config/i386/bmmintrin.h +++ b/gcc/config/i386/bmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bsd.h b/gcc/config/i386/bsd.h index 42e81fc..2aa7fb2 100644 --- a/gcc/config/i386/bsd.h +++ b/gcc/config/i386/bsd.h @@ -1,7 +1,7 @@ /* Definitions for BSD assembler syntax for Intel 386 (actually AT&T syntax for insns and operands, adapted to BSD conventions for symbol names and debugging.) - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/btver2.md b/gcc/config/i386/btver2.md index 42338ed..f9e4a15 100644 --- a/gcc/config/i386/btver2.md +++ b/gcc/config/i386/btver2.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/cet.h b/gcc/config/i386/cet.h index b9e6476..03ce1c6 100644 --- a/gcc/config/i386/cet.h +++ b/gcc/config/i386/cet.h @@ -1,5 +1,5 @@ /* ELF program property for Intel CET. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/i386/cetintrin.h b/gcc/config/i386/cetintrin.h index 81c4d72..803c628 100644 --- a/gcc/config/i386/cetintrin.h +++ b/gcc/config/i386/cetintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cldemoteintrin.h b/gcc/config/i386/cldemoteintrin.h index 0c31c35..67dddaf 100644 --- a/gcc/config/i386/cldemoteintrin.h +++ b/gcc/config/i386/cldemoteintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clflushoptintrin.h b/gcc/config/i386/clflushoptintrin.h index a3697f0..d8b5576 100644 --- a/gcc/config/i386/clflushoptintrin.h +++ b/gcc/config/i386/clflushoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clwbintrin.h b/gcc/config/i386/clwbintrin.h index 3f83962..2113442 100644 --- a/gcc/config/i386/clwbintrin.h +++ b/gcc/config/i386/clwbintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clzerointrin.h b/gcc/config/i386/clzerointrin.h index fb96bc5..f909516 100644 --- a/gcc/config/i386/clzerointrin.h +++ b/gcc/config/i386/clzerointrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 0b902d5..0ccefa8 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for IA-32 and x86-64. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/core2.md b/gcc/config/i386/core2.md index a03e0d2..d631819 100644 --- a/gcc/config/i386/core2.md +++ b/gcc/config/i386/core2.md @@ -1,5 +1,5 @@ ;; Scheduling for Core 2 and derived processors. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index d2d42f7..539325d 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2020 Free Software Foundation, Inc. + * Copyright (C) 2007-2021 Free Software Foundation, Inc. * * This file is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/gcc/config/i386/cross-stdarg.h b/gcc/config/i386/cross-stdarg.h index 6eac4b3..0d524e8 100644 --- a/gcc/config/i386/cross-stdarg.h +++ b/gcc/config/i386/cross-stdarg.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/crtdll.h b/gcc/config/i386/crtdll.h index 9c441c0..2858ad1 100644 --- a/gcc/config/i386/crtdll.h +++ b/gcc/config/i386/crtdll.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. This variant uses CRTDLL.DLL instead of MSVCRTDLL.DLL. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 1b1ea7d..cfbca34 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt index 73f1438..1907874 100644 --- a/gcc/config/i386/cygming.opt +++ b/gcc/config/i386/cygming.opt @@ -1,6 +1,6 @@ ; Cygwin- and MinGW-specific options. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -27,7 +27,7 @@ Target RejectNegative Generate code for a DLL. mnop-fun-dllimport -Target Report Var(TARGET_NOP_FUN_DLLIMPORT) +Target Var(TARGET_NOP_FUN_DLLIMPORT) Ignore dllimport for functions. mthreads @@ -51,14 +51,14 @@ Target Condition({defined (USE_CYGWIN_LIBSTDCXX_WRAPPERS)}) Compile code that relies on Cygwin DLL wrappers to support C++ operator new/delete replacement. fset-stack-executable -Common Report Var(flag_setstackexecutable) Init(1) Optimization +Common Var(flag_setstackexecutable) Init(1) Optimization For nested functions on stack executable permission is set. posix Driver fwritable-relocated-rdata -Common Report Var(flag_writable_rel_rdata) Init(0) +Common Var(flag_writable_rel_rdata) Init(0) Put relocated read-only data into .data section. ; Retain blank line above diff --git a/gcc/config/i386/cygwin-stdint.h b/gcc/config/i386/cygwin-stdint.h index e44188e..2725cb1 100644 --- a/gcc/config/i386/cygwin-stdint.h +++ b/gcc/config/i386/cygwin-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using Cygwin. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin-w64.h b/gcc/config/i386/cygwin-w64.h index 25814a3..8bac9d0 100644 --- a/gcc/config/i386/cygwin-w64.h +++ b/gcc/config/i386/cygwin-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via Cygwin runtime, using GNU tools and the Windows API Library. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index 73737f4..db0a3cc 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.opt b/gcc/config/i386/cygwin.opt index 44b9c88..fcec11d 100644 --- a/gcc/config/i386/cygwin.opt +++ b/gcc/config/i386/cygwin.opt @@ -1,6 +1,6 @@ ; Cygwin-specific options. -; Copyright (C) 2013-2020 Free Software Foundation, Inc. +; Copyright (C) 2013-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h index fec934a..c81db9b 100644 --- a/gcc/config/i386/darwin.h +++ b/gcc/config/i386/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for x86 running Darwin. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/i386/darwin32-biarch.h b/gcc/config/i386/darwin32-biarch.h index 2a90709..73b83eb 100644 --- a/gcc/config/i386/darwin32-biarch.h +++ b/gcc/config/i386/darwin32-biarch.h @@ -1,6 +1,6 @@ /* Target definitions for i386 running Darwin with a 32b host and supporting a 64b multilib. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/darwin64-biarch.h b/gcc/config/i386/darwin64-biarch.h index f20fa83..1ae76b8 100644 --- a/gcc/config/i386/darwin64-biarch.h +++ b/gcc/config/i386/darwin64-biarch.h @@ -1,6 +1,6 @@ /* Target definitions for x86_64 running Darwin with a 64b host supporting a 32b multilib. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp-stdint.h b/gcc/config/i386/djgpp-stdint.h index 7aafb52..19a699d 100644 --- a/gcc/config/i386/djgpp-stdint.h +++ b/gcc/config/i386/djgpp-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using DJGPP. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp.c b/gcc/config/i386/djgpp.c index ba6c2d4..4d9548a 100644 --- a/gcc/config/i386/djgpp.c +++ b/gcc/config/i386/djgpp.c @@ -1,5 +1,5 @@ /* Subroutines for DJGPP. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp.h b/gcc/config/i386/djgpp.h index 62bfd3a..9decff7 100644 --- a/gcc/config/i386/djgpp.h +++ b/gcc/config/i386/djgpp.h @@ -1,5 +1,5 @@ /* Configuration for an i386 running MS-DOS with DJGPP. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp.opt b/gcc/config/i386/djgpp.opt index 5bebf87..08fd633 100644 --- a/gcc/config/i386/djgpp.opt +++ b/gcc/config/i386/djgpp.opt @@ -1,6 +1,6 @@ ; DJGPP-specific options. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/dragonfly.h b/gcc/config/i386/dragonfly.h index 2f1d3ee..ab8a269 100644 --- a/gcc/config/i386/dragonfly.h +++ b/gcc/config/i386/dragonfly.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running DragonFly with ELF format - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 2bfa037..dd92366 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/driver-mingw32.c b/gcc/config/i386/driver-mingw32.c index d0517e6..5dfd1fe 100644 --- a/gcc/config/i386/driver-mingw32.c +++ b/gcc/config/i386/driver-mingw32.c @@ -1,5 +1,5 @@ /* Host OS specific configuration for the gcc driver. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index 8ff240e..eb6de5c 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/enqcmdintrin.h b/gcc/config/i386/enqcmdintrin.h index dcb6507..2518df1 100644 --- a/gcc/config/i386/enqcmdintrin.h +++ b/gcc/config/i386/enqcmdintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2019-2020 Free Software Foundation, Inc. +/* Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h index 8276e8d..c9b71c1 100644 --- a/gcc/config/i386/f16cintrin.h +++ b/gcc/config/i386/f16cintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fma4intrin.h b/gcc/config/i386/fma4intrin.h index 1cfe2d8..f6edcdd 100644 --- a/gcc/config/i386/fma4intrin.h +++ b/gcc/config/i386/fma4intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fmaintrin.h b/gcc/config/i386/fmaintrin.h index 0bd18af..ffad1a6 100644 --- a/gcc/config/i386/fmaintrin.h +++ b/gcc/config/i386/fmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h index 9d66602..b1b3bb3 100644 --- a/gcc/config/i386/freebsd.h +++ b/gcc/config/i386/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running FreeBSD with ELF format - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. Adapted from GNU/Linux version by John Polstra. diff --git a/gcc/config/i386/freebsd64.h b/gcc/config/i386/freebsd64.h index c211e1a..b69b8a5 100644 --- a/gcc/config/i386/freebsd64.h +++ b/gcc/config/i386/freebsd64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running FreeBSD with ELF format - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by David O'Brien <obrien@FreeBSD.org> This file is part of GCC. diff --git a/gcc/config/i386/fxsrintrin.h b/gcc/config/i386/fxsrintrin.h index 6e059df..fd2e538 100644 --- a/gcc/config/i386/fxsrintrin.h +++ b/gcc/config/i386/fxsrintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h index 945ba62..f76a283 100644 --- a/gcc/config/i386/gas.h +++ b/gcc/config/i386/gas.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 using GAS. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/geode.md b/gcc/config/i386/geode.md index c2d1f12..0bf02b5 100644 --- a/gcc/config/i386/geode.md +++ b/gcc/config/i386/geode.md @@ -1,5 +1,5 @@ ;; Geode Scheduling -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h index ebfb304..3e64b25 100644 --- a/gcc/config/i386/gfniintrin.h +++ b/gcc/config/i386/gfniintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/glm.md b/gcc/config/i386/glm.md index 962407a..6f72fd0 100644 --- a/gcc/config/i386/glm.md +++ b/gcc/config/i386/glm.md @@ -1,5 +1,5 @@ ;; Goldmont(GLM) Scheduling -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/gmm_malloc.h b/gcc/config/i386/gmm_malloc.h index 7d1d122..70b38ab 100644 --- a/gcc/config/i386/gmm_malloc.h +++ b/gcc/config/i386/gmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gnu-property.c b/gcc/config/i386/gnu-property.c index 1288325..4ba0440 100644 --- a/gcc/config/i386/gnu-property.c +++ b/gcc/config/i386/gnu-property.c @@ -1,5 +1,5 @@ /* Functions for x86 GNU property. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h index 10392e6..00226f5 100644 --- a/gcc/config/i386/gnu-user-common.h +++ b/gcc/config/i386/gnu-user-common.h @@ -1,5 +1,5 @@ /* Common definitions for Intel 386 and AMD x86-64 systems using - GNU userspace. Copyright (C) 2012-2020 Free Software Foundation, Inc. + GNU userspace. Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h index 6ec5a11..a23e7ab 100644 --- a/gcc/config/i386/gnu-user.h +++ b/gcc/config/i386/gnu-user.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 systems using GNU userspace. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 785c682..f3e25b1 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 using GNU userspace. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/gnu.h b/gcc/config/i386/gnu.h index a39241d..25fbc07 100644 --- a/gcc/config/i386/gnu.h +++ b/gcc/config/i386/gnu.h @@ -1,7 +1,7 @@ /* Configuration for an i386 running GNU with ELF as the target machine. */ /* -Copyright (C) 1994-2020 Free Software Foundation, Inc. +Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/haswell.md b/gcc/config/i386/haswell.md index a7273e5..617d54a 100644 --- a/gcc/config/i386/haswell.md +++ b/gcc/config/i386/haswell.md @@ -1,5 +1,5 @@ ;; Scheduling for Haswell and derived processors. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/host-cygwin.c b/gcc/config/i386/host-cygwin.c index 461b992..bbd59b4 100644 --- a/gcc/config/i386/host-cygwin.c +++ b/gcc/config/i386/host-cygwin.c @@ -1,5 +1,5 @@ /* Cygwin host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-i386-darwin.c b/gcc/config/i386/host-i386-darwin.c index b55847d..92afe96 100644 --- a/gcc/config/i386/host-i386-darwin.c +++ b/gcc/config/i386/host-i386-darwin.c @@ -1,5 +1,5 @@ /* i386-darwin host-specific hook definitions. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-mingw32.c b/gcc/config/i386/host-mingw32.c index 250fef5..360a280 100644 --- a/gcc/config/i386/host-mingw32.c +++ b/gcc/config/i386/host-mingw32.c @@ -1,5 +1,5 @@ /* mingw32 host-specific hook definitions. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/hresetintrin.h b/gcc/config/i386/hresetintrin.h index bdbe253..5006188 100644 --- a/gcc/config/i386/hresetintrin.h +++ b/gcc/config/i386/hresetintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-builtin-types.awk b/gcc/config/i386/i386-builtin-types.awk index 862438f..2d2a638 100644 --- a/gcc/config/i386/i386-builtin-types.awk +++ b/gcc/config/i386/i386-builtin-types.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2009-2020 Free Software Foundation, Inc. +# Copyright (C) 2009-2021 Free Software Foundation, Inc. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 67d5f2ef..e3ed4e1 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1,5 +1,5 @@ /* Builtin functions for ia32. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c index d8ec1e5..4fcdf4b 100644 --- a/gcc/config/i386/i386-builtins.c +++ b/gcc/config/i386/i386-builtins.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -1888,7 +1888,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) gcc_assert (new_target); if (new_target->arch_specified && new_target->arch > 0) - for (i = 0; i < (unsigned int) pta_size; i++) + for (i = 0; i < pta_size; i++) if (processor_alias_table[i].processor == new_target->arch) { const pta *arch_info = &processor_alias_table[i]; diff --git a/gcc/config/i386/i386-builtins.h b/gcc/config/i386/i386-builtins.h index a88cc0c..0641808 100644 --- a/gcc/config/i386/i386-builtins.h +++ b/gcc/config/i386/i386-builtins.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -236,10 +236,6 @@ struct builtin_isa { /* Bits for builtin_description.flag. */ -/* Set when we don't support the comparison natively, and should - swap_comparison in order to support it. */ -#define BUILTIN_DESC_SWAP_OPERANDS 1 - struct builtin_description { const HOST_WIDE_INT mask; diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 6d690e0..ed4b098 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on the ia-32. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -757,10 +757,8 @@ ix86_target_macros (void) if (TARGET_LONG_DOUBLE_128) cpp_define (parse_in, "__LONG_DOUBLE_128__"); - if (TARGET_128BIT_LONG_DOUBLE) - cpp_define (parse_in, "__SIZEOF_FLOAT80__=16"); - else - cpp_define (parse_in, "__SIZEOF_FLOAT80__=12"); + cpp_define_formatted (parse_in, "__SIZEOF_FLOAT80__=%d", + GET_MODE_SIZE (XFmode)); cpp_define (parse_in, "__SIZEOF_FLOAT128__=16"); @@ -780,8 +778,7 @@ ix86_target_macros (void) cpp_define (parse_in, "__SEG_GS"); if (flag_cf_protection != CF_NONE) - cpp_define_formatted (parse_in, "__CET__=%d", - flag_cf_protection & ~CF_SET); + cpp_define_formatted (parse_in, "__CET__=%d", flag_cf_protection & ~CF_SET); } diff --git a/gcc/config/i386/i386-d.c b/gcc/config/i386/i386-d.c index 56fec11..cbd3ceb 100644 --- a/gcc/config/i386/i386-d.c +++ b/gcc/config/i386/i386-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the x86 architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 7c31cc7..d64b4ac 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -3568,17 +3568,11 @@ ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) ? force_reg (mode, op_false) : op_false); if (op_true == CONST0_RTX (mode)) { - rtx (*gen_not) (rtx, rtx); - switch (cmpmode) - { - case E_QImode: gen_not = gen_knotqi; break; - case E_HImode: gen_not = gen_knothi; break; - case E_SImode: gen_not = gen_knotsi; break; - case E_DImode: gen_not = gen_knotdi; break; - default: gcc_unreachable (); - } rtx n = gen_reg_rtx (cmpmode); - emit_insn (gen_not (n, cmp)); + if (cmpmode == E_DImode && !TARGET_64BIT) + emit_insn (gen_knotdi (n, cmp)); + else + emit_insn (gen_rtx_SET (n, gen_rtx_fmt_e (NOT, cmpmode, cmp))); cmp = n; /* Reverse op_true op_false. */ std::swap (op_true, op_false); @@ -8634,11 +8628,6 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree exp, if (VECTOR_MODE_P (mode1)) op1 = safe_vector_operand (op1, mode1); - /* Swap operands if we have a comparison that isn't available in - hardware. */ - if (d->flag & BUILTIN_DESC_SWAP_OPERANDS) - std::swap (op0, op1); - target = gen_reg_rtx (SImode); emit_move_insn (target, const0_rtx); target = gen_rtx_SUBREG (QImode, target, 0); @@ -16214,8 +16203,8 @@ void ix86_expand_lround (rtx op0, rtx op1) { /* C code for the stuff we're doing below: - tmp = op1 + copysign (nextafter (0.5, 0.0), op1) - return (long)tmp; + tmp = op1 + copysign (nextafter (0.5, 0.0), op1) + return (long)tmp; */ machine_mode mode = GET_MODE (op1); const struct real_format *fmt; @@ -16246,8 +16235,8 @@ ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor) { /* C code for the stuff we're doing below (for do_floor): xi = (long)op1; - xi -= (double)xi > op1 ? 1 : 0; - return xi; + xi -= (double)xi > op1 ? 1 : 0; + return xi; */ machine_mode fmode = GET_MODE (op1); machine_mode imode = GET_MODE (op0); @@ -16281,10 +16270,12 @@ ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor) static rtx ix86_gen_TWO52 (machine_mode mode) { + const struct real_format *fmt; REAL_VALUE_TYPE TWO52r; rtx TWO52; - real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23); + fmt = REAL_MODE_FORMAT (mode); + real_2expN (&TWO52r, fmt->p - 1, mode); TWO52 = const_double_from_real_value (TWO52r, mode); TWO52 = force_reg (mode, TWO52); @@ -16298,41 +16289,45 @@ ix86_expand_rint (rtx operand0, rtx operand1) { /* C code for the stuff we're doing below: xa = fabs (operand1); - if (!isless (xa, 2**52)) + if (!isless (xa, 2**52)) return operand1; - two52 = 2**52; - if (flag_rounding_math) + two52 = 2**52; + if (flag_rounding_math) { two52 = copysign (two52, operand1); xa = operand1; } - xa = xa + two52 - two52; - return copysign (xa, operand1); + xa = xa + two52 - two52; + return copysign (xa, operand1); */ machine_mode mode = GET_MODE (operand0); - rtx res, xa, TWO52, two52, mask; + rtx res, xa, TWO52, mask; rtx_code_label *label; - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + TWO52 = ix86_gen_TWO52 (mode); + + /* Temporary for holding the result, initialized to the input + operand to ease control flow. */ + res = copy_to_reg (operand1); /* xa = abs (operand1) */ xa = ix86_expand_sse_fabs (res, &mask); /* if (!isless (xa, TWO52)) goto label; */ - TWO52 = ix86_gen_TWO52 (mode); label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false); - two52 = TWO52; if (flag_rounding_math) { - two52 = gen_reg_rtx (mode); - ix86_sse_copysign_to_positive (two52, TWO52, res, mask); + ix86_sse_copysign_to_positive (TWO52, TWO52, res, mask); xa = res; } - xa = expand_simple_binop (mode, PLUS, xa, two52, NULL_RTX, 0, OPTAB_DIRECT); - xa = expand_simple_binop (mode, MINUS, xa, two52, xa, 0, OPTAB_DIRECT); + xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT); + xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT); + + /* Remove the sign with FE_DOWNWARD, where x - x = -0.0. */ + if (HONOR_SIGNED_ZEROS (mode) && flag_rounding_math) + xa = ix86_expand_sse_fabs (xa, NULL); ix86_sse_copysign_to_positive (res, xa, res, mask); @@ -16349,15 +16344,17 @@ ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor) { /* C code for the stuff we expand below. double xa = fabs (x), x2; - if (!isless (xa, TWO52)) - return x; + if (!isless (xa, TWO52)) + return x; x2 = (double)(long)x; + Compensate. Floor: if (x2 > x) x2 -= 1; Compensate. Ceil: if (x2 < x) x2 += 1; + if (HONOR_SIGNED_ZEROS (mode)) return copysign (x2, x); return x2; @@ -16370,8 +16367,7 @@ ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor) /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res = copy_to_reg (operand1); /* xa = abs (operand1) */ xa = ix86_expand_sse_fabs (res, &mask); @@ -16380,7 +16376,7 @@ ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor) label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false); /* xa = (double)(long)x */ - xi = gen_reg_rtx (mode == DFmode ? DImode : SImode); + xi = gen_reg_rtx (int_mode_for_mode (mode).require ()); expand_fix (xi, res, 0); expand_float (xa, xi, 0); @@ -16392,10 +16388,15 @@ ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor) emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (mode, one, tmp))); tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS, xa, tmp, NULL_RTX, 0, OPTAB_DIRECT); - emit_move_insn (res, tmp); - if (HONOR_SIGNED_ZEROS (mode)) - ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask); + { + /* Remove the sign with FE_DOWNWARD, where x - x = -0.0. */ + if (do_floor && flag_rounding_math) + tmp = ix86_expand_sse_fabs (tmp, NULL); + + ix86_sse_copysign_to_positive (tmp, tmp, res, mask); + } + emit_move_insn (res, tmp); emit_label (label); LABEL_NUSES (label) = 1; @@ -16410,17 +16411,19 @@ void ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor) { /* C code for the stuff we expand below. - double xa = fabs (x), x2; - if (!isless (xa, TWO52)) - return x; - xa = xa + TWO52 - TWO52; - x2 = copysign (xa, x); + double xa = fabs (x), x2; + if (!isless (xa, TWO52)) + return x; + xa = xa + TWO52 - TWO52; + x2 = copysign (xa, x); + Compensate. Floor: - if (x2 > x) - x2 -= 1; + if (x2 > x) + x2 -= 1; Compensate. Ceil: - if (x2 < x) - x2 += 1; + if (x2 < x) + x2 += 1; + if (HONOR_SIGNED_ZEROS (mode)) x2 = copysign (x2, x); return x2; @@ -16433,8 +16436,7 @@ ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor) /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res = copy_to_reg (operand1); /* xa = abs (operand1) */ xa = ix86_expand_sse_fabs (res, &mask); @@ -16457,8 +16459,14 @@ ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor) emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (mode, one, tmp))); tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS, xa, tmp, NULL_RTX, 0, OPTAB_DIRECT); - if (!do_floor && HONOR_SIGNED_ZEROS (mode)) - ix86_sse_copysign_to_positive (tmp, tmp, res, mask); + if (HONOR_SIGNED_ZEROS (mode)) + { + /* Remove the sign with FE_DOWNWARD, where x - x = -0.0. */ + if (do_floor && flag_rounding_math) + tmp = ix86_expand_sse_fabs (tmp, NULL); + + ix86_sse_copysign_to_positive (tmp, tmp, res, mask); + } emit_move_insn (res, tmp); emit_label (label); @@ -16473,10 +16481,10 @@ void ix86_expand_trunc (rtx operand0, rtx operand1) { /* C code for SSE variant we expand below. - double xa = fabs (x), x2; - if (!isless (xa, TWO52)) - return x; - x2 = (double)(long)x; + double xa = fabs (x), x2; + if (!isless (xa, TWO52)) + return x; + x2 = (double)(long)x; if (HONOR_SIGNED_ZEROS (mode)) return copysign (x2, x); return x2; @@ -16489,8 +16497,7 @@ ix86_expand_trunc (rtx operand0, rtx operand1) /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res = copy_to_reg (operand1); /* xa = abs (operand1) */ xa = ix86_expand_sse_fabs (res, &mask); @@ -16498,13 +16505,15 @@ ix86_expand_trunc (rtx operand0, rtx operand1) /* if (!isless (xa, TWO52)) goto label; */ label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false); - /* x = (double)(long)x */ - xi = gen_reg_rtx (mode == DFmode ? DImode : SImode); + /* xa = (double)(long)x */ + xi = gen_reg_rtx (int_mode_for_mode (mode).require ()); expand_fix (xi, res, 0); - expand_float (res, xi, 0); + expand_float (xa, xi, 0); if (HONOR_SIGNED_ZEROS (mode)) - ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask); + ix86_sse_copysign_to_positive (xa, xa, res, mask); + + emit_move_insn (res, xa); emit_label (label); LABEL_NUSES (label) = 1; @@ -16519,51 +16528,51 @@ void ix86_expand_truncdf_32 (rtx operand0, rtx operand1) { machine_mode mode = GET_MODE (operand0); - rtx xa, mask, TWO52, one, res, smask, tmp; + rtx xa, xa2, TWO52, tmp, one, res, mask; rtx_code_label *label; /* C code for SSE variant we expand below. - double xa = fabs (x), x2; - if (!isless (xa, TWO52)) - return x; - xa2 = xa + TWO52 - TWO52; + double xa = fabs (x), x2; + if (!isless (xa, TWO52)) + return x; + xa2 = xa + TWO52 - TWO52; Compensate: - if (xa2 > xa) - xa2 -= 1.0; - x2 = copysign (xa2, x); - return x2; + if (xa2 > xa) + xa2 -= 1.0; + x2 = copysign (xa2, x); + return x2; */ TWO52 = ix86_gen_TWO52 (mode); /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res =copy_to_reg (operand1); /* xa = abs (operand1) */ - xa = ix86_expand_sse_fabs (res, &smask); + xa = ix86_expand_sse_fabs (res, &mask); /* if (!isless (xa, TWO52)) goto label; */ label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false); - /* res = xa + TWO52 - TWO52; */ - tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT); - tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT); - emit_move_insn (res, tmp); + /* xa2 = xa + TWO52 - TWO52; */ + xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT); + xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT); /* generate 1.0 */ one = force_reg (mode, const_double_from_real_value (dconst1, mode)); - /* Compensate: res = xa2 - (res > xa ? 1 : 0) */ - mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false); - emit_insn (gen_rtx_SET (mask, gen_rtx_AND (mode, mask, one))); + /* Compensate: xa2 = xa2 - (xa2 > xa ? 1 : 0) */ + tmp = ix86_expand_sse_compare_mask (UNGT, xa2, xa, false); + emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (mode, one, tmp))); tmp = expand_simple_binop (mode, MINUS, - res, mask, NULL_RTX, 0, OPTAB_DIRECT); - emit_move_insn (res, tmp); + xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT); + /* Remove the sign with FE_DOWNWARD, where x - x = -0.0. */ + if (HONOR_SIGNED_ZEROS (mode) && flag_rounding_math) + tmp = ix86_expand_sse_fabs (tmp, NULL); - /* res = copysign (res, operand1) */ - ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask); + /* res = copysign (xa2, operand1) */ + ix86_sse_copysign_to_positive (res, tmp, res, mask); emit_label (label); LABEL_NUSES (label) = 1; @@ -16577,11 +16586,11 @@ void ix86_expand_round (rtx operand0, rtx operand1) { /* C code for the stuff we're doing below: - double xa = fabs (x); - if (!isless (xa, TWO52)) - return x; - xa = (double)(long)(xa + nextafter (0.5, 0.0)); - return copysign (xa, x); + double xa = fabs (x); + if (!isless (xa, TWO52)) + return x; + xa = (double)(long)(xa + nextafter (0.5, 0.0)); + return copysign (xa, x); */ machine_mode mode = GET_MODE (operand0); rtx res, TWO52, xa, xi, half, mask; @@ -16591,8 +16600,7 @@ ix86_expand_round (rtx operand0, rtx operand1) /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res = copy_to_reg (operand1); TWO52 = ix86_gen_TWO52 (mode); xa = ix86_expand_sse_fabs (res, &mask); @@ -16608,12 +16616,12 @@ ix86_expand_round (rtx operand0, rtx operand1) xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT); /* xa = (double)(int64_t)xa */ - xi = gen_reg_rtx (mode == DFmode ? DImode : SImode); + xi = gen_reg_rtx (int_mode_for_mode (mode).require ()); expand_fix (xi, xa, 0); expand_float (xa, xi, 0); /* res = copysign (xa, operand1) */ - ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask); + ix86_sse_copysign_to_positive (res, xa, res, mask); emit_label (label); LABEL_NUSES (label) = 1; @@ -16628,20 +16636,20 @@ void ix86_expand_rounddf_32 (rtx operand0, rtx operand1) { /* C code for the stuff we expand below. - double xa = fabs (x), xa2, x2; - if (!isless (xa, TWO52)) - return x; + double xa = fabs (x), xa2, x2; + if (!isless (xa, TWO52)) + return x; Using the absolute value and copying back sign makes -0.0 -> -0.0 correct. - xa2 = xa + TWO52 - TWO52; + xa2 = xa + TWO52 - TWO52; Compensate. dxa = xa2 - xa; - if (dxa <= -0.5) - xa2 += 1; - else if (dxa > 0.5) - xa2 -= 1; - x2 = copysign (xa2, x); - return x2; + if (dxa <= -0.5) + xa2 += 1; + else if (dxa > 0.5) + xa2 -= 1; + x2 = copysign (xa2, x); + return x2; */ machine_mode mode = GET_MODE (operand0); rtx xa, xa2, dxa, TWO52, tmp, half, mhalf, one, res, mask; @@ -16651,8 +16659,7 @@ ix86_expand_rounddf_32 (rtx operand0, rtx operand1) /* Temporary for holding the result, initialized to the input operand to ease control flow. */ - res = gen_reg_rtx (mode); - emit_move_insn (res, operand1); + res = copy_to_reg (operand1); /* xa = abs (operand1) */ xa = ix86_expand_sse_fabs (res, &mask); @@ -16684,7 +16691,7 @@ ix86_expand_rounddf_32 (rtx operand0, rtx operand1) xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT); /* res = copysign (xa2, operand1) */ - ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask); + ix86_sse_copysign_to_positive (res, xa2, res, mask); emit_label (label); LABEL_NUSES (label) = 1; @@ -19916,6 +19923,32 @@ ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, two_args = canonicalize_perm (&d); + /* If one of the operands is a zero vector, try to match pmovzx. */ + if (two_args && (d.op0 == CONST0_RTX (vmode) || d.op1 == CONST0_RTX (vmode))) + { + struct expand_vec_perm_d dzero = d; + if (d.op0 == CONST0_RTX (vmode)) + { + d.op1 = dzero.op1 = force_reg (vmode, d.op1); + std::swap (dzero.op0, dzero.op1); + for (i = 0; i < nelt; ++i) + dzero.perm[i] ^= nelt; + } + else + d.op0 = dzero.op0 = force_reg (vmode, d.op0); + + if (expand_vselect_vconcat (dzero.target, dzero.op0, dzero.op1, + dzero.perm, nelt, dzero.testing_p)) + return true; + } + + /* Force operands into registers. */ + rtx nop0 = force_reg (vmode, d.op0); + if (d.op0 == d.op1) + d.op1 = nop0; + d.op0 = nop0; + d.op1 = force_reg (vmode, d.op1); + if (ix86_expand_vec_perm_const_1 (&d)) return true; diff --git a/gcc/config/i386/i386-expand.h b/gcc/config/i386/i386-expand.h index 76815c0..c879f08 100644 --- a/gcc/config/i386/i386-expand.h +++ b/gcc/config/i386/i386-expand.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c index c61685b..41891c9 100644 --- a/gcc/config/i386/i386-features.c +++ b/gcc/config/i386/i386-features.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -1627,7 +1627,7 @@ convert_scalars_to_vector (bool timode_p) bitmap_initialize (&candidates[i], &bitmap_default_obstack); calculate_dominance_info (CDI_DOMINATORS); - df_set_flags (DF_DEFER_INSN_RESCAN); + df_set_flags (DF_DEFER_INSN_RESCAN | DF_RD_PRUNE_DEAD_DEFS); df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN); df_analyze (); @@ -2272,6 +2272,9 @@ remove_partial_avx_dependency (void) auto_vec<rtx_insn *> control_flow_insns; + /* We create invalid RTL initially so defer rescans. */ + df_set_flags (DF_DEFER_INSN_RESCAN); + FOR_EACH_BB_FN (bb, cfun) { FOR_BB_INSNS (bb, insn) @@ -2292,14 +2295,7 @@ remove_partial_avx_dependency (void) continue; if (!v4sf_const0) - { - calculate_dominance_info (CDI_DOMINATORS); - df_set_flags (DF_DEFER_INSN_RESCAN); - df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN); - df_md_add_problem (); - df_analyze (); - v4sf_const0 = gen_reg_rtx (V4SFmode); - } + v4sf_const0 = gen_reg_rtx (V4SFmode); /* Convert PARTIAL_XMM_UPDATE_TRUE insns, DF -> SF, SF -> DF, SI -> SF, SI -> DF, DI -> SF, DI -> DF, to vec_dup and @@ -2360,6 +2356,7 @@ remove_partial_avx_dependency (void) { /* (Re-)discover loops so that bb->loop_father can be used in the analysis below. */ + calculate_dominance_info (CDI_DOMINATORS); loop_optimizer_init (AVOID_CFG_MODIFICATIONS); /* Generate a vxorps at entry of the nearest dominator for basic @@ -2391,7 +2388,6 @@ remove_partial_avx_dependency (void) set_insn = emit_insn_after (set, insn ? PREV_INSN (insn) : BB_END (bb)); df_insn_rescan (set_insn); - df_process_deferred_rescans (); loop_optimizer_finalize (); if (!control_flow_insns.is_empty ()) @@ -2412,6 +2408,8 @@ remove_partial_avx_dependency (void) } } + df_process_deferred_rescans (); + df_clear_flags (DF_DEFER_INSN_RESCAN); bitmap_obstack_release (NULL); BITMAP_FREE (convert_bbs); @@ -2441,7 +2439,7 @@ const pass_data pass_data_remove_partial_avx_dependency = 0, /* properties_provided */ 0, /* properties_destroyed */ 0, /* todo_flags_start */ - TODO_df_finish, /* todo_flags_finish */ + 0, /* todo_flags_finish */ }; class pass_remove_partial_avx_dependency : public rtl_opt_pass diff --git a/gcc/config/i386/i386-features.h b/gcc/config/i386/i386-features.h index ee6b10f..a896e99 100644 --- a/gcc/config/i386/i386-features.h +++ b/gcc/config/i386/i386-features.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index 4278bb8..dbddfd8 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 40714c8..a70f6ed 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -641,7 +641,7 @@ ix86_function_specific_save (struct cl_target_option *ptr, { ptr->arch = ix86_arch; ptr->schedule = ix86_schedule; - ptr->prefetch_sse = x86_prefetch_sse; + ptr->prefetch_sse = ix86_prefetch_sse; ptr->tune = ix86_tune; ptr->branch_cost = ix86_branch_cost; ptr->tune_defaulted = ix86_tune_defaulted; @@ -651,18 +651,13 @@ ix86_function_specific_save (struct cl_target_option *ptr, ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit; ptr->x_ix86_arch_string = opts->x_ix86_arch_string; ptr->x_ix86_tune_string = opts->x_ix86_tune_string; - ptr->x_ix86_cmodel = opts->x_ix86_cmodel; ptr->x_ix86_abi = opts->x_ix86_abi; ptr->x_ix86_asm_dialect = opts->x_ix86_asm_dialect; ptr->x_ix86_branch_cost = opts->x_ix86_branch_cost; ptr->x_ix86_dump_tunes = opts->x_ix86_dump_tunes; ptr->x_ix86_force_align_arg_pointer = opts->x_ix86_force_align_arg_pointer; ptr->x_ix86_force_drap = opts->x_ix86_force_drap; - ptr->x_ix86_incoming_stack_boundary_arg = opts->x_ix86_incoming_stack_boundary_arg; - ptr->x_ix86_pmode = opts->x_ix86_pmode; - ptr->x_ix86_preferred_stack_boundary_arg = opts->x_ix86_preferred_stack_boundary_arg; ptr->x_ix86_recip_name = opts->x_ix86_recip_name; - ptr->x_ix86_regparm = opts->x_ix86_regparm; ptr->x_ix86_section_threshold = opts->x_ix86_section_threshold; ptr->x_ix86_sse2avx = opts->x_ix86_sse2avx; ptr->x_ix86_stack_protector_guard = opts->x_ix86_stack_protector_guard; @@ -672,7 +667,6 @@ ix86_function_specific_save (struct cl_target_option *ptr, ptr->x_ix86_tune_memcpy_strategy = opts->x_ix86_tune_memcpy_strategy; ptr->x_ix86_tune_memset_strategy = opts->x_ix86_tune_memset_strategy; ptr->x_ix86_tune_no_default = opts->x_ix86_tune_no_default; - ptr->x_ix86_veclibabi_type = opts->x_ix86_veclibabi_type; /* The fields are char but the variables are not; make sure the values fit in the fields. */ @@ -779,8 +773,7 @@ ix86_function_specific_restore (struct gcc_options *opts, ix86_arch = (enum processor_type) ptr->arch; ix86_schedule = (enum attr_cpu) ptr->schedule; ix86_tune = (enum processor_type) ptr->tune; - x86_prefetch_sse = ptr->prefetch_sse; - opts->x_ix86_branch_cost = ptr->branch_cost; + ix86_prefetch_sse = ptr->prefetch_sse; ix86_tune_defaulted = ptr->tune_defaulted; ix86_arch_specified = ptr->arch_specified; opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit; @@ -788,18 +781,13 @@ ix86_function_specific_restore (struct gcc_options *opts, opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit; opts->x_ix86_arch_string = ptr->x_ix86_arch_string; opts->x_ix86_tune_string = ptr->x_ix86_tune_string; - opts->x_ix86_cmodel = ptr->x_ix86_cmodel; opts->x_ix86_abi = ptr->x_ix86_abi; opts->x_ix86_asm_dialect = ptr->x_ix86_asm_dialect; opts->x_ix86_branch_cost = ptr->x_ix86_branch_cost; opts->x_ix86_dump_tunes = ptr->x_ix86_dump_tunes; opts->x_ix86_force_align_arg_pointer = ptr->x_ix86_force_align_arg_pointer; opts->x_ix86_force_drap = ptr->x_ix86_force_drap; - opts->x_ix86_incoming_stack_boundary_arg = ptr->x_ix86_incoming_stack_boundary_arg; - opts->x_ix86_pmode = ptr->x_ix86_pmode; - opts->x_ix86_preferred_stack_boundary_arg = ptr->x_ix86_preferred_stack_boundary_arg; opts->x_ix86_recip_name = ptr->x_ix86_recip_name; - opts->x_ix86_regparm = ptr->x_ix86_regparm; opts->x_ix86_section_threshold = ptr->x_ix86_section_threshold; opts->x_ix86_sse2avx = ptr->x_ix86_sse2avx; opts->x_ix86_stack_protector_guard = ptr->x_ix86_stack_protector_guard; @@ -809,7 +797,6 @@ ix86_function_specific_restore (struct gcc_options *opts, opts->x_ix86_tune_memcpy_strategy = ptr->x_ix86_tune_memcpy_strategy; opts->x_ix86_tune_memset_strategy = ptr->x_ix86_tune_memset_strategy; opts->x_ix86_tune_no_default = ptr->x_ix86_tune_no_default; - opts->x_ix86_veclibabi_type = ptr->x_ix86_veclibabi_type; ix86_tune_cost = processor_cost_table[ix86_tune]; /* TODO: ix86_cost should be chosen at instruction or function granuality so for cold code we use size_cost even in !optimize_size compilation. */ @@ -1101,8 +1088,6 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], /* If this is a list, recurse to get the options. */ if (TREE_CODE (args) == TREE_LIST) { - bool ret = true; - for (; args; args = TREE_CHAIN (args)) if (TREE_VALUE (args) && !ix86_valid_target_attribute_inner_p (fndecl, TREE_VALUE (args), @@ -1374,6 +1359,14 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, /* Add any builtin functions with the new isa if any. */ ix86_add_new_builtins (opts->x_ix86_isa_flags, opts->x_ix86_isa_flags2); + enum excess_precision orig_ix86_excess_precision + = opts->x_ix86_excess_precision; + bool orig_ix86_unsafe_math_optimizations + = opts->x_ix86_unsafe_math_optimizations; + opts->x_ix86_excess_precision = opts->x_flag_excess_precision; + opts->x_ix86_unsafe_math_optimizations + = opts->x_flag_unsafe_math_optimizations; + /* Save the current options unless we are validating options for #pragma. */ t = build_target_option_node (opts, opts_set); @@ -1382,6 +1375,9 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, opts->x_ix86_tune_string = orig_tune_string; opts_set->x_ix86_fpmath = orig_fpmath_set; opts_set->x_prefer_vector_width_type = orig_pvw_set; + opts->x_ix86_excess_precision = orig_ix86_excess_precision; + opts->x_ix86_unsafe_math_optimizations + = orig_ix86_unsafe_math_optimizations; release_options_strings (option_strings); } @@ -1784,7 +1780,7 @@ ix86_option_override_internal (bool main_args_p, struct gcc_options *opts, struct gcc_options *opts_set) { - int i; + unsigned int i; unsigned HOST_WIDE_INT ix86_arch_mask; const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL); @@ -1873,9 +1869,7 @@ ix86_option_override_internal (bool main_args_p, as -mtune=generic. With native compilers we won't see the -mtune=native, as it was changed by the driver. */ if (!strcmp (opts->x_ix86_tune_string, "native")) - { - opts->x_ix86_tune_string = "generic"; - } + opts->x_ix86_tune_string = "generic"; else if (!strcmp (opts->x_ix86_tune_string, "x86-64")) warning (OPT_Wdeprecated, main_args_p @@ -1897,10 +1891,12 @@ ix86_option_override_internal (bool main_args_p, /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string or defaulted. We need to use a sensible tune option. */ - if (!strcmp (opts->x_ix86_tune_string, "x86-64")) - { - opts->x_ix86_tune_string = "generic"; - } + if (!strncmp (opts->x_ix86_tune_string, "x86-64", 6) + && (opts->x_ix86_tune_string[6] == '\0' + || (!strcmp (opts->x_ix86_tune_string + 6, "-v2") + || !strcmp (opts->x_ix86_tune_string + 6, "-v3") + || !strcmp (opts->x_ix86_tune_string + 6, "-v4")))) + opts->x_ix86_tune_string = "generic"; } if (opts->x_ix86_stringop_alg == rep_prefix_8_byte @@ -2073,17 +2069,6 @@ ix86_option_override_internal (bool main_args_p, return false; } - /* The feature-only micro-architecture levels that use - PTA_NO_TUNE are only defined for the x86-64 psABI. */ - if ((processor_alias_table[i].flags & PTA_NO_TUNE) != 0 - && (!TARGET_64BIT_P (opts->x_ix86_isa_flags) - || opts->x_ix86_abi != SYSV_ABI)) - { - error (G_("%qs architecture level is only defined" - " for the x86-64 psABI"), opts->x_ix86_arch_string); - return false; - } - ix86_schedule = processor_alias_table[i].schedule; ix86_arch = processor_alias_table[i].processor; @@ -2360,7 +2345,7 @@ ix86_option_override_internal (bool main_args_p, if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) - x86_prefetch_sse = true; + ix86_prefetch_sse = true; if (((processor_alias_table[i].flags & PTA_MWAITX) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_MWAITX)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX; @@ -2458,7 +2443,7 @@ ix86_option_override_internal (bool main_args_p, if (TARGET_CMOV && ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0)) - x86_prefetch_sse = true; + ix86_prefetch_sse = true; break; } @@ -2601,7 +2586,7 @@ ix86_option_override_internal (bool main_args_p, || (TARGET_PRFCHW_P (opts->x_ix86_isa_flags) && !TARGET_3DNOW_P (opts->x_ix86_isa_flags)) || TARGET_PREFETCHWT1_P (opts->x_ix86_isa_flags)) - x86_prefetch_sse = true; + ix86_prefetch_sse = true; /* Enable popcnt instruction for -msse4.2 or -mabm. */ if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags) @@ -2865,7 +2850,7 @@ ix86_option_override_internal (bool main_args_p, { char *p = ASTRDUP (opts->x_ix86_recip_name); char *q; - unsigned int mask, i; + unsigned int mask; bool invert; while ((q = strtok (p, ",")) != NULL) @@ -3019,12 +3004,24 @@ ix86_option_override_internal (bool main_args_p, /* Save the initial options in case the user does function specific options. */ if (main_args_p) - target_option_default_node = target_option_current_node - = build_target_option_node (opts, opts_set); + { + opts->x_ix86_excess_precision + = opts->x_flag_excess_precision; + opts->x_ix86_unsafe_math_optimizations + = opts->x_flag_unsafe_math_optimizations; + target_option_default_node = target_option_current_node + = build_target_option_node (opts, opts_set); + } if (opts->x_flag_cf_protection != CF_NONE) - opts->x_flag_cf_protection + { + if ((opts->x_flag_cf_protection & CF_BRANCH) == CF_BRANCH + && !TARGET_64BIT && !TARGET_CMOV) + error ("%<-fcf-protection%> is not compatible with this target"); + + opts->x_flag_cf_protection = (cf_protection_level) (opts->x_flag_cf_protection | CF_SET); + } if (ix86_tune_features [X86_TUNE_AVOID_256FMA_CHAINS]) SET_OPTION_IF_UNSET (opts, opts_set, param_avoid_fma_max_bits, 256); @@ -3326,6 +3323,24 @@ ix86_set_current_function (tree fndecl) else TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts (); } + else if (flag_unsafe_math_optimizations + != TREE_TARGET_OPTION (new_tree)->x_ix86_unsafe_math_optimizations + || (flag_excess_precision + != TREE_TARGET_OPTION (new_tree)->x_ix86_excess_precision)) + { + cl_target_option_restore (&global_options, &global_options_set, + TREE_TARGET_OPTION (new_tree)); + ix86_excess_precision = flag_excess_precision; + ix86_unsafe_math_optimizations = flag_unsafe_math_optimizations; + DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_tree + = build_target_option_node (&global_options, &global_options_set); + if (TREE_TARGET_GLOBALS (new_tree)) + restore_target_globals (TREE_TARGET_GLOBALS (new_tree)); + else if (new_tree == target_option_default_node) + restore_target_globals (&default_target_globals); + else + TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts (); + } ix86_previous_fndecl = fndecl; static bool prev_no_caller_saved_registers; diff --git a/gcc/config/i386/i386-options.h b/gcc/config/i386/i386-options.h index 9172936..cdaca26 100644 --- a/gcc/config/i386/i386-options.h +++ b/gcc/config/i386/i386-options.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1988-2020 Free Software Foundation, Inc. +/* Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -33,7 +33,7 @@ extern enum attr_cpu ix86_schedule; extern enum processor_type ix86_tune; extern enum processor_type ix86_arch; -extern unsigned char x86_prefetch_sse; +extern unsigned char ix86_prefetch_sse; extern const struct processor_costs *ix86_tune_cost; extern int ix86_tune_defaulted; diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index b40317b..de6e7e0 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IA-32. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-passes.def b/gcc/config/i386/i386-passes.def index 07ecf8e..44df00e 100644 --- a/gcc/config/i386/i386-passes.def +++ b/gcc/config/i386/i386-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for IA-32 - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 65347a5..9f8a69e 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3a57710..48f9aa0 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IA-32. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -347,7 +347,7 @@ enum processor_type ix86_tune; enum processor_type ix86_arch; /* True if processor has SSE prefetch instruction. */ -unsigned char x86_prefetch_sse; +unsigned char ix86_prefetch_sse; /* Preferred alignment for stack boundary in bits. */ unsigned int ix86_preferred_stack_boundary; @@ -20794,8 +20794,38 @@ x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) fprintf (file, "\tleaq\t%sP%d(%%rip),%%r11\n", LPREFIX, labelno); #endif - if (!TARGET_PECOFF && flag_pic) - fprintf (file, "1:\tcall\t*%s@GOTPCREL(%%rip)\n", mcount_name); + if (!TARGET_PECOFF) + { + switch (ix86_cmodel) + { + case CM_LARGE: + /* NB: R10 is caller-saved. Although it can be used as a + static chain register, it is preserved when calling + mcount for nested functions. */ + fprintf (file, "1:\tmovabsq\t$%s, %%r10\n\tcall\t*%%r10\n", + mcount_name); + break; + case CM_LARGE_PIC: +#ifdef NO_PROFILE_COUNTERS + fprintf (file, "1:\tmovabsq\t$_GLOBAL_OFFSET_TABLE_-1b, %%r11\n"); + fprintf (file, "\tleaq\t1b(%%rip), %%r10\n"); + fprintf (file, "\taddq\t%%r11, %%r10\n"); + fprintf (file, "\tmovabsq\t$%s@PLTOFF, %%r11\n", mcount_name); + fprintf (file, "\taddq\t%%r11, %%r10\n"); + fprintf (file, "\tcall\t*%%r10\n"); +#else + sorry ("profiling %<-mcmodel=large%> with PIC is not supported"); +#endif + break; + case CM_SMALL_PIC: + case CM_MEDIUM_PIC: + fprintf (file, "1:\tcall\t*%s@GOTPCREL(%%rip)\n", mcount_name); + break; + default: + x86_print_call_or_nop (file, mcount_name); + break; + } + } else x86_print_call_or_nop (file, mcount_name); } @@ -23001,7 +23031,7 @@ ix86_init_libfuncs (void) apparently at random. */ static enum flt_eval_method -ix86_excess_precision (enum excess_precision_type type) +ix86_get_excess_precision (enum excess_precision_type type) { switch (type) { @@ -23527,7 +23557,7 @@ ix86_run_selftests (void) #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust #undef TARGET_C_EXCESS_PRECISION -#define TARGET_C_EXCESS_PRECISION ix86_excess_precision +#define TARGET_C_EXCESS_PRECISION ix86_get_excess_precision #undef TARGET_PROMOTE_PROTOTYPES #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true #undef TARGET_SETUP_INCOMING_VARARGS diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 5680fdc..272b195 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -654,8 +654,8 @@ extern unsigned char ix86_arch_features[X86_ARCH_LAST]; #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) -extern unsigned char x86_prefetch_sse; -#define TARGET_PREFETCH_SSE x86_prefetch_sse +extern unsigned char ix86_prefetch_sse; +#define TARGET_PREFETCH_SSE ix86_prefetch_sse #define ASSEMBLER_DIALECT (ix86_asm_dialect) @@ -829,15 +829,15 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); SFmode, DFmode and XFmode) in the current excess precision configuration. */ #define X87_ENABLE_ARITH(MODE) \ - (flag_unsafe_math_optimizations \ - || flag_excess_precision == EXCESS_PRECISION_FAST \ + (ix86_unsafe_math_optimizations \ + || ix86_excess_precision == EXCESS_PRECISION_FAST \ || (MODE) == XFmode) /* Likewise, whether to allow direct conversions from integer mode IMODE (HImode, SImode or DImode) to MODE. */ #define X87_ENABLE_FLOAT(MODE, IMODE) \ - (flag_unsafe_math_optimizations \ - || flag_excess_precision == EXCESS_PRECISION_FAST \ + (ix86_unsafe_math_optimizations \ + || ix86_excess_precision == EXCESS_PRECISION_FAST \ || (MODE) == XFmode \ || ((MODE) == DFmode && (IMODE) == SImode) \ || (IMODE) == HImode) @@ -1163,22 +1163,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1, 1, 1, 1, 1, 1, 1, 1 } -/* Order in which to allocate registers. Each register must be - listed once, even those in FIXED_REGISTERS. List frame pointer - late and fixed registers last. Note that, in general, we prefer - registers listed in CALL_USED_REGISTERS, keeping the others - available for storage of persistent values. - - The ADJUST_REG_ALLOC_ORDER actually overwrite the order, - so this is just empty initializer for array. */ - -#define REG_ALLOC_ORDER \ -{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ - 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 } - /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order to be rearranged based on a particular function. When using sse math, we want to allocate SSE before x87 registers and vice versa. */ @@ -2578,7 +2562,7 @@ public: }; extern const pta processor_alias_table[]; -extern int const pta_size; +extern unsigned int const pta_size; extern unsigned int const num_arch_names; #endif diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 21f0044..b60784a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1,5 +1,5 @@ ;; GCC machine description for IA-32 and x86-64. -;; Copyright (C) 1988-2020 Free Software Foundation, Inc. +;; Copyright (C) 1988-2021 Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; x86_64 support added by Jan Hubicka ;; @@ -869,7 +869,8 @@ (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") (eq_attr "isa" "avxvnni") (symbol_ref "TARGET_AVXVNNI") - (eq_attr "isa" "avx512vnnivl") (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL") + (eq_attr "isa" "avx512vnnivl") + (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL") (eq_attr "mmx_isa" "native") (symbol_ref "!TARGET_MMX_WITH_SSE") @@ -894,17 +895,13 @@ (define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) -(define_code_iterator multdiv [mult div]) - -;; Base name for define_insn -(define_code_attr plusminus_insn - [(plus "add") (ss_plus "ssadd") (us_plus "usadd") - (minus "sub") (ss_minus "sssub") (us_minus "ussub")]) - ;; Base name for insn mnemonic. (define_code_attr plusminus_mnemonic [(plus "add") (ss_plus "adds") (us_plus "addus") (minus "sub") (ss_minus "subs") (us_minus "subus")]) + +(define_code_iterator multdiv [mult div]) + (define_code_attr multdiv_mnemonic [(mult "mul") (div "div")]) @@ -951,10 +948,6 @@ ;; Mapping of all shift operators (define_code_iterator any_shift [ashift lshiftrt ashiftrt]) -;; Base name for define_insn -(define_code_attr shift_insn - [(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")]) - ;; Base name for insn mnemonic. (define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")]) (define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")]) @@ -962,9 +955,6 @@ ;; Mapping of rotate operators (define_code_iterator any_rotate [rotate rotatert]) -;; Base name for define_insn -(define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")]) - ;; Base name for insn mnemonic. (define_code_attr rotate [(rotate "rol") (rotatert "ror")]) @@ -977,7 +967,7 @@ ;; Base name for x87 insn mnemonic. (define_code_attr absneg_mnemonic [(abs "fabs") (neg "fchs")]) -;; Used in signed and unsigned widening multiplications. +;; Mapping of extend operators (define_code_iterator any_extend [sign_extend zero_extend]) ;; Prefix for insn menmonic. @@ -993,7 +983,8 @@ ;; Used in signed and unsigned truncations. (define_code_iterator any_truncate [ss_truncate truncate us_truncate]) ;; Instruction suffix for truncations. -(define_code_attr trunsuffix [(ss_truncate "s") (truncate "") (us_truncate "us")]) +(define_code_attr trunsuffix + [(ss_truncate "s") (truncate "") (us_truncate "us")]) ;; Used in signed and unsigned fix. (define_code_iterator any_fix [fix unsigned_fix]) @@ -1007,6 +998,14 @@ (define_code_attr floatunssuffix [(float "") (unsigned_float "uns")]) (define_code_attr floatprefix [(float "s") (unsigned_float "u")]) +;; Base name for expression +(define_code_attr insn + [(plus "add") (ss_plus "ssadd") (us_plus "usadd") + (minus "sub") (ss_minus "sssub") (us_minus "ussub") + (sign_extend "extend") (zero_extend "zero_extend") + (ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr") + (rotate "rotl") (rotatert "rotr")]) + ;; All integer modes. (define_mode_iterator SWI1248x [QI HI SI DI]) @@ -7456,14 +7455,14 @@ ;; The patterns that match these are at the end of this file. -(define_expand "<plusminus_insn>xf3" +(define_expand "<insn>xf3" [(set (match_operand:XF 0 "register_operand") (plusminus:XF (match_operand:XF 1 "register_operand") (match_operand:XF 2 "register_operand")))] "TARGET_80387") -(define_expand "<plusminus_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:MODEF 0 "register_operand") (plusminus:MODEF (match_operand:MODEF 1 "register_operand") @@ -10561,7 +10560,7 @@ not{<imodesuffix>}\t%0 #" [(set (attr "isa") - (cond [(eq_attr "alternative" "2") + (cond [(eq_attr "alternative" "1") (if_then_else (eq_attr "mode" "SI,DI") (const_string "avx512bw") (const_string "avx512f")) @@ -11395,7 +11394,7 @@ ;; See comment above `ashl<mode>3' about how this works. -(define_expand "<shift_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:SDWIM 0 "<shift_operand>") (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>") (match_operand:QI 2 "nonmemory_operand")))] @@ -11403,7 +11402,7 @@ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*<shift_insn><mode>3_mask" +(define_insn_and_split "*<insn><mode>3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11426,7 +11425,7 @@ "operands[2] = gen_lowpart (QImode, operands[2]);" [(set_attr "isa" "*,bmi2")]) -(define_insn_and_split "*<shift_insn><mode>3_mask_1" +(define_insn_and_split "*<insn><mode>3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11448,7 +11447,7 @@ "" [(set_attr "isa" "*,bmi2")]) -(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask" +(define_insn_and_split "*<insn><dwi>3_doubleword_mask" [(set (match_operand:<DWI> 0 "register_operand") (any_shiftrt:<DWI> (match_operand:<DWI> 1 "register_operand") @@ -11490,7 +11489,7 @@ emit_move_insn (operands[4], operands[5]); }) -(define_insn_and_split "*<shift_insn><dwi>3_doubleword_mask_1" +(define_insn_and_split "*<insn><dwi>3_doubleword_mask_1" [(set (match_operand:<DWI> 0 "register_operand") (any_shiftrt:<DWI> (match_operand:<DWI> 1 "register_operand") @@ -11529,7 +11528,7 @@ emit_move_insn (operands[4], operands[5]); }) -(define_insn_and_split "*<shift_insn><mode>3_doubleword" +(define_insn_and_split "*<insn><mode>3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=&r") (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "<S>c"))) @@ -11538,7 +11537,7 @@ "#" "epilogue_completed" [(const_int 0)] - "ix86_split_<shift_insn> (operands, NULL_RTX, <MODE>mode); DONE;" + "ix86_split_<insn> (operands, NULL_RTX, <MODE>mode); DONE;" [(set_attr "type" "multi")]) ;; By default we don't ask for a scratch register, because when DWImode @@ -11555,7 +11554,7 @@ (match_dup 3)] "TARGET_CMOVE" [(const_int 0)] - "ix86_split_<shift_insn> (operands, operands[3], <DWI>mode); DONE;") + "ix86_split_<insn> (operands, operands[3], <DWI>mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") @@ -11659,7 +11658,7 @@ DONE; }) -(define_insn "*bmi2_<shift_insn><mode>3_1" +(define_insn "*bmi2_<insn><mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") (match_operand:SWI48 2 "register_operand" "r")))] @@ -11668,7 +11667,7 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "<MODE>")]) -(define_insn "*<shift_insn><mode>3_1" +(define_insn "*<insn><mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm") @@ -11711,7 +11710,7 @@ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))] "operands[2] = gen_lowpart (<MODE>mode, operands[2]);") -(define_insn "*bmi2_<shift_insn>si3_1_zext" +(define_insn "*bmi2_<insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "rm") @@ -11721,7 +11720,7 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "SI")]) -(define_insn "*<shift_insn>si3_1_zext" +(define_insn "*<insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm") @@ -11765,7 +11764,7 @@ (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))] "operands[2] = gen_lowpart (SImode, operands[2]);") -(define_insn "*<shift_insn><mode>3_1" +(define_insn "*<insn><mode>3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m") (any_shiftrt:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0") @@ -11789,7 +11788,7 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) -(define_insn "*<shift_insn><mode>3_1_slp" +(define_insn "*<insn><mode>3_1_slp" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) (any_shiftrt:SWI12 (match_operand:SWI12 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) @@ -11817,7 +11816,7 @@ ;; This pattern can't accept a variable shift count, since shifts by ;; zero don't affect the flags. We assume that shifts by constant ;; zero are optimized away. -(define_insn "*<shift_insn><mode>3_cmp" +(define_insn "*<insn><mode>3_cmp" [(set (reg FLAGS_REG) (compare (any_shiftrt:SWI @@ -11849,7 +11848,7 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) -(define_insn "*<shift_insn>si3_cmp_zext" +(define_insn "*<insn>si3_cmp_zext" [(set (reg FLAGS_REG) (compare (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0") @@ -11881,7 +11880,7 @@ (const_string "*"))) (set_attr "mode" "SI")]) -(define_insn "*<shift_insn><mode>3_cconly" +(define_insn "*<insn><mode>3_cconly" [(set (reg FLAGS_REG) (compare (any_shiftrt:SWI @@ -11913,14 +11912,14 @@ ;; Rotate instructions -(define_expand "<rotate_insn>ti3" +(define_expand "<insn>ti3" [(set (match_operand:TI 0 "register_operand") (any_rotate:TI (match_operand:TI 1 "register_operand") (match_operand:QI 2 "nonmemory_operand")))] "TARGET_64BIT" { if (const_1_to_63_operand (operands[2], VOIDmode)) - emit_insn (gen_ix86_<rotate_insn>ti3_doubleword + emit_insn (gen_ix86_<insn>ti3_doubleword (operands[0], operands[1], operands[2])); else FAIL; @@ -11928,7 +11927,7 @@ DONE; }) -(define_expand "<rotate_insn>di3" +(define_expand "<insn>di3" [(set (match_operand:DI 0 "shiftdi_operand") (any_rotate:DI (match_operand:DI 1 "shiftdi_operand") (match_operand:QI 2 "nonmemory_operand")))] @@ -11937,7 +11936,7 @@ if (TARGET_64BIT) ix86_expand_binary_operator (<CODE>, DImode, operands); else if (const_1_to_31_operand (operands[2], VOIDmode)) - emit_insn (gen_ix86_<rotate_insn>di3_doubleword + emit_insn (gen_ix86_<insn>di3_doubleword (operands[0], operands[1], operands[2])); else FAIL; @@ -11945,7 +11944,7 @@ DONE; }) -(define_expand "<rotate_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:SWIM124 0 "nonimmediate_operand") (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") (match_operand:QI 2 "nonmemory_operand")))] @@ -11953,7 +11952,7 @@ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") ;; Avoid useless masking of count operand. -(define_insn_and_split "*<rotate_insn><mode>3_mask" +(define_insn_and_split "*<insn><mode>3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -11991,7 +11990,7 @@ (subreg:QI (match_dup 2) 0)))] "operands[4] = gen_reg_rtx (<MODE>mode);") -(define_insn_and_split "*<rotate_insn><mode>3_mask_1" +(define_insn_and_split "*<insn><mode>3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -12098,7 +12097,7 @@ [(set_attr "type" "rotatex") (set_attr "mode" "<MODE>")]) -(define_insn "*<rotate_insn><mode>3_1" +(define_insn "*<insn><mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,rm") @@ -12165,7 +12164,7 @@ [(set_attr "type" "rotatex") (set_attr "mode" "SI")]) -(define_insn "*<rotate_insn>si3_1_zext" +(define_insn "*<insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (any_rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm") @@ -12224,7 +12223,7 @@ [(set (match_dup 0) (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))]) -(define_insn "*<rotate_insn><mode>3_1" +(define_insn "*<insn><mode>3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m") (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0") (match_operand:QI 2 "nonmemory_operand" "c<S>"))) @@ -12247,7 +12246,7 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) -(define_insn "*<rotate_insn><mode>3_1_slp" +(define_insn "*<insn><mode>3_1_slp" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) (any_rotate:SWI12 (match_operand:SWI12 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) @@ -12420,6 +12419,71 @@ (match_dup 3))) (clobber (reg:CC FLAGS_REG))])]) +(define_insn_and_split "*btr<mode>_1" + [(set (match_operand:SWI12 0 "register_operand") + (and:SWI12 + (subreg:SWI12 + (rotate:SI (const_int -2) + (match_operand:QI 2 "register_operand")) 0) + (match_operand:SWI12 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 0) + (and:SI (rotate:SI (const_int -2) (match_dup 2)) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode); + if (MEM_P (operands[1])) + operands[1] = force_reg (<MODE>mode, operands[1]); + operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode); +}) + +(define_insn_and_split "*btr<mode>_2" + [(set (zero_extract:HI + (match_operand:SWI12 0 "nonimmediate_operand") + (const_int 1) + (zero_extend:SI (match_operand:QI 1 "register_operand"))) + (const_int 0)) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT && ix86_pre_reload_split ()" + "#" + "&& MEM_P (operands[0])" + [(set (match_dup 2) (match_dup 0)) + (parallel + [(set (match_dup 3) + (and:SI (rotate:SI (const_int -2) (match_dup 1)) + (match_dup 4))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 0) (match_dup 5))] +{ + operands[2] = gen_reg_rtx (<MODE>mode); + operands[5] = gen_reg_rtx (<MODE>mode); + operands[3] = lowpart_subreg (SImode, operands[5], <MODE>mode); + operands[4] = lowpart_subreg (SImode, operands[2], <MODE>mode); +}) + +(define_split + [(set (zero_extract:HI + (match_operand:SWI12 0 "register_operand") + (const_int 1) + (zero_extend:SI (match_operand:QI 1 "register_operand"))) + (const_int 0)) + (clobber (reg:CC FLAGS_REG))] + "TARGET_USE_BT && ix86_pre_reload_split ()" + [(parallel + [(set (match_dup 0) + (and:SI (rotate:SI (const_int -2) (match_dup 1)) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[2] = lowpart_subreg (SImode, operands[0], <MODE>mode); + operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode); +}) + ;; These instructions are never faster than the corresponding ;; and/ior/xor operations when using immediate operand, so with ;; 32-bit there's no point. But in 64-bit, we can't hold the @@ -12689,12 +12753,10 @@ [(not:SWI (match_operand:SWI 2 "register_operand")) (match_operand:SWI 3 "nonimmediate_operand")]))] "" - [(parallel - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (plus:SWI (match_dup 2) (match_dup 3)) - (match_dup 2))) - (clobber (scratch:SWI))]) + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (plus:SWI (match_dup 2) (match_dup 3)) + (match_dup 2))) (set (match_dup 0) (match_op_dup 1 [(reg:CCC FLAGS_REG) (const_int 0)]))]) @@ -12705,12 +12767,10 @@ (match_operand 3 "const_int_operand")]))] "TARGET_64BIT && IN_RANGE (exact_log2 (UINTVAL (operands[3]) + 1), 32, 63)" - [(parallel - [(set (reg:CCZ FLAGS_REG) - (compare:CCZ - (lshiftrt:DI (match_dup 2) (match_dup 4)) - (const_int 0))) - (clobber (scratch:DI))]) + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (lshiftrt:DI (match_dup 2) (match_dup 4)) + (const_int 0))) (set (match_dup 0) (match_op_dup 1 [(reg:CCZ FLAGS_REG) (const_int 0)]))] { @@ -12901,12 +12961,10 @@ (label_ref (match_operand 0)) (pc)))] "" - [(parallel - [(set (reg:CCC FLAGS_REG) - (compare:CCC - (plus:SWI (match_dup 2) (match_dup 3)) - (match_dup 2))) - (clobber (scratch:SWI))]) + [(set (reg:CCC FLAGS_REG) + (compare:CCC + (plus:SWI (match_dup 2) (match_dup 3)) + (match_dup 2))) (set (pc) (if_then_else (match_op_dup 1 [(reg:CCC FLAGS_REG) (const_int 0)]) (label_ref (match_operand 0)) @@ -12922,12 +12980,10 @@ (pc)))] "TARGET_64BIT && IN_RANGE (exact_log2 (UINTVAL (operands[3]) + 1), 32, 63)" - [(parallel - [(set (reg:CCZ FLAGS_REG) - (compare:CCZ - (lshiftrt:DI (match_dup 2) (match_dup 4)) - (const_int 0))) - (clobber (scratch:DI))]) + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (lshiftrt:DI (match_dup 2) (match_dup 4)) + (const_int 0))) (set (pc) (if_then_else (match_op_dup 1 [(reg:CCZ FLAGS_REG) (const_int 0)]) (label_ref (match_operand 0)) @@ -14572,6 +14628,35 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) +(define_insn "*bmi_blsi_<mode>_cmp" + [(set (reg FLAGS_REG) + (compare + (and:SWI48 + (neg:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")) + (match_dup 1)) + (const_int 0))) + (set (match_operand:SWI48 0 "register_operand" "=r") + (and:SWI48 (neg:SWI48 (match_dup 1)) (match_dup 1)))] + "TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)" + "blsi\t{%1, %0|%0, %1}" + [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "double") + (set_attr "mode" "<MODE>")]) + +(define_insn "*bmi_blsi_<mode>_ccno" + [(set (reg FLAGS_REG) + (compare + (and:SWI48 + (neg:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")) + (match_dup 1)) + (const_int 0))) + (clobber (match_scratch:SWI48 0 "=r"))] + "TARGET_BMI && ix86_match_ccmode (insn, CCNOmode)" + "blsi\t{%1, %0|%0, %1}" + [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "double") + (set_attr "mode" "<MODE>")]) + (define_insn "*bmi_blsmsk_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (xor:SWI48 @@ -18577,9 +18662,8 @@ && INTVAL (operands[2]) != -1 && INTVAL (operands[2]) != 2147483647" [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2))) - (parallel [(set (match_dup 0) - (neg:SWI48 (ltu:SWI48 (reg:CC FLAGS_REG) (const_int 0)))) - (clobber (reg:CC FLAGS_REG))])] + (set (match_dup 0) + (neg:SWI48 (ltu:SWI48 (reg:CC FLAGS_REG) (const_int 0))))] "operands[2] = GEN_INT (INTVAL (operands[2]) + 1);") (define_split @@ -18590,9 +18674,8 @@ (const_int 0))))] "" [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (const_int 1))) - (parallel [(set (match_dup 0) - (neg:SWI (ltu:SWI (reg:CC FLAGS_REG) (const_int 0)))) - (clobber (reg:CC FLAGS_REG))])]) + (set (match_dup 0) + (neg:SWI (ltu:SWI (reg:CC FLAGS_REG) (const_int 0))))]) (define_split [(set (match_operand:SWI 0 "register_operand") @@ -18601,13 +18684,10 @@ (match_operand 1 "int_nonimmediate_operand") (const_int 0))))] "" - [(parallel [(set (reg:CCC FLAGS_REG) - (ne:CCC (match_dup 1) (const_int 0))) - (clobber (match_dup 2))]) - (parallel [(set (match_dup 0) - (neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0)))) - (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_rtx_SCRATCH (GET_MODE (operands[1]));") + [(set (reg:CCC FLAGS_REG) + (ne:CCC (match_dup 1) (const_int 0))) + (set (match_dup 0) + (neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))]) (define_insn "*mov<mode>cc_noc" [(set (match_operand:SWI248 0 "register_operand" "=r,r") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 87e6021..c781fdc 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1,6 +1,6 @@ ; Options for the IA-32 and AMD64 ports of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -49,6 +49,16 @@ int recip_mask_explicit TargetSave int x_recip_mask_explicit +;; A copy of flag_excess_precision as a target variable that should +;; force a different DECL_FUNCTION_SPECIFIC_TARGET upon +;; flag_excess_precision changes. +TargetVariable +enum excess_precision ix86_excess_precision = EXCESS_PRECISION_DEFAULT + +;; Similarly for flag_unsafe_math_optimizations. +TargetVariable +bool ix86_unsafe_math_optimizations = false + ;; Definitions to add to the cl_target_option structure ;; -march= processor TargetSave @@ -95,8 +105,8 @@ TargetSave unsigned char arch_specified ;; -mcmodel= model -TargetSave -enum cmodel x_ix86_cmodel +TargetVariable +enum cmodel ix86_cmodel = CM_32 ;; -mabi= TargetSave @@ -123,24 +133,24 @@ TargetSave int x_ix86_force_drap ;; -mincoming-stack-boundary= -TargetSave -int x_ix86_incoming_stack_boundary_arg +TargetVariable +int ix86_incoming_stack_boundary_arg ;; -maddress-mode= -TargetSave -enum pmode x_ix86_pmode +TargetVariable +enum pmode ix86_pmode = PMODE_SI ;; -mpreferred-stack-boundary= -TargetSave -int x_ix86_preferred_stack_boundary_arg +TargetVariable +int ix86_preferred_stack_boundary_arg ;; -mrecip= TargetSave const char *x_ix86_recip_name ;; -mregparm= -TargetSave -int x_ix86_regparm +TargetVariable +int ix86_regparm ;; -mlarge-data-threshold= TargetSave @@ -179,40 +189,40 @@ TargetSave int x_ix86_tune_no_default ;; -mveclibabi= -TargetSave -enum ix86_veclibabi x_ix86_veclibabi_type +TargetVariable +enum ix86_veclibabi ix86_veclibabi_type = ix86_veclibabi_type_none ;; x86 options m128bit-long-double -Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save +Target RejectNegative Mask(128BIT_LONG_DOUBLE) Save sizeof(long double) is 16. m80387 -Target Report Mask(80387) Save +Target Mask(80387) Save Use hardware fp. m96bit-long-double -Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save +Target RejectNegative InverseMask(128BIT_LONG_DOUBLE) Save sizeof(long double) is 12. mlong-double-80 -Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save +Target RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save Use 80-bit long double. mlong-double-64 -Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save +Target RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save Use 64-bit long double. mlong-double-128 -Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save +Target RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save Use 128-bit long double. maccumulate-outgoing-args -Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save +Target Mask(ACCUMULATE_OUTGOING_ARGS) Save Reserve space for outgoing arguments in the function prologue. malign-double -Target Report Mask(ALIGN_DOUBLE) Save +Target Mask(ALIGN_DOUBLE) Save Align some doubles on dword boundary. malign-functions= @@ -228,7 +238,7 @@ Target RejectNegative Joined UInteger Loop code aligned to this power of 2. malign-stringops -Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save +Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save Align destination of the string operations. malign-data= @@ -315,15 +325,15 @@ mcpu= Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) mfancy-math-387 -Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save +Target RejectNegative InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save Generate sin, cos, sqrt for FPU. mforce-drap -Target Report Var(ix86_force_drap) +Target Var(ix86_force_drap) Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. mfp-ret-in-387 -Target Report Mask(FLOAT_RETURNS) Save +Target Mask(FLOAT_RETURNS) Save Return values of functions in FPU registers. mfpmath= @@ -360,50 +370,50 @@ Target RejectNegative Mask(80387) Save Use hardware fp. mieee-fp -Target Report Mask(IEEE_FP) Save +Target Mask(IEEE_FP) Save Use IEEE math for fp comparisons. minline-all-stringops -Target Report Mask(INLINE_ALL_STRINGOPS) Save +Target Mask(INLINE_ALL_STRINGOPS) Save Inline all known string operations. minline-stringops-dynamically -Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save +Target Mask(INLINE_STRINGOPS_DYNAMICALLY) Save Inline memset/memcpy string operations, but perform inline version only for small blocks. mintel-syntax Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) mms-bitfields -Target Report Mask(MS_BITFIELD_LAYOUT) Save +Target Mask(MS_BITFIELD_LAYOUT) Save Use native (MS) bitfield layout. mno-align-stringops -Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save +Target RejectNegative Mask(NO_ALIGN_STRINGOPS) Undocumented Save mno-fancy-math-387 -Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save +Target RejectNegative Mask(NO_FANCY_MATH_387) Undocumented Save mno-push-args -Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save +Target RejectNegative Mask(NO_PUSH_ARGS) Undocumented Save mno-red-zone -Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save +Target RejectNegative Mask(NO_RED_ZONE) Undocumented Save momit-leaf-frame-pointer -Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save +Target Mask(OMIT_LEAF_FRAME_POINTER) Save Omit the frame pointer in leaf functions. mpc32 -Target RejectNegative Report +Target RejectNegative Set 80387 floating-point precision to 32-bit. mpc64 -Target RejectNegative Report +Target RejectNegative Set 80387 floating-point precision to 64-bit. mpc80 -Target RejectNegative Report +Target RejectNegative Set 80387 floating-point precision to 80-bit. mpreferred-stack-boundary= @@ -415,11 +425,11 @@ Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) Assume incoming stack aligned to this power of 2. mpush-args -Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save +Target InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save Use push instructions to save outgoing arguments. mred-zone -Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save +Target RejectNegative InverseMask(NO_RED_ZONE, RED_ZONE) Save Use red-zone in the x86-64 code. mregparm= @@ -427,7 +437,7 @@ Target RejectNegative Joined UInteger Var(ix86_regparm) Number of registers used to pass integer arguments. mrtd -Target Report Mask(RTD) Save +Target Mask(RTD) Save Alternate calling convention. msoft-float @@ -439,11 +449,11 @@ Target RejectNegative Mask(SSEREGPARM) Save Use SSE register passing conventions for SF and DF mode. mstackrealign -Target Report Var(ix86_force_align_arg_pointer) +Target Var(ix86_force_align_arg_pointer) Realign stack in prologue. mstack-arg-probe -Target Report Mask(STACK_PROBE) Save +Target Mask(STACK_PROBE) Save Enable stack probing. mmemcpy-strategy= @@ -501,7 +511,7 @@ EnumValue Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) mtls-direct-seg-refs -Target Report Mask(TLS_DIRECT_SEG_REFS) +Target Mask(TLS_DIRECT_SEG_REFS) Use direct references against %gs when accessing tls data. mtune= @@ -520,7 +530,7 @@ mdump-tune-features Target RejectNegative Var(ix86_dump_tunes) miamcu -Target Report Mask(IAMCU) +Target Mask(IAMCU) Generate code that conforms to Intel MCU psABI. mabi= @@ -538,7 +548,7 @@ EnumValue Enum(calling_abi) String(ms) Value(MS_ABI) mcall-ms2sysv-xlogues -Target Report Mask(CALL_MS2SYSV_XLOGUES) Save +Target Mask(CALL_MS2SYSV_XLOGUES) Save Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. mveclibabi= @@ -556,28 +566,28 @@ EnumValue Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) mvect8-ret-in-mem -Target Report Mask(VECT8_RETURNS) Save +Target Mask(VECT8_RETURNS) Save Return 8-byte vectors in memory. mrecip -Target Report Mask(RECIP) Save +Target Mask(RECIP) Save Generate reciprocals instead of divss and sqrtss. mrecip= -Target Report RejectNegative Joined Var(ix86_recip_name) +Target RejectNegative Joined Var(ix86_recip_name) Control generation of reciprocal estimates. mcld -Target Report Mask(CLD) Save +Target Mask(CLD) Save Generate cld instruction in the function prologue. mvzeroupper -Target Report Mask(VZEROUPPER) Save +Target Mask(VZEROUPPER) Save Generate vzeroupper instruction before a transfer of control flow out of the function. mstv -Target Report Mask(STV) Save +Target Mask(STV) Save Disable Scalar to Vector optimization pass transforming 64-bit integer computations into a vector ones. @@ -591,7 +601,7 @@ Target Alias(mprefer-vector-width=, 128, 256) Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. mprefer-vector-width= -Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save +Target RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save Use given register vector width instructions instead of maximum register width in the auto-vectorizer. Enum @@ -613,63 +623,63 @@ Enum(prefer_vector_width) String(512) Value(PVW_AVX512) ;; ISA support m32 -Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save +Target RejectNegative Negative(m64) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save Generate 32bit i386 code. m64 -Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save +Target RejectNegative Negative(mx32) Mask(ABI_64) Var(ix86_isa_flags) Save Generate 64bit x86-64 code. mx32 -Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save +Target RejectNegative Negative(m16) Mask(ABI_X32) Var(ix86_isa_flags) Save Generate 32bit x86-64 code. m16 -Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save +Target RejectNegative Negative(m32) Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save Generate 16bit i386 code. mmmx -Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save +Target Mask(ISA_MMX) Var(ix86_isa_flags) Save Support MMX built-in functions. m3dnow -Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save +Target Mask(ISA_3DNOW) Var(ix86_isa_flags) Save Support 3DNow! built-in functions. m3dnowa -Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save +Target Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save Support Athlon 3Dnow! built-in functions. msse -Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE) Var(ix86_isa_flags) Save Support MMX and SSE built-in functions and code generation. msse2 -Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE2) Var(ix86_isa_flags) Save Support MMX, SSE and SSE2 built-in functions and code generation. msse3 -Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE3) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. mssse3 -Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save +Target Mask(ISA_SSSE3) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. msse4.1 -Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. msse4.2 -Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. msse4 -Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save +Target RejectNegative Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. mno-sse4 -Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save +Target RejectNegative InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save Do not support SSE4.1 and SSE4.2 built-in functions and code generation. msse5 @@ -677,262 +687,262 @@ Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) ;; Deprecated mavx -Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. mavx2 -Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. mavx512f -Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512F) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. mavx512pf -Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. mavx512er -Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. mavx512cd -Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. mavx512dq -Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. mavx512bw -Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. mavx512vl -Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. mavx512ifma -Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. mavx512vbmi -Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. mavx5124fmaps -Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. mavx5124vnniw -Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. mavx512vpopcntdq -Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. mavx512vbmi2 -Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. mavx512vnni -Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save Support AVX512VNNI built-in functions and code generation. mavx512bitalg -Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save +Target Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. mavx512vp2intersect -Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save Support AVX512VP2INTERSECT built-in functions and code generation. mfma -Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save +Target Mask(ISA_FMA) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. msse4a -Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save +Target Mask(ISA_SSE4A) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. mfma4 -Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save +Target Mask(ISA_FMA4) Var(ix86_isa_flags) Save Support FMA4 built-in functions and code generation. mxop -Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save +Target Mask(ISA_XOP) Var(ix86_isa_flags) Save Support XOP built-in functions and code generation. mlwp -Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save +Target Mask(ISA_LWP) Var(ix86_isa_flags) Save Support LWP built-in functions and code generation. mabm -Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save +Target Mask(ISA_ABM) Var(ix86_isa_flags) Save Support code generation of Advanced Bit Manipulation (ABM) instructions. mpopcnt -Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save +Target Mask(ISA_POPCNT) Var(ix86_isa_flags) Save Support code generation of popcnt instruction. mpconfig -Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save +Target Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save Support PCONFIG built-in functions and code generation. mwbnoinvd -Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save +Target Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save Support WBNOINVD built-in functions and code generation. mptwrite -Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save Support PTWRITE built-in functions and code generation. muintr -Target Report Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save +Target Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save Support UINTR built-in functions and code generation. msgx -Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save +Target Mask(ISA2_SGX) Var(ix86_isa_flags2) Save Support SGX built-in functions and code generation. mrdpid -Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save +Target Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save Support RDPID built-in functions and code generation. mgfni -Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save +Target Mask(ISA_GFNI) Var(ix86_isa_flags) Save Support GFNI built-in functions and code generation. mvaes -Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save +Target Mask(ISA2_VAES) Var(ix86_isa_flags2) Save Support VAES built-in functions and code generation. mvpclmulqdq -Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save +Target Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save Support VPCLMULQDQ built-in functions and code generation. mbmi -Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save +Target Mask(ISA_BMI) Var(ix86_isa_flags) Save Support BMI built-in functions and code generation. mbmi2 -Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save +Target Mask(ISA_BMI2) Var(ix86_isa_flags) Save Support BMI2 built-in functions and code generation. mlzcnt -Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save +Target Mask(ISA_LZCNT) Var(ix86_isa_flags) Save Support LZCNT built-in function and code generation. mhle -Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_HLE) Var(ix86_isa_flags2) Save Support Hardware Lock Elision prefixes. mrdseed -Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save +Target Mask(ISA_RDSEED) Var(ix86_isa_flags) Save Support RDSEED instruction. mprfchw -Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save +Target Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save Support PREFETCHW instruction. madx -Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save +Target Mask(ISA_ADX) Var(ix86_isa_flags) Save Support flag-preserving add-carry instructions. mclflushopt -Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save +Target Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save Support CLFLUSHOPT instructions. mclwb -Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save +Target Mask(ISA_CLWB) Var(ix86_isa_flags) Save Support CLWB instruction. mpcommit Target WarnRemoved mfxsr -Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save +Target Mask(ISA_FXSR) Var(ix86_isa_flags) Save Support FXSAVE and FXRSTOR instructions. mxsave -Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save +Target Mask(ISA_XSAVE) Var(ix86_isa_flags) Save Support XSAVE and XRSTOR instructions. mxsaveopt -Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save +Target Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save Support XSAVEOPT instruction. mxsavec -Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save +Target Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save Support XSAVEC instructions. mxsaves -Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save +Target Mask(ISA_XSAVES) Var(ix86_isa_flags) Save Support XSAVES and XRSTORS instructions. mtbm -Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save +Target Mask(ISA_TBM) Var(ix86_isa_flags) Save Support TBM built-in functions and code generation. mcx16 -Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save +Target Mask(ISA2_CX16) Var(ix86_isa_flags2) Save Support code generation of cmpxchg16b instruction. msahf -Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save +Target Mask(ISA_SAHF) Var(ix86_isa_flags) Save Support code generation of sahf instruction in 64bit x86-64 code. mmovbe -Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save Support code generation of movbe instruction. mcrc32 -Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save +Target Mask(ISA_CRC32) Var(ix86_isa_flags) Save Support code generation of crc32 instruction. maes -Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save +Target Mask(ISA_AES) Var(ix86_isa_flags) Save Support AES built-in functions and code generation. msha -Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save +Target Mask(ISA_SHA) Var(ix86_isa_flags) Save Support SHA1 and SHA256 built-in functions and code generation. mpclmul -Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save +Target Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save Support PCLMUL built-in functions and code generation. msse2avx -Target Report Var(ix86_sse2avx) +Target Var(ix86_sse2avx) Encode SSE instructions with VEX prefix. mfsgsbase -Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save +Target Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save Support FSGSBASE built-in functions and code generation. mrdrnd -Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save +Target Mask(ISA_RDRND) Var(ix86_isa_flags) Save Support RDRND built-in functions and code generation. mf16c -Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save +Target Mask(ISA_F16C) Var(ix86_isa_flags) Save Support F16C built-in functions and code generation. mprefetchwt1 -Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save +Target Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save Support PREFETCHWT1 built-in functions and code generation. mfentry -Target Report Var(flag_fentry) +Target Save Var(flag_fentry) Emit profiling counter call at function entry before prologue. mrecord-mcount -Target Report Var(flag_record_mcount) +Target Var(flag_record_mcount) Generate __mcount_loc section with all mcount or __fentry__ calls. mnop-mcount -Target Report Var(flag_nop_mcount) +Target Var(flag_nop_mcount) Generate mcount/__fentry__ calls as nops. To activate they need to be patched in. @@ -945,23 +955,23 @@ Target RejectNegative Joined Var(fentry_section) Set name of section to record mrecord-mcount calls. mskip-rax-setup -Target Report Var(flag_skip_rax_setup) +Target Var(flag_skip_rax_setup) Skip setting up RAX register when passing variable arguments. m8bit-idiv -Target Report Mask(USE_8BIT_IDIV) Save +Target Mask(USE_8BIT_IDIV) Save Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. mavx256-split-unaligned-load -Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save +Target Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save Split 32-byte AVX unaligned load. mavx256-split-unaligned-store -Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save +Target Mask(AVX256_SPLIT_UNALIGNED_STORE) Save Split 32-byte AVX unaligned store. mrtm -Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save +Target Mask(ISA_RTM) Var(ix86_isa_flags) Save Support RTM built-in functions and code generation. mmpx @@ -969,15 +979,15 @@ Target WarnRemoved Removed in GCC 9. This switch has no effect. mmwaitx -Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save +Target Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save Support MWAITX and MONITORX built-in functions and code generation. mclzero -Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save +Target Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save Support CLZERO built-in functions and code generation. mpku -Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save +Target Mask(ISA_PKU) Var(ix86_isa_flags) Save Support PKU built-in functions and code generation. mstack-protector-guard= @@ -995,55 +1005,55 @@ EnumValue Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) mstack-protector-guard-reg= -Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) +Target Save RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) Use the given base register for addressing the stack-protector guard. TargetVariable addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC mstack-protector-guard-offset= -Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) +Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) Use the given offset for addressing the stack-protector guard. TargetVariable HOST_WIDE_INT ix86_stack_protector_guard_offset = 0 mstack-protector-guard-symbol= -Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) +Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) Use the given symbol for addressing the stack-protector guard. mmitigate-rop Target WarnRemoved mgeneral-regs-only -Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save +Target RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save Generate code which uses only the general registers. mshstk -Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save +Target Mask(ISA_SHSTK) Var(ix86_isa_flags) Save Enable shadow stack built-in functions from Control-flow Enforcement Technology (CET). mcet-switch -Target Report Undocumented Var(flag_cet_switch) Init(0) +Target Undocumented Var(flag_cet_switch) Init(0) Turn on CET instrumentation for switch statements that use a jump table and an indirect jump. mmanual-endbr -Target Report Var(flag_manual_endbr) Init(0) +Target Var(flag_manual_endbr) Init(0) Insert ENDBR instruction at function entry only via cf_check attribute for CET instrumentation. mforce-indirect-call -Target Report Var(flag_force_indirect_call) Init(0) +Target Var(flag_force_indirect_call) Init(0) Make all function calls indirect. mindirect-branch= -Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) Convert indirect call and jump to call and return thunks. mfunction-return= -Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) Convert function return to call and return thunk. Enum @@ -1063,27 +1073,27 @@ EnumValue Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) mindirect-branch-register -Target Report Var(ix86_indirect_branch_register) Init(0) +Target Var(ix86_indirect_branch_register) Init(0) Force indirect call and jump via register. mmovdiri -Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save +Target Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save Support MOVDIRI built-in functions and code generation. mmovdir64b -Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save +Target Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save Support MOVDIR64B built-in functions and code generation. mwaitpkg -Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save +Target Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save Support WAITPKG built-in functions and code generation. mcldemote -Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save Support CLDEMOTE built-in functions and code generation. minstrument-return= -Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) +Target RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) Instrument function exit in instrumented functions with __fentry__. Enum @@ -1100,55 +1110,55 @@ EnumValue Enum(instrument_return) String(nop5) Value(instrument_return_nop5) mrecord-return -Target Report Var(ix86_flag_record_return) Init(0) +Target Var(ix86_flag_record_return) Init(0) Generate a __return_loc section pointing to all return instrumentation code. mavx512bf16 -Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BF16 built-in functions and code generation. menqcmd -Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save +Target Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save Support ENQCMD built-in functions and code generation. mserialize -Target Report Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save Support SERIALIZE built-in functions and code generation. mtsxldtrk -Target Report Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save +Target Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save Support TSXLDTRK built-in functions and code generation. mamx-tile -Target Report Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save Support AMX-TILE built-in functions and code generation. mamx-int8 -Target Report Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save Support AMX-INT8 built-in functions and code generation. mamx-bf16 -Target Report Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save Support AMX-BF16 built-in functions and code generation. mhreset -Target Report Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save +Target Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save Support HRESET built-in functions and code generation. mkl -Target Report Mask(ISA2_KL) Var(ix86_isa_flags2) Save +Target Mask(ISA2_KL) Var(ix86_isa_flags2) Save Support KL built-in functions and code generation. mwidekl -Target Report Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save +Target Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save Support WIDEKL built-in functions and code generation. mavxvnni -Target Report Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save +Target Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVXVNNI built-in functions and code generation. mneeded -Target Report Var(ix86_needed) Save +Target Var(ix86_needed) Save Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property. diff --git a/gcc/config/i386/i386elf.h b/gcc/config/i386/i386elf.h index 05cee89..0f03c36 100644 --- a/gcc/config/i386/i386elf.h +++ b/gcc/config/i386/i386elf.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 using ELF - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. Derived from sysv4.h written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index 3568d1f..d336a51 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/iamcu.h b/gcc/config/i386/iamcu.h index 065ee32..be99406 100644 --- a/gcc/config/i386/iamcu.h +++ b/gcc/config/i386/iamcu.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Intel MCU psABI. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index b787967..f129de4 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/intelmic-mkoffload.c b/gcc/config/i386/intelmic-mkoffload.c index 668208c..475f071 100644 --- a/gcc/config/i386/intelmic-mkoffload.c +++ b/gcc/config/i386/intelmic-mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for Intel MIC devices. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Ilya Verbin <ilya.verbin@intel.com>. diff --git a/gcc/config/i386/intelmic-offload.h b/gcc/config/i386/intelmic-offload.h index fd3894a..c4ca7b1 100644 --- a/gcc/config/i386/intelmic-offload.h +++ b/gcc/config/i386/intelmic-offload.h @@ -1,6 +1,6 @@ /* Support for Intel MIC offloading. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/k6.md b/gcc/config/i386/k6.md index 73c8ba3..d0b5c1c 100644 --- a/gcc/config/i386/k6.md +++ b/gcc/config/i386/k6.md @@ -1,5 +1,5 @@ ;; AMD K6/K6-2 Scheduling -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/keylockerintrin.h b/gcc/config/i386/keylockerintrin.h index a5f29fd..4bb6071 100644 --- a/gcc/config/i386/keylockerintrin.h +++ b/gcc/config/i386/keylockerintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/kfreebsd-gnu.h b/gcc/config/i386/kfreebsd-gnu.h index 5a0b183..8268c52 100644 --- a/gcc/config/i386/kfreebsd-gnu.h +++ b/gcc/config/i386/kfreebsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/kfreebsd-gnu64.h b/gcc/config/i386/kfreebsd-gnu64.h index b8b7143..d924650 100644 --- a/gcc/config/i386/kfreebsd-gnu64.h +++ b/gcc/config/i386/kfreebsd-gnu64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/kopensolaris-gnu.h b/gcc/config/i386/kopensolaris-gnu.h index 162c2fc..eb52707 100644 --- a/gcc/config/i386/kopensolaris-gnu.h +++ b/gcc/config/i386/kopensolaris-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kOpenSolaris-based GNU systems with ELF format - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/linux-common.h b/gcc/config/i386/linux-common.h index da0fabb..65d5a0e 100644 --- a/gcc/config/i386/linux-common.h +++ b/gcc/config/i386/linux-common.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index 9f823f1..04b274f 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h index 6cb68d1..b3822ce 100644 --- a/gcc/config/i386/linux64.h +++ b/gcc/config/i386/linux64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running Linux-based GNU systems with ELF format. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h index 0b5c8bb..1a7465b 100644 --- a/gcc/config/i386/lwpintrin.h +++ b/gcc/config/i386/lwpintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lynx.h b/gcc/config/i386/lynx.h index 9c6adb5..4804016 100644 --- a/gcc/config/i386/lynx.h +++ b/gcc/config/i386/lynx.h @@ -1,5 +1,5 @@ /* Definitions for LynxOS on i386. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lzcntintrin.h b/gcc/config/i386/lzcntintrin.h index 6d00e9f..cfa2719 100644 --- a/gcc/config/i386/lzcntintrin.h +++ b/gcc/config/i386/lzcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-pthread.h b/gcc/config/i386/mingw-pthread.h index c0cb66d..2d9263d 100644 --- a/gcc/config/i386/mingw-pthread.h +++ b/gcc/config/i386/mingw-pthread.h @@ -1,6 +1,6 @@ /* Defines that pthread library shall be enabled by default for target. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-stdint.h b/gcc/config/i386/mingw-stdint.h index efb2c0a..5216c81 100644 --- a/gcc/config/i386/mingw-stdint.h +++ b/gcc/config/i386/mingw-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using mingw. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.h b/gcc/config/i386/mingw-w64.h index 0d0aa93..0cec6b0 100644 --- a/gcc/config/i386/mingw-w64.h +++ b/gcc/config/i386/mingw-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via mingw-w64 runtime, using GNU tools and the Windows API Library. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.opt b/gcc/config/i386/mingw-w64.opt index 94d6f1c..1d34cfc 100644 --- a/gcc/config/i386/mingw-w64.opt +++ b/gcc/config/i386/mingw-w64.opt @@ -1,6 +1,6 @@ ; MinGW-w64-specific options. -; Copyright (C) 2009-2020 Free Software Foundation, Inc. +; Copyright (C) 2009-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw.opt b/gcc/config/i386/mingw.opt index bee46c9..2c239ab 100644 --- a/gcc/config/i386/mingw.opt +++ b/gcc/config/i386/mingw.opt @@ -1,6 +1,6 @@ ; MinGW-specific options. -; Copyright (C) 2008-2020 Free Software Foundation, Inc. +; Copyright (C) 2008-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index 321c30e..1a6a3a0 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mm3dnow.h b/gcc/config/i386/mm3dnow.h index e57ceea..c42426b 100644 --- a/gcc/config/i386/mm3dnow.h +++ b/gcc/config/i386/mm3dnow.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h index dff42fd..5464563 100644 --- a/gcc/config/i386/mmintrin.h +++ b/gcc/config/i386/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 7c9640d..a6ddc71 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMX and 3dNOW! instructions -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -1135,7 +1135,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "mmx_<plusminus_insn><mode>3" +(define_expand "mmx_<insn><mode>3" [(set (match_operand:MMXMODEI8 0 "register_operand") (plusminus:MMXMODEI8 (match_operand:MMXMODEI8 1 "register_mmxmem_operand") @@ -1143,7 +1143,7 @@ "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_expand "<plusminus_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:MMXMODEI 0 "register_operand") (plusminus:MMXMODEI (match_operand:MMXMODEI 1 "register_operand") @@ -1151,7 +1151,7 @@ "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*mmx_<plusminus_insn><mode>3" +(define_insn "*mmx_<insn><mode>3" [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv") (plusminus:MMXMODEI8 (match_operand:MMXMODEI8 1 "register_mmxmem_operand" "<comm>0,0,Yv") @@ -1167,7 +1167,7 @@ (set_attr "type" "mmxadd,sseadd,sseadd") (set_attr "mode" "DI,TI,TI")]) -(define_expand "mmx_<plusminus_insn><mode>3" +(define_expand "mmx_<insn><mode>3" [(set (match_operand:MMXMODE12 0 "register_operand") (sat_plusminus:MMXMODE12 (match_operand:MMXMODE12 1 "register_mmxmem_operand") @@ -1175,7 +1175,7 @@ "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*mmx_<plusminus_insn><mode>3" +(define_insn "*mmx_<insn><mode>3" [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv") (sat_plusminus:MMXMODE12 (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yv") @@ -1508,7 +1508,7 @@ (match_operand:DI 2 "nonmemory_operand")))] "TARGET_MMX_WITH_SSE") -(define_insn "mmx_<shift_insn><mode>3" +(define_insn "mmx_<insn><mode>3" [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv") (any_lshift:MMXMODE248 (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv") @@ -1527,7 +1527,7 @@ (const_string "0"))) (set_attr "mode" "DI,TI,TI")]) -(define_expand "<shift_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:MMXMODE248 0 "register_operand") (any_lshift:MMXMODE248 (match_operand:MMXMODE248 1 "register_operand") diff --git a/gcc/config/i386/movdirintrin.h b/gcc/config/i386/movdirintrin.h index b2f8406..c50fe40 100644 --- a/gcc/config/i386/movdirintrin.h +++ b/gcc/config/i386/movdirintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/msformat-c.c b/gcc/config/i386/msformat-c.c index 085ac88..5b9ca5f 100644 --- a/gcc/config/i386/msformat-c.c +++ b/gcc/config/i386/msformat-c.c @@ -1,5 +1,5 @@ /* Check calls to formatted I/O functions (-Wformat). - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mwaitxintrin.h b/gcc/config/i386/mwaitxintrin.h index 7144141..ad8afba 100644 --- a/gcc/config/i386/mwaitxintrin.h +++ b/gcc/config/i386/mwaitxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/netbsd-elf.h b/gcc/config/i386/netbsd-elf.h index d7dfe4c..a0bbfd0 100644 --- a/gcc/config/i386/netbsd-elf.h +++ b/gcc/config/i386/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for i386/ELF NetBSD systems. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by matthew green <mrg@eterna.com.au> This file is part of GCC. diff --git a/gcc/config/i386/netbsd64.h b/gcc/config/i386/netbsd64.h index a14a835..7987dbf 100644 --- a/gcc/config/i386/netbsd64.h +++ b/gcc/config/i386/netbsd64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for x86-64/ELF NetBSD systems. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nmmintrin.h b/gcc/config/i386/nmmintrin.h index 6c5ec40..acb0714 100644 --- a/gcc/config/i386/nmmintrin.h +++ b/gcc/config/i386/nmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.h b/gcc/config/i386/nto.h index c09c2b1..739dbe9 100644 --- a/gcc/config/i386/nto.h +++ b/gcc/config/i386/nto.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running QNX/Neutrino. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.opt b/gcc/config/i386/nto.opt index ce32d32..0fa86bb 100644 --- a/gcc/config/i386/nto.opt +++ b/gcc/config/i386/nto.opt @@ -1,6 +1,6 @@ ; QNX options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/openbsdelf.h b/gcc/config/i386/openbsdelf.h index 7771e4c..c411ff5 100644 --- a/gcc/config/i386/openbsdelf.h +++ b/gcc/config/i386/openbsdelf.h @@ -1,6 +1,6 @@ /* Configuration for an OpenBSD i386 target. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pconfigintrin.h b/gcc/config/i386/pconfigintrin.h index 31c493a..5346cbd 100644 --- a/gcc/config/i386/pconfigintrin.h +++ b/gcc/config/i386/pconfigintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pentium.md b/gcc/config/i386/pentium.md index e7c4a72..a876339 100644 --- a/gcc/config/i386/pentium.md +++ b/gcc/config/i386/pentium.md @@ -1,5 +1,5 @@ ;; Pentium Scheduling -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/pkuintrin.h b/gcc/config/i386/pkuintrin.h index 0d2dd51..cd5638f 100644 --- a/gcc/config/i386/pkuintrin.h +++ b/gcc/config/i386/pkuintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2015-2020 Free Software Foundation, Inc. +/* Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h index 87344d9..1b0bfe3 100644 --- a/gcc/config/i386/pmm_malloc.h +++ b/gcc/config/i386/pmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h index feef44f..fa9c5bb 100644 --- a/gcc/config/i386/pmmintrin.h +++ b/gcc/config/i386/pmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/popcntintrin.h b/gcc/config/i386/popcntintrin.h index 473dca4..8487656 100644 --- a/gcc/config/i386/popcntintrin.h +++ b/gcc/config/i386/popcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md index d5dde1f..cfcb0e7 100644 --- a/gcc/config/i386/ppro.md +++ b/gcc/config/i386/ppro.md @@ -1,5 +1,5 @@ ;; Scheduling for the Intel P6 family of processors -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index be5aaa4..ee42ba2 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for IA-32 and x86-64. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -1069,6 +1069,53 @@ return true; }) +/* Return true if operand is a float vector constant that is all ones. */ +(define_predicate "float_vector_all_ones_operand" + (match_code "const_vector,mem") +{ + mode = GET_MODE (op); + if (!FLOAT_MODE_P (mode) + || (MEM_P (op) + && (!SYMBOL_REF_P (XEXP (op, 0)) + || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))))) + return false; + + if (MEM_P (op)) + { + op = get_pool_constant (XEXP (op, 0)); + if (GET_CODE (op) != CONST_VECTOR) + return false; + + if (GET_MODE (op) != mode + && INTEGRAL_MODE_P (GET_MODE (op)) + && op == CONSTM1_RTX (GET_MODE (op))) + return true; + } + + rtx first = XVECEXP (op, 0, 0); + for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++) + { + rtx tmp = XVECEXP (op, 0, i); + if (!rtx_equal_p (tmp, first)) + return false; + } + if (GET_MODE (first) == E_SFmode) + { + long l; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l); + return (l & 0xffffffff) == 0xffffffff; + } + else if (GET_MODE (first) == E_DFmode) + { + long l[2]; + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l); + return ((l[0] & 0xffffffff) == 0xffffffff + && (l[1] & 0xffffffff) == 0xffffffff); + } + else + return false; +}) + /* Return true if operand is a vector constant that is all ones. */ (define_predicate "vector_all_ones_operand" (and (match_code "const_vector") @@ -1600,6 +1647,38 @@ return true; }) +;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select, +;; where one of the two operands of the vec_concat is const0_operand. +(define_predicate "pmovzx_parallel" + (and (match_code "parallel") + (match_code "const_int" "a")) +{ + int nelt = XVECLEN (op, 0); + int elt, i; + + if (nelt < 2) + return false; + + /* Check that the permutation is suitable for pmovz{bw,wd,dq}. + For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */ + elt = INTVAL (XVECEXP (op, 0, 0)); + if (elt == 0) + { + for (i = 1; i < nelt; ++i) + if ((i & 1) != 0) + { + if (INTVAL (XVECEXP (op, 0, i)) < nelt) + return false; + } + else if (INTVAL (XVECEXP (op, 0, i)) != i / 2) + return false; + } + else + return false; + + return true; +}) + ;; Return true if OP is a parallel for a vbroadcast permute. (define_predicate "avx_vbroadcast_operand" (and (match_code "parallel") diff --git a/gcc/config/i386/prfchwintrin.h b/gcc/config/i386/prfchwintrin.h index c9d263a..0ae4f13 100644 --- a/gcc/config/i386/prfchwintrin.h +++ b/gcc/config/i386/prfchwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos.h b/gcc/config/i386/rdos.h index 74af3ec..1d6e31d 100644 --- a/gcc/config/i386/rdos.h +++ b/gcc/config/i386/rdos.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on i386. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos64.h b/gcc/config/i386/rdos64.h index 993eb5b..73e77e6 100644 --- a/gcc/config/i386/rdos64.h +++ b/gcc/config/i386/rdos64.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on x86_64. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdseedintrin.h b/gcc/config/i386/rdseedintrin.h index 168053a..1badab7 100644 --- a/gcc/config/i386/rdseedintrin.h +++ b/gcc/config/i386/rdseedintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rtemself.h b/gcc/config/i386/rtemself.h index d3cc8ad..97639da 100644 --- a/gcc/config/i386/rtemself.h +++ b/gcc/config/i386/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting an ix86 using ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/i386/rtmintrin.h b/gcc/config/i386/rtmintrin.h index 436e517..5b2ac76 100644 --- a/gcc/config/i386/rtmintrin.h +++ b/gcc/config/i386/rtmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/serializeintrin.h b/gcc/config/i386/serializeintrin.h index 95f26d6..89b5b94 100644 --- a/gcc/config/i386/serializeintrin.h +++ b/gcc/config/i386/serializeintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/sgxintrin.h b/gcc/config/i386/sgxintrin.h index fc6f4c5..152be6a 100644 --- a/gcc/config/i386/sgxintrin.h +++ b/gcc/config/i386/sgxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/shaintrin.h b/gcc/config/i386/shaintrin.h index 13833b2..ed09408 100644 --- a/gcc/config/i386/shaintrin.h +++ b/gcc/config/i386/shaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2020 Free Software Foundation, Inc. +/* Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/slm.md b/gcc/config/i386/slm.md index 7814417..4531479 100644 --- a/gcc/config/i386/slm.md +++ b/gcc/config/i386/slm.md @@ -1,5 +1,5 @@ ;; Slivermont(SLM) Scheduling -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h index 6437752..f8c4c92 100644 --- a/gcc/config/i386/smmintrin.h +++ b/gcc/config/i386/smmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index c288d44..29b37a1 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running Solaris 2 - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Fred Fish (fnf@cygnus.com). This file is part of GCC. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 94bb445..369a00d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1,5 +1,5 @@ ;; GCC machine description for SSE instructions -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -648,6 +648,9 @@ ;; All 256bit vector integer modes (define_mode_iterator VI_256 [V32QI V16HI V8SI V4DI]) +;; All 128 and 256bit vector integer modes +(define_mode_iterator VI_128_256 [V16QI V8HI V4SI V2DI V32QI V16HI V8SI V4DI]) + ;; Various 128bit vector integer mode combinations (define_mode_iterator VI12_128 [V16QI V8HI]) (define_mode_iterator VI14_128 [V16QI V4SI]) @@ -1854,7 +1857,7 @@ } [(set_attr "isa" "noavx,noavx,avx,avx")]) -(define_expand "<plusminus_insn><mode>3<mask_name><round_name>" +(define_expand "<insn><mode>3<mask_name><round_name>" [(set (match_operand:VF 0 "register_operand") (plusminus:VF (match_operand:VF 1 "<round_nimm_predicate>") @@ -1862,7 +1865,7 @@ "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*<plusminus_insn><mode>3<mask_name><round_name>" +(define_insn "*<insn><mode>3<mask_name><round_name>" [(set (match_operand:VF 0 "register_operand" "=x,v") (plusminus:VF (match_operand:VF 1 "<bcst_round_nimm_predicate>" "<comm>0,v") @@ -1879,7 +1882,7 @@ ;; Standard scalar operation patterns which preserve the rest of the ;; vector for combiner. -(define_insn "*<sse>_vm<plusminus_insn><mode>3" +(define_insn "*<sse>_vm<insn><mode>3" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (vec_duplicate:VF_128 @@ -1899,7 +1902,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<ssescalarmode>")]) -(define_insn "<sse>_vm<plusminus_insn><mode>3<mask_scalar_name><round_scalar_name>" +(define_insn "<sse>_vm<insn><mode>3<mask_scalar_name><round_scalar_name>" [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (plusminus:VF_128 @@ -2569,7 +2572,7 @@ operands[5] = GEN_INT (ival); }) -(define_insn "avx_h<plusminus_insn>v4df3" +(define_insn "avx_h<insn>v4df3" [(set (match_operand:V4DF 0 "register_operand" "=x") (vec_concat:V4DF (vec_concat:V2DF @@ -2698,7 +2701,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "V2DF")]) -(define_insn "avx_h<plusminus_insn>v8sf3" +(define_insn "avx_h<insn>v8sf3" [(set (match_operand:V8SF 0 "register_operand" "=x") (vec_concat:V8SF (vec_concat:V4SF @@ -2741,7 +2744,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "V8SF")]) -(define_insn "sse3_h<plusminus_insn>v4sf3" +(define_insn "sse3_h<insn>v4sf3" [(set (match_operand:V4SF 0 "register_operand" "=x,x") (vec_concat:V4SF (vec_concat:V2SF @@ -2965,6 +2968,102 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +(define_insn_and_split "*avx_cmp<mode>3_1" + [(set (match_operand:<sseintvecmode> 0 "register_operand") + (vec_merge:<sseintvecmode> + (match_operand:<sseintvecmode> 1 "vector_all_ones_operand") + (match_operand:<sseintvecmode> 2 "const0_operand") + (unspec:<avx512fmaskmode> + [(match_operand:VF_128_256 3 "register_operand") + (match_operand:VF_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_31_operand")] + UNSPEC_PCMP)))] + "TARGET_AVX512VL && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 6) + (unspec:VF_128_256 + [(match_dup 3) + (match_dup 4) + (match_dup 5)] + UNSPEC_PCMP)) + (set (match_dup 0) (match_dup 7))] +{ + operands[6] = gen_reg_rtx (<MODE>mode); + operands[7] + = lowpart_subreg (GET_MODE (operands[0]), operands[6], <MODE>mode); +}) + +(define_insn_and_split "*avx_cmp<mode>3_2" + [(set (match_operand:<sseintvecmode> 0 "register_operand") + (vec_merge:<sseintvecmode> + (match_operand:<sseintvecmode> 1 "vector_all_ones_operand") + (match_operand:<sseintvecmode> 2 "const0_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:VF_128_256 3 "register_operand") + (match_operand:VF_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_31_operand")] + UNSPEC_PCMP))))] + "TARGET_AVX512VL && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 6) + (unspec:VF_128_256 + [(match_dup 3) + (match_dup 4) + (match_dup 5)] + UNSPEC_PCMP)) + (set (match_dup 0) (match_dup 7))] +{ + operands[5] = GEN_INT (INTVAL (operands[5]) ^ 4); + operands[6] = gen_reg_rtx (<MODE>mode); + operands[7] + = lowpart_subreg (GET_MODE (operands[0]), operands[6], <MODE>mode); +}) + +(define_insn_and_split "*avx_cmp<mode>3_3" + [(set (match_operand:VF_128_256 0 "register_operand") + (vec_merge:VF_128_256 + (match_operand:VF_128_256 1 "float_vector_all_ones_operand") + (match_operand:VF_128_256 2 "const0_operand") + (unspec:<avx512fmaskmode> + [(match_operand:VF_128_256 3 "register_operand") + (match_operand:VF_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_31_operand")] + UNSPEC_PCMP)))] + "TARGET_AVX512VL && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:VF_128_256 + [(match_dup 3) + (match_dup 4) + (match_dup 5)] + UNSPEC_PCMP))]) + +(define_insn_and_split "*avx_cmp<mode>3_4" + [(set (match_operand:VF_128_256 0 "register_operand") + (vec_merge:VF_128_256 + (match_operand:VF_128_256 1 "float_vector_all_ones_operand") + (match_operand:VF_128_256 2 "const0_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:VF_128_256 3 "register_operand") + (match_operand:VF_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_31_operand")] + UNSPEC_PCMP))))] + "TARGET_AVX512VL && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:VF_128_256 + [(match_dup 3) + (match_dup 4) + (match_dup 5)] + UNSPEC_PCMP))] + "operands[5] = GEN_INT (INTVAL (operands[5]) ^ 4);") + (define_insn "avx_vmcmp<mode>3" [(set (match_operand:VF_128 0 "register_operand" "=x") (vec_merge:VF_128 @@ -3056,6 +3155,25 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn_and_split "*<avx512>_cmp<mode>3" + [(set (match_operand:<avx512fmaskmode> 0 "register_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:V48_AVX512VL 1 "register_operand") + (match_operand:V48_AVX512VL 2 "nonimmediate_operand") + (match_operand:SI 3 "<cmp_imm_predicate>" "n")] + UNSPEC_PCMP)))] + "TARGET_AVX512F && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:<avx512fmaskmode> + [(match_dup 1) + (match_dup 2) + (match_dup 4)] + UNSPEC_PCMP))] + "operands[4] = GEN_INT (INTVAL (operands[3]) ^ 4);") + (define_insn "<avx512>_cmp<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> @@ -3070,6 +3188,28 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_int_iterator UNSPEC_PCMP_ITER + [UNSPEC_PCMP UNSPEC_UNSIGNED_PCMP]) + +(define_insn_and_split "*<avx512>_cmp<mode>3" + [(set (match_operand:<avx512fmaskmode> 0 "register_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:VI12_AVX512VL 1 "register_operand") + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand") + (match_operand:SI 3 "<cmp_imm_predicate>")] + UNSPEC_PCMP_ITER)))] + "TARGET_AVX512BW && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:<avx512fmaskmode> + [(match_dup 1) + (match_dup 2) + (match_dup 4)] + UNSPEC_PCMP_ITER))] + "operands[4] = GEN_INT (INTVAL (operands[3]) ^ 4);") + (define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> @@ -3098,8 +3238,24 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) -(define_int_iterator UNSPEC_PCMP_ITER - [UNSPEC_PCMP UNSPEC_UNSIGNED_PCMP]) +(define_insn_and_split "*<avx512>_ucmp<mode>3" + [(set (match_operand:<avx512fmaskmode> 0 "register_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:VI48_AVX512VL 1 "register_operand") + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand") + (match_operand:SI 3 "const_0_to_7_operand")] + UNSPEC_UNSIGNED_PCMP)))] + "TARGET_AVX512F && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:<avx512fmaskmode> + [(match_dup 1) + (match_dup 2) + (match_dup 4)] + UNSPEC_UNSIGNED_PCMP))] + "operands[4] = GEN_INT (INTVAL (operands[3]) ^ 4);") (define_int_attr pcmp_signed_mask [(UNSPEC_PCMP "3") (UNSPEC_UNSIGNED_PCMP "1")]) @@ -5103,31 +5259,65 @@ (set_attr "type" "ssecvt") (set_attr "mode" "V4SF")]) -(define_insn "sse_cvtps2pi" +(define_insn_and_split "sse_cvtps2pi" [(set (match_operand:V2SI 0 "register_operand" "=y,Yv") (vec_select:V2SI - (unspec:V4SI [(match_operand:V4SF 1 "register_mmxmem_operand" "xm,YvBm")] + (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm,YvBm")] UNSPEC_FIX_NOTRUNC) (parallel [(const_int 0) (const_int 1)])))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" "@ cvtps2pi\t{%1, %0|%0, %q1} - %vcvtps2dq\t{%1, %0|%0, %1}" + #" + "TARGET_SSE2 && reload_completed + && SSE_REG_P (operands[0])" + [(const_int 0)] +{ + rtx op1 = lowpart_subreg (V2SFmode, operands[1], + GET_MODE (operands[1])); + rtx tmp = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); + + op1 = gen_rtx_VEC_CONCAT (V4SFmode, op1, CONST0_RTX (V2SFmode)); + emit_insn (gen_rtx_SET (tmp, op1)); + + rtx dest = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); + emit_insn (gen_sse2_fix_notruncv4sfv4si (dest, tmp)); + DONE; +} [(set_attr "isa" "*,sse2") (set_attr "mmx_isa" "native,*") (set_attr "type" "ssecvt") (set_attr "unit" "mmx,*") (set_attr "mode" "DI")]) -(define_insn "sse_cvttps2pi" +(define_insn_and_split "sse_cvttps2pi" [(set (match_operand:V2SI 0 "register_operand" "=y,Yv") (vec_select:V2SI - (fix:V4SI (match_operand:V4SF 1 "register_mmxmem_operand" "xm,YvBm")) + (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm,YvBm")) (parallel [(const_int 0) (const_int 1)])))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" "@ cvttps2pi\t{%1, %0|%0, %q1} - %vcvttps2dq\t{%1, %0|%0, %1}" + #" + "TARGET_SSE2 && reload_completed + && SSE_REG_P (operands[0])" + [(const_int 0)] +{ + rtx op1 = lowpart_subreg (V2SFmode, operands[1], + GET_MODE (operands[1])); + rtx tmp = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); + + op1 = gen_rtx_VEC_CONCAT (V4SFmode, op1, CONST0_RTX (V2SFmode)); + emit_insn (gen_rtx_SET (tmp, op1)); + + rtx dest = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); + emit_insn (gen_fix_truncv4sfv4si2 (dest, tmp)); + DONE; +} [(set_attr "isa" "*,sse2") (set_attr "mmx_isa" "native,*") (set_attr "type" "ssecvt") @@ -8026,7 +8216,7 @@ (define_insn "*vec_concatv4sf_0" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF - (match_operand:V2SF 1 "nonimmediate_operand" "xm") + (match_operand:V2SF 1 "nonimmediate_operand" "vm") (match_operand:V2SF 2 "const0_operand" " C")))] "TARGET_SSE2" "%vmovq\t{%1, %0|%0, %1}" @@ -10457,7 +10647,7 @@ [(set (match_operand:VF2_512_256 0 "register_operand" "=v") (vec_merge:VF2_512_256 (vec_duplicate:VF2_512_256 - (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "xm")) + (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "vm")) (match_operand:VF2_512_256 1 "const0_operand" "C") (const_int 1)))] "TARGET_AVX" @@ -11455,7 +11645,7 @@ "TARGET_SSE2" "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));") -(define_expand "<plusminus_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "vector_operand") @@ -11463,7 +11653,7 @@ "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_expand "<plusminus_insn><mode>3_mask" +(define_expand "<insn><mode>3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand") (vec_merge:VI48_AVX512VL (plusminus:VI48_AVX512VL @@ -11474,7 +11664,7 @@ "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_expand "<plusminus_insn><mode>3_mask" +(define_expand "<insn><mode>3_mask" [(set (match_operand:VI12_AVX512VL 0 "register_operand") (vec_merge:VI12_AVX512VL (plusminus:VI12_AVX512VL @@ -11485,7 +11675,7 @@ "TARGET_AVX512BW" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*<plusminus_insn><mode>3" +(define_insn "*<insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "bcst_vector_operand" "<comm>0,v") @@ -11500,7 +11690,7 @@ (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "*<plusminus_insn><mode>3_mask" +(define_insn "*<insn><mode>3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL (plusminus:VI48_AVX512VL @@ -11514,7 +11704,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "*<plusminus_insn><mode>3_mask" +(define_insn "*<insn><mode>3_mask" [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") (vec_merge:VI12_AVX512VL (plusminus:VI12_AVX512VL @@ -11528,7 +11718,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) -(define_expand "<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" +(define_expand "<sse2_avx2>_<insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand") (sat_plusminus:VI12_AVX2_AVX512BW (match_operand:VI12_AVX2_AVX512BW 1 "vector_operand") @@ -11536,7 +11726,7 @@ "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" +(define_insn "*<sse2_avx2>_<insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2_AVX512BW 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2_AVX512BW (match_operand:VI12_AVX2_AVX512BW 1 "vector_operand" "<comm>0,v") @@ -12282,7 +12472,7 @@ (const_string "0"))) (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<mask_codefor><shift_insn><mode>3<mask_name>" +(define_insn "<mask_codefor><insn><mode>3<mask_name>" [(set (match_operand:VI248_AVX512BW_2 0 "register_operand" "=v,v") (any_lshift:VI248_AVX512BW_2 (match_operand:VI248_AVX512BW_2 1 "nonimmediate_operand" "v,vm") @@ -12296,7 +12486,7 @@ (const_string "0"))) (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<shift_insn><mode>3" +(define_insn "<insn><mode>3" [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x") (any_lshift:VI248_AVX2 (match_operand:VI248_AVX2 1 "register_operand" "0,x") @@ -12315,7 +12505,7 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<shift_insn><mode>3<mask_name>" +(define_insn "<insn><mode>3<mask_name>" [(set (match_operand:VI248_AVX512BW 0 "register_operand" "=v,v") (any_lshift:VI248_AVX512BW (match_operand:VI248_AVX512BW 1 "nonimmediate_operand" "v,m") @@ -12356,7 +12546,7 @@ operands[4] = gen_lowpart (<MODE>mode, operands[3]); }) -(define_insn "avx512bw_<shift_insn><mode>3" +(define_insn "avx512bw_<insn><mode>3" [(set (match_operand:VIMAX_AVX512VL 0 "register_operand" "=v") (any_lshift:VIMAX_AVX512VL (match_operand:VIMAX_AVX512VL 1 "nonimmediate_operand" "vm") @@ -12371,7 +12561,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<sse2_avx2>_<shift_insn><mode>3" +(define_insn "<sse2_avx2>_<insn><mode>3" [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,v") (any_lshift:VIMAX_AVX2 (match_operand:VIMAX_AVX2 1 "register_operand" "0,v") @@ -12699,6 +12889,89 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) +(define_insn_and_split "*avx2_eq<mode>3" + [(set (match_operand:VI_128_256 0 "register_operand") + (vec_merge:VI_128_256 + (match_operand:VI_128_256 1 "vector_all_ones_operand") + (match_operand:VI_128_256 2 "const0_operand") + (unspec:<avx512fmaskmode> + [(match_operand:VI_128_256 3 "nonimmediate_operand") + (match_operand:VI_128_256 4 "nonimmediate_operand")] + UNSPEC_MASKED_EQ)))] + "TARGET_AVX512VL && ix86_pre_reload_split () + && !(MEM_P (operands[3]) && MEM_P (operands[4]))" + "#" + "&& 1" + [(set (match_dup 0) + (eq:VI_128_256 + (match_dup 3) + (match_dup 4)))]) + +(define_insn_and_split "*avx2_pcmp<mode>3_1" + [(set (match_operand:VI_128_256 0 "register_operand") + (vec_merge:VI_128_256 + (match_operand:VI_128_256 1 "vector_all_ones_operand") + (match_operand:VI_128_256 2 "const0_operand") + (unspec:<avx512fmaskmode> + [(match_operand:VI_128_256 3 "nonimmediate_operand") + (match_operand:VI_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_7_operand")] + UNSPEC_PCMP)))] + "TARGET_AVX512VL && ix86_pre_reload_split () + /* EQ is commutative. */ + && ((INTVAL (operands[5]) == 0 + && !(MEM_P (operands[3]) && MEM_P (operands[4]))) + /* NLE aka GT, 3 must be register. */ + || (INTVAL (operands[5]) == 6 + && !MEM_P (operands[3])) + /* LT, 4 must be register and we swap operands. */ + || (INTVAL (operands[5]) == 1 + && !MEM_P (operands[4])))" + "#" + "&& 1" + [(const_int 0)] +{ + if (INTVAL (operands[5]) == 1) + std::swap (operands[3], operands[4]); + enum rtx_code code = INTVAL (operands[5]) ? GT : EQ; + emit_move_insn (operands[0], gen_rtx_fmt_ee (code, <MODE>mode, + operands[3], operands[4])); + DONE; +}) + +(define_insn_and_split "*avx2_pcmp<mode>3_2" + [(set (match_operand:VI_128_256 0 "register_operand") + (vec_merge:VI_128_256 + (match_operand:VI_128_256 1 "vector_all_ones_operand") + (match_operand:VI_128_256 2 "const0_operand") + (not:<avx512fmaskmode> + (unspec:<avx512fmaskmode> + [(match_operand:VI_128_256 3 "nonimmediate_operand") + (match_operand:VI_128_256 4 "nonimmediate_operand") + (match_operand:SI 5 "const_0_to_7_operand")] + UNSPEC_PCMP))))] + "TARGET_AVX512VL && ix86_pre_reload_split () + /* NE is commutative. */ + && ((INTVAL (operands[5]) == 4 + && !(MEM_P (operands[3]) && MEM_P (operands[4]))) + /* LE, 3 must be register. */ + || (INTVAL (operands[5]) == 2 + && !MEM_P (operands[3])) + /* NLT aka GE, 4 must be register and we swap operands. */ + || (INTVAL (operands[5]) == 5 + && !MEM_P (operands[4])))" + "#" + "&& 1" + [(const_int 0)] +{ + if (INTVAL (operands[5]) == 5) + std::swap (operands[3], operands[4]); + enum rtx_code code = INTVAL (operands[5]) != 4 ? GT : EQ; + emit_move_insn (operands[0], gen_rtx_fmt_ee (code, <MODE>mode, + operands[3], operands[4])); + DONE; +}) + (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand") (unspec:<avx512fmaskmode> @@ -12768,7 +13041,7 @@ (eq:VI124_128 (match_operand:VI124_128 1 "vector_operand" "%0,x") (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] - "TARGET_SSE2 && !TARGET_XOP + "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2} @@ -12823,6 +13096,24 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) +(define_insn_and_split "*avx2_gt<mode>3" + [(set (match_operand:VI_128_256 0 "register_operand") + (vec_merge:VI_128_256 + (match_operand:VI_128_256 1 "vector_all_ones_operand") + (match_operand:VI_128_256 2 "const0_operand") + (unspec:<avx512fmaskmode> + [(match_operand:VI_128_256 3 "register_operand") + (match_operand:VI_128_256 4 "nonimmediate_operand")] + UNSPEC_MASKED_GT)))] + "TARGET_AVX512VL + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (gt:VI_128_256 + (match_dup 3) + (match_dup 4)))]) + (define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> @@ -12852,7 +13143,7 @@ (gt:VI124_128 (match_operand:VI124_128 1 "register_operand" "0,x") (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] - "TARGET_SSE2 && !TARGET_XOP" + "TARGET_SSE2" "@ pcmpgt<ssemodesuffix>\t{%2, %0|%0, %2} vpcmpgt<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" @@ -16099,6 +16390,81 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) +(define_insn_and_split "*sse2_pmovskb_zexthisi" + [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI + (subreg:HI + (unspec:SI + [(match_operand:V16QI 1 "register_operand")] + UNSPEC_MOVMSK) 0)))] + "TARGET_SSE2 && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))]) + +(define_split + [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI + (not:HI + (subreg:HI + (unspec:SI + [(match_operand:V16QI 1 "register_operand")] + UNSPEC_MOVMSK) 0))))] + "TARGET_SSE2" + [(set (match_dup 2) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) + (set (match_dup 0) + (xor:SI (match_dup 2) (const_int 65535)))] + "operands[2] = gen_reg_rtx (SImode);") + +(define_split + [(set (match_operand:SI 0 "register_operand") + (unspec:SI + [(not:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand"))] + UNSPEC_MOVMSK))] + "TARGET_SSE2" + [(set (match_dup 2) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) + (set (match_dup 0) (match_dup 3))] +{ + operands[2] = gen_reg_rtx (SImode); + if (GET_MODE_NUNITS (<MODE>mode) == 32) + operands[3] = gen_rtx_NOT (SImode, operands[2]); + else + { + operands[3] + = gen_int_mode ((HOST_WIDE_INT_1 << GET_MODE_NUNITS (<MODE>mode)) - 1, + SImode); + operands[3] = gen_rtx_XOR (SImode, operands[2], operands[3]); + } +}) + +(define_split + [(set (match_operand:SI 0 "register_operand") + (unspec:SI + [(subreg:VI1_AVX2 (not (match_operand 1 "register_operand")) 0)] + UNSPEC_MOVMSK))] + "TARGET_SSE2 + && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_VECTOR_INT + && GET_MODE_SIZE (GET_MODE (operands[1])) == <MODE_SIZE>" + [(set (match_dup 2) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) + (set (match_dup 0) (match_dup 3))] +{ + operands[2] = gen_reg_rtx (SImode); + operands[1] = gen_lowpart (<MODE>mode, operands[1]); + if (GET_MODE_NUNITS (<MODE>mode) == 32) + operands[3] = gen_rtx_NOT (SImode, operands[2]); + else + { + operands[3] + = gen_int_mode ((HOST_WIDE_INT_1 << GET_MODE_NUNITS (<MODE>mode)) - 1, + SImode); + operands[3] = gen_rtx_XOR (SImode, operands[2], operands[3]); + } +}) + (define_insn_and_split "*<sse2_avx2>_pmovmskb_lt" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI @@ -17502,7 +17868,24 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_expand "<code>v16qiv16hi2" +(define_insn_and_split "*avx2_zero_extendv16qiv16hi2_1" + [(set (match_operand:V32QI 0 "register_operand" "=v") + (vec_select:V32QI + (vec_concat:V64QI + (match_operand:V32QI 1 "nonimmediate_operand" "vm") + (match_operand:V32QI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX2" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V16HI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V16HImode, operands[0], V32QImode); + operands[1] = lowpart_subreg (V16QImode, operands[1], V32QImode); +}) + +(define_expand "<insn>v16qiv16hi2" [(set (match_operand:V16HI 0 "register_operand") (any_extend:V16HI (match_operand:V16QI 1 "nonimmediate_operand")))] @@ -17519,7 +17902,24 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "<code>v32qiv32hi2" +(define_insn_and_split "*avx512bw_zero_extendv32qiv32hi2_1" + [(set (match_operand:V64QI 0 "register_operand" "=v") + (vec_select:V64QI + (vec_concat:V128QI + (match_operand:V64QI 1 "nonimmediate_operand" "vm") + (match_operand:V64QI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX512BW" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V32HI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V32HImode, operands[0], V64QImode); + operands[1] = lowpart_subreg (V32QImode, operands[1], V64QImode); +}) + +(define_expand "<insn>v32qiv32hi2" [(set (match_operand:V32HI 0 "register_operand") (any_extend:V32HI (match_operand:V32QI 1 "nonimmediate_operand")))] @@ -17574,7 +17974,38 @@ (any_extend:V8HI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "<code>v8qiv8hi2" +(define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3" + [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,v") + (vec_select:V16QI + (vec_concat:V32QI + (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V16QI 2 "const0_operand" "C,C,C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n,n,n")])))] + "TARGET_SSE4_1" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:V8HI + (vec_select:V8QI + (match_dup 1) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))))] +{ + operands[0] = lowpart_subreg (V8HImode, operands[0], V16QImode); + if (MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V8QImode, operands[1], V16QImode); + operands[1] = gen_rtx_ZERO_EXTEND (V8HImode, operands[1]); + emit_insn (gen_rtx_SET (operands[0], operands[1])); + DONE; + } +} + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_expand "<insn>v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand") (any_extend:V8HI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -17598,7 +18029,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "<code>v16qiv16si2" +(define_expand "<insn>v16qiv16si2" [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16QI 1 "nonimmediate_operand")))] @@ -17651,7 +18082,7 @@ (any_extend:V8SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "<code>v8qiv8si2" +(define_expand "<insn>v8qiv8si2" [(set (match_operand:V8SI 0 "register_operand") (any_extend:V8SI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -17714,7 +18145,7 @@ (any_extend:V4SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);") -(define_expand "<code>v4qiv4si2" +(define_expand "<insn>v4qiv4si2" [(set (match_operand:V4SI 0 "register_operand") (any_extend:V4SI (match_operand:V4QI 1 "nonimmediate_operand")))] @@ -17738,12 +18169,29 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "<code>v16hiv16si2" +(define_expand "<insn>v16hiv16si2" [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16HI 1 "nonimmediate_operand")))] "TARGET_AVX512F") +(define_insn_and_split "avx512f_zero_extendv16hiv16si2_1" + [(set (match_operand:V32HI 0 "register_operand" "=v") + (vec_select:V32HI + (vec_concat:V64HI + (match_operand:V32HI 1 "nonimmediate_operand" "vm") + (match_operand:V32HI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX512F" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V16SI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V16SImode, operands[0], V32HImode); + operands[1] = lowpart_subreg (V16HImode, operands[1], V32HImode); +}) + (define_insn "avx2_<code>v8hiv8si2<mask_name>" [(set (match_operand:V8SI 0 "register_operand" "=v") (any_extend:V8SI @@ -17755,12 +18203,29 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_expand "<code>v8hiv8si2" +(define_expand "<insn>v8hiv8si2" [(set (match_operand:V8SI 0 "register_operand") (any_extend:V8SI (match_operand:V8HI 1 "nonimmediate_operand")))] "TARGET_AVX2") +(define_insn_and_split "avx2_zero_extendv8hiv8si2_1" + [(set (match_operand:V16HI 0 "register_operand" "=v") + (vec_select:V16HI + (vec_concat:V32HI + (match_operand:V16HI 1 "nonimmediate_operand" "vm") + (match_operand:V16HI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX2" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V8SI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V8SImode, operands[0], V16HImode); + operands[1] = lowpart_subreg (V8HImode, operands[1], V16HImode); +}) + (define_insn "sse4_1_<code>v4hiv4si2<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI @@ -17806,7 +18271,7 @@ (any_extend:V4SI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);") -(define_expand "<code>v4hiv4si2" +(define_expand "<insn>v4hiv4si2" [(set (match_operand:V4SI 0 "register_operand") (any_extend:V4SI (match_operand:V4HI 1 "nonimmediate_operand")))] @@ -17820,6 +18285,35 @@ } }) +(define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3" + [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") + (vec_select:V8HI + (vec_concat:V16HI + (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V8HI 2 "const0_operand" "C,C,C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n,n,n")])))] + "TARGET_SSE4_1" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:V4SI + (vec_select:V4HI + (match_dup 1) + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))))] +{ + operands[0] = lowpart_subreg (V4SImode, operands[0], V8HImode); + if (MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V4HImode, operands[1], V8HImode); + operands[1] = gen_rtx_ZERO_EXTEND (V4SImode, operands[1]); + emit_insn (gen_rtx_SET (operands[0], operands[1])); + DONE; + } +} + [(set_attr "isa" "noavx,noavx,avx")]) + (define_insn "avx512f_<code>v8qiv8di2<mask_name>" [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI @@ -17864,7 +18358,7 @@ (any_extend:V8DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);") -(define_expand "<code>v8qiv8di2" +(define_expand "<insn>v8qiv8di2" [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8QI 1 "nonimmediate_operand")))] @@ -17925,7 +18419,7 @@ (any_extend:V4DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);") -(define_expand "<code>v4qiv4di2" +(define_expand "<insn>v4qiv4di2" [(set (match_operand:V4DI 0 "register_operand") (any_extend:V4DI (match_operand:V4QI 1 "nonimmediate_operand")))] @@ -17953,7 +18447,7 @@ (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) -(define_expand "<code>v2qiv2di2" +(define_expand "<insn>v2qiv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2QI 1 "register_operand")))] @@ -17974,7 +18468,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "<code>v8hiv8di2" +(define_expand "<insn>v8hiv8di2" [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8HI 1 "nonimmediate_operand")))] @@ -18023,7 +18517,7 @@ (any_extend:V4DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);") -(define_expand "<code>v4hiv4di2" +(define_expand "<insn>v4hiv4di2" [(set (match_operand:V4DI 0 "register_operand") (any_extend:V4DI (match_operand:V4HI 1 "nonimmediate_operand")))] @@ -18084,7 +18578,7 @@ (any_extend:V2DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V2HImode, 0);") -(define_expand "<code>v2hiv2di2" +(define_expand "<insn>v2hiv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2HI 1 "nonimmediate_operand")))] @@ -18108,7 +18602,24 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "<code>v8siv8di2" +(define_insn_and_split "*avx512f_zero_extendv8siv8di2_1" + [(set (match_operand:V16SI 0 "register_operand" "=v") + (vec_select:V16SI + (vec_concat:V32SI + (match_operand:V16SI 1 "nonimmediate_operand" "vm") + (match_operand:V16SI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX512F" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V8DI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V8DImode, operands[0], V16SImode); + operands[1] = lowpart_subreg (V8SImode, operands[1], V16SImode); +}) + +(define_expand "<insn>v8siv8di2" [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8SI 1 "nonimmediate_operand" "vm")))] @@ -18125,7 +18636,24 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "OI")]) -(define_expand "<code>v4siv4di2" +(define_insn_and_split "*avx2_zero_extendv4siv4di2_1" + [(set (match_operand:V8SI 0 "register_operand" "=v") + (vec_select:V8SI + (vec_concat:V16SI + (match_operand:V8SI 1 "nonimmediate_operand" "vm") + (match_operand:V8SI 2 "const0_operand" "C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n")])))] + "TARGET_AVX2" + "#" + "&& reload_completed" + [(set (match_dup 0) (zero_extend:V4DI (match_dup 1)))] +{ + operands[0] = lowpart_subreg (V4DImode, operands[0], V8SImode); + operands[1] = lowpart_subreg (V4SImode, operands[1], V8SImode); +}) + +(define_expand "<insn>v4siv4di2" [(set (match_operand:V4DI 0 "register_operand" "=v") (any_extend:V4DI (match_operand:V4SI 1 "nonimmediate_operand" "vm")))] @@ -18174,7 +18702,34 @@ (any_extend:V2DI (match_dup 1)))] "operands[1] = adjust_address_nv (operands[1], V2SImode, 0);") -(define_expand "<code>v2siv2di2" +(define_insn_and_split "*sse4_1_zero_extendv2siv2di2_3" + [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") + (vec_select:V4SI + (vec_concat:V8SI + (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm") + (match_operand:V4SI 2 "const0_operand" "C,C,C")) + (match_parallel 3 "pmovzx_parallel" + [(match_operand 4 "const_int_operand" "n,n,n")])))] + "TARGET_SSE4_1" + "#" + "&& reload_completed" + [(set (match_dup 0) + (zero_extend:V2DI + (vec_select:V2SI (match_dup 1) + (parallel [(const_int 0) (const_int 1)]))))] +{ + operands[0] = lowpart_subreg (V2DImode, operands[0], V4SImode); + if (MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V2SImode, operands[1], V4SImode); + operands[1] = gen_rtx_ZERO_EXTEND (V2DImode, operands[1]); + emit_insn (gen_rtx_SET (operands[0], operands[1])); + DONE; + } +} + [(set_attr "isa" "noavx,noavx,avx")]) + +(define_expand "<insn>v2siv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI (match_operand:V2SI 1 "nonimmediate_operand")))] @@ -19713,7 +20268,7 @@ (set_attr "prefix_extra" "2") (set_attr "mode" "TI")]) -(define_expand "<shift_insn><mode>3" +(define_expand "<insn><mode>3" [(set (match_operand:VI1_AVX512 0 "register_operand") (any_shift:VI1_AVX512 (match_operand:VI1_AVX512 1 "register_operand") @@ -21466,7 +22021,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<avx2_avx512>_<shift_insn>v<mode><mask_name>" +(define_insn "<avx2_avx512>_<insn>v<mode><mask_name>" [(set (match_operand:VI48_AVX512F 0 "register_operand" "=v") (any_lshift:VI48_AVX512F (match_operand:VI48_AVX512F 1 "register_operand" "v") @@ -21477,7 +22032,7 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "<avx2_avx512>_<shift_insn>v<mode><mask_name>" +(define_insn "<avx2_avx512>_<insn>v<mode><mask_name>" [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") (any_lshift:VI2_AVX512VL (match_operand:VI2_AVX512VL 1 "register_operand" "v") diff --git a/gcc/config/i386/ssemath.h b/gcc/config/i386/ssemath.h index 96e9677..a26c3e7 100644 --- a/gcc/config/i386/ssemath.h +++ b/gcc/config/i386/ssemath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2020 Free Software Foundation, Inc. +/* Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/stringop.def b/gcc/config/i386/stringop.def index d9bf03c..76898d2 100644 --- a/gcc/config/i386/stringop.def +++ b/gcc/config/i386/stringop.def @@ -1,5 +1,5 @@ /* Definitions for stringop strategy for IA-32. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index e037a96..477a898 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -1,5 +1,5 @@ ;; GCC machine description for AVX512F instructions -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index ed17bb0..c7c508c 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for i386 synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/sysv4.h b/gcc/config/i386/sysv4.h index 20e29f7..a634f53 100644 --- a/gcc/config/i386/sysv4.h +++ b/gcc/config/i386/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running System V.4 - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/t-cygming b/gcc/config/i386/t-cygming index 9251663..7ccbb84 100644 --- a/gcc/config/i386/t-cygming +++ b/gcc/config/i386/t-cygming @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-freebsd64 b/gcc/config/i386/t-freebsd64 index b17d3a6..721f71f 100644 --- a/gcc/config/i386/t-freebsd64 +++ b/gcc/config/i386/t-freebsd64 @@ -1,4 +1,4 @@ -# Copyright (C) 2019-2020 Free Software Foundation, Inc. +# Copyright (C) 2019-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-gnu-property b/gcc/config/i386/t-gnu-property index fd8bbce..ce24233 100644 --- a/gcc/config/i386/t-gnu-property +++ b/gcc/config/i386/t-gnu-property @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2020 Free Software Foundation, Inc. +# Copyright (C) 2017-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-i386 b/gcc/config/i386/t-i386 index e5fb061..66d5a8c 100644 --- a/gcc/config/i386/t-i386 +++ b/gcc/config/i386/t-i386 @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2020 Free Software Foundation, Inc. +# Copyright (C) 2008-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64 index 1171e21..d288b09 100644 --- a/gcc/config/i386/t-linux64 +++ b/gcc/config/i386/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-rtems b/gcc/config/i386/t-rtems index 5f078c6..5f756ca 100644 --- a/gcc/config/i386/t-rtems +++ b/gcc/config/i386/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 1999-2020 Free Software Foundation, Inc. +# Copyright (C) 1999-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-sol2 b/gcc/config/i386/t-sol2 index b34e149..395fab1 100644 --- a/gcc/config/i386/t-sol2 +++ b/gcc/config/i386/t-sol2 @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/tbmintrin.h b/gcc/config/i386/tbmintrin.h index e03bf91..971d1f3 100644 --- a/gcc/config/i386/tbmintrin.h +++ b/gcc/config/i386/tbmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2020 Free Software Foundation, Inc. +/* Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/tmmintrin.h b/gcc/config/i386/tmmintrin.h index fb02bfc..38ff882 100644 --- a/gcc/config/i386/tmmintrin.h +++ b/gcc/config/i386/tmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2020 Free Software Foundation, Inc. +/* Copyright (C) 2006-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/tsxldtrkintrin.h b/gcc/config/i386/tsxldtrkintrin.h index eab36d0..bb42a8e 100644 --- a/gcc/config/i386/tsxldtrkintrin.h +++ b/gcc/config/i386/tsxldtrkintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/uintrintrin.h b/gcc/config/i386/uintrintrin.h index 991f642..2ff0cce 100644 --- a/gcc/config/i386/uintrintrin.h +++ b/gcc/config/i386/uintrintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -38,9 +38,6 @@ struct __uintr_frame { - /* The position of the most significant bit set in user-interrupt - request register. */ - unsigned long long uirrv; /* RIP of the interrupted user process. */ unsigned long long rip; /* RFLAGS of the interrupted user process. */ diff --git a/gcc/config/i386/unix.h b/gcc/config/i386/unix.h index e911c62..fba2a7f 100644 --- a/gcc/config/i386/unix.h +++ b/gcc/config/i386/unix.h @@ -1,5 +1,5 @@ /* Definitions for Unix assembler syntax for the Intel 80386. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h index b66bc19..d934014 100644 --- a/gcc/config/i386/vaesintrin.h +++ b/gcc/config/i386/vaesintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/vpclmulqdqintrin.h b/gcc/config/i386/vpclmulqdqintrin.h index 9ff1fa7..74e3b8d 100644 --- a/gcc/config/i386/vpclmulqdqintrin.h +++ b/gcc/config/i386/vpclmulqdqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/vxworks.h b/gcc/config/i386/vxworks.h index 891b4ff..b3ca224 100644 --- a/gcc/config/i386/vxworks.h +++ b/gcc/config/i386/vxworks.h @@ -1,5 +1,5 @@ /* IA32 VxWorks target definitions for GNU compiler. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. Updated by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/vxworksae.h b/gcc/config/i386/vxworksae.h index 7e7dbba..a224b54 100644 --- a/gcc/config/i386/vxworksae.h +++ b/gcc/config/i386/vxworksae.h @@ -1,5 +1,5 @@ /* IA32 VxWorks AE target definitions for GNU compiler. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/waitpkgintrin.h b/gcc/config/i386/waitpkgintrin.h index 5046c98..a7a4d6a 100644 --- a/gcc/config/i386/waitpkgintrin.h +++ b/gcc/config/i386/waitpkgintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/wbnoinvdintrin.h b/gcc/config/i386/wbnoinvdintrin.h index 7089e61..71dc1b6 100644 --- a/gcc/config/i386/wbnoinvdintrin.h +++ b/gcc/config/i386/wbnoinvdintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt-cxx.c b/gcc/config/i386/winnt-cxx.c index 4d6a75d..91a9a7a 100644 --- a/gcc/config/i386/winnt-cxx.c +++ b/gcc/config/i386/winnt-cxx.c @@ -1,6 +1,6 @@ /* Target support for C++ classes on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt-stubs.c b/gcc/config/i386/winnt-stubs.c index bc54007..9f79a86 100644 --- a/gcc/config/i386/winnt-stubs.c +++ b/gcc/config/i386/winnt-stubs.c @@ -1,6 +1,6 @@ /* Dummy subroutines for language-specific support on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index 2ccd591..962c88e 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for Windows NT. Contributed by Douglas Rupp (drupp@cs.washington.edu) - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/wmmintrin.h b/gcc/config/i386/wmmintrin.h index e3ea181..7f2a5b0 100644 --- a/gcc/config/i386/wmmintrin.h +++ b/gcc/config/i386/wmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x-mingw32 b/gcc/config/i386/x-mingw32 index 2754c93..b7e0493 100644 --- a/gcc/config/i386/x-mingw32 +++ b/gcc/config/i386/x-mingw32 @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/x86-64.h b/gcc/config/i386/x86-64.h index 0c5b8af..0cdd980 100644 --- a/gcc/config/i386/x86-64.h +++ b/gcc/config/i386/x86-64.h @@ -1,5 +1,5 @@ /* OS independent definitions for AMD x86-64. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 5de4149..cc27c79 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1,5 +1,5 @@ /* Costs of operations of individual x86 CPUs. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune-sched-atom.c b/gcc/config/i386/x86-tune-sched-atom.c index 1318efa..cfb0c65 100644 --- a/gcc/config/i386/x86-tune-sched-atom.c +++ b/gcc/config/i386/x86-tune-sched-atom.c @@ -1,5 +1,5 @@ /* Scheduler hooks for IA-32 which implement atom+ specific logic. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune-sched-bd.c b/gcc/config/i386/x86-tune-sched-bd.c index 8c2abc4..d696643 100644 --- a/gcc/config/i386/x86-tune-sched-bd.c +++ b/gcc/config/i386/x86-tune-sched-bd.c @@ -1,5 +1,5 @@ /* Scheduler hooks for IA-32 which implement bdver1-4 specific logic. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune-sched-core.c b/gcc/config/i386/x86-tune-sched-core.c index 076368c..729cca3 100644 --- a/gcc/config/i386/x86-tune-sched-core.c +++ b/gcc/config/i386/x86-tune-sched-core.c @@ -1,5 +1,5 @@ /* Scheduler hooks for IA-32 which implement bdver1-4 specific logic. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune-sched.c b/gcc/config/i386/x86-tune-sched.c index 404b5b1..2bcc64b 100644 --- a/gcc/config/i386/x86-tune-sched.c +++ b/gcc/config/i386/x86-tune-sched.c @@ -1,5 +1,5 @@ /* Scheduler hooks for IA-32 which implement CPU specific logic. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index ed4d74c..7ace8da 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -1,5 +1,5 @@ /* Definitions of x86 tunable features. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86gprintrin.h b/gcc/config/i386/x86gprintrin.h index ffe07e4..ceda501 100644 --- a/gcc/config/i386/x86gprintrin.h +++ b/gcc/config/i386/x86gprintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2020 Free Software Foundation, Inc. +/* Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index bc6cb40..1b8dcac 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xm-cygwin.h b/gcc/config/i386/xm-cygwin.h index 8e88369..f283857 100644 --- a/gcc/config/i386/xm-cygwin.h +++ b/gcc/config/i386/xm-cygwin.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows NT. using a unix style C library. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xm-djgpp.h b/gcc/config/i386/xm-djgpp.h index 299ef0a..f53b348a 100644 --- a/gcc/config/i386/xm-djgpp.h +++ b/gcc/config/i386/xm-djgpp.h @@ -1,5 +1,5 @@ /* Configuration for GCC for Intel 80386 running DJGPP. - Copyright (C) 1988-2020 Free Software Foundation, Inc. + Copyright (C) 1988-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xm-mingw32.h b/gcc/config/i386/xm-mingw32.h index af23455..a2216d2 100644 --- a/gcc/config/i386/xm-mingw32.h +++ b/gcc/config/i386/xm-mingw32.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows32. using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h index c6f1c01..f013f5c 100644 --- a/gcc/config/i386/xmmintrin.h +++ b/gcc/config/i386/xmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -1022,7 +1022,7 @@ _mm_move_ss (__m128 __A, __m128 __B) extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_extract_pi16 (__m64 const __A, int const __N) { - return __builtin_ia32_vec_ext_v4hi ((__v4hi)__A, __N); + return (unsigned short) __builtin_ia32_vec_ext_v4hi ((__v4hi)__A, __N); } extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -1032,7 +1032,7 @@ _m_pextrw (__m64 const __A, int const __N) } #else #define _mm_extract_pi16(A, N) \ - ((int) __builtin_ia32_vec_ext_v4hi ((__v4hi)(__m64)(A), (int)(N))) + ((int) (unsigned short) __builtin_ia32_vec_ext_v4hi ((__v4hi)(__m64)(A), (int)(N))) #define _m_pextrw(A, N) _mm_extract_pi16(A, N) #endif diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h index 49bac22..b95ef48 100644 --- a/gcc/config/i386/xopintrin.h +++ b/gcc/config/i386/xopintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2020 Free Software Foundation, Inc. +/* Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -208,6 +208,12 @@ _mm_cmov_si128(__m128i __A, __m128i __B, __m128i __C) return (__m128i) __builtin_ia32_vpcmov (__A, __B, __C); } +extern __inline __m256i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_cmov_si256(__m256i __A, __m256i __B, __m256i __C) +{ + return (__m256i) __builtin_ia32_vpcmov256 (__A, __B, __C); +} + extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_perm_epi8(__m128i __A, __m128i __B, __m128i __C) { diff --git a/gcc/config/i386/xsavecintrin.h b/gcc/config/i386/xsavecintrin.h index 06c9f36..45751a0 100644 --- a/gcc/config/i386/xsavecintrin.h +++ b/gcc/config/i386/xsavecintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveintrin.h b/gcc/config/i386/xsaveintrin.h index f9cac0d..56e6a1e 100644 --- a/gcc/config/i386/xsaveintrin.h +++ b/gcc/config/i386/xsaveintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveoptintrin.h b/gcc/config/i386/xsaveoptintrin.h index 4f2756b..ba076ce 100644 --- a/gcc/config/i386/xsaveoptintrin.h +++ b/gcc/config/i386/xsaveoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsavesintrin.h b/gcc/config/i386/xsavesintrin.h index 629a1f3..969835f 100644 --- a/gcc/config/i386/xsavesintrin.h +++ b/gcc/config/i386/xsavesintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2020 Free Software Foundation, Inc. +/* Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xtestintrin.h b/gcc/config/i386/xtestintrin.h index 757cc34..39d18af 100644 --- a/gcc/config/i386/xtestintrin.h +++ b/gcc/config/i386/xtestintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2020 Free Software Foundation, Inc. +/* Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index b0edfab..fc4af22 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/constraints.md b/gcc/config/ia64/constraints.md index 54aea7b..f243df1 100644 --- a/gcc/config/ia64/constraints.md +++ b/gcc/config/ia64/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for IA-64 -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md index 86eeff9..4d46129 100644 --- a/gcc/config/ia64/div.md +++ b/gcc/config/ia64/div.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/elf.h b/gcc/config/ia64/elf.h index e2cd5ec..eced682 100644 --- a/gcc/config/ia64/elf.h +++ b/gcc/config/ia64/elf.h @@ -1,6 +1,6 @@ /* Definitions for embedded ia64-elf target. -Copyright (C) 2000-2020 Free Software Foundation, Inc. +Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/freebsd.h b/gcc/config/ia64/freebsd.h index 1a20502..5c1c99c 100644 --- a/gcc/config/ia64/freebsd.h +++ b/gcc/config/ia64/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Intel IA-64 running FreeBSD using the ELF format - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/ia64/hpux.h b/gcc/config/ia64/hpux.h index e19797c..5e4e055 100644 --- a/gcc/config/ia64/hpux.h +++ b/gcc/config/ia64/hpux.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Steve Ellcey <sje@cup.hp.com> and Reva Cuthbertson <reva@cup.hp.com> diff --git a/gcc/config/ia64/ia64-c.c b/gcc/config/ia64/ia64-c.c index d6c2215..6363e9f 100644 --- a/gcc/config/ia64/ia64-c.c +++ b/gcc/config/ia64/ia64-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for GNU compiler. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Steve Ellcey <sje@cup.hp.com> This file is part of GCC. diff --git a/gcc/config/ia64/ia64-modes.def b/gcc/config/ia64/ia64-modes.def index 840456f..9b6c7ae 100644 --- a/gcc/config/ia64/ia64-modes.def +++ b/gcc/config/ia64/ia64-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64-opts.h b/gcc/config/ia64/ia64-opts.h index 31944fe..11f06ad 100644 --- a/gcc/config/ia64/ia64-opts.h +++ b/gcc/config/ia64/ia64-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IA-64. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h index c5d8984..f25f091 100644 --- a/gcc/config/ia64/ia64-protos.h +++ b/gcc/config/ia64/ia64-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for IA-64. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 7075d6a..f1a6de1 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. @@ -11759,6 +11759,15 @@ ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, unsigned int i, nelt, which; d.target = target; + if (op0) + { + rtx nop0 = force_reg (vmode, op0); + if (op0 == op1) + op1 = nop0; + op0 = nop0; + } + if (op1) + op1 = force_reg (vmode, op1); d.op0 = op0; d.op1 = op1; diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index d5acc62..3d86847 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 15a0a02..0299955 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -1,5 +1,5 @@ ;; IA-64 Machine description template -;; Copyright (C) 1999-2020 Free Software Foundation, Inc. +;; Copyright (C) 1999-2021 Free Software Foundation, Inc. ;; Contributed by James E. Wilson <wilson@cygnus.com> and ;; David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64.opt b/gcc/config/ia64/ia64.opt index 05b9d32..520f97f 100644 --- a/gcc/config/ia64/ia64.opt +++ b/gcc/config/ia64/ia64.opt @@ -1,4 +1,4 @@ -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -24,23 +24,23 @@ Variable enum processor_type ia64_tune = PROCESSOR_ITANIUM2 mbig-endian -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Generate big endian code. mlittle-endian -Target Report RejectNegative InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Generate little endian code. mgnu-as -Target Report Mask(GNU_AS) +Target Mask(GNU_AS) Generate code for GNU as. mgnu-ld -Target Report Mask(GNU_LD) +Target Mask(GNU_LD) Generate code for GNU ld. mvolatile-asm-stop -Target Report Mask(VOL_ASM_STOP) +Target Mask(VOL_ASM_STOP) Emit stop bits before and after volatile extended asms. mregister-names @@ -48,65 +48,65 @@ Target Mask(REG_NAMES) Use in/loc/out register names. mno-sdata -Target Report RejectNegative Mask(NO_SDATA) +Target RejectNegative Mask(NO_SDATA) msdata -Target Report RejectNegative InverseMask(NO_SDATA) +Target RejectNegative InverseMask(NO_SDATA) Enable use of sdata/scommon/sbss. mno-pic -Target Report RejectNegative Mask(NO_PIC) +Target RejectNegative Mask(NO_PIC) Generate code without GP reg. mconstant-gp -Target Report RejectNegative Mask(CONST_GP) +Target RejectNegative Mask(CONST_GP) gp is constant (but save/restore gp on indirect calls). mauto-pic -Target Report RejectNegative Mask(AUTO_PIC) +Target RejectNegative Mask(AUTO_PIC) Generate self-relocatable code. minline-float-divide-min-latency -Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1) +Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1) Generate inline floating point division, optimize for latency. minline-float-divide-max-throughput -Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2) +Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2) Generate inline floating point division, optimize for throughput. mno-inline-float-divide -Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0) +Target RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0) minline-int-divide-min-latency -Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1) +Target RejectNegative Var(TARGET_INLINE_INT_DIV, 1) Generate inline integer division, optimize for latency. minline-int-divide-max-throughput -Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2) +Target RejectNegative Var(TARGET_INLINE_INT_DIV, 2) Generate inline integer division, optimize for throughput. mno-inline-int-divide -Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0) +Target RejectNegative Var(TARGET_INLINE_INT_DIV, 0) Do not inline integer division. minline-sqrt-min-latency -Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1) +Target RejectNegative Var(TARGET_INLINE_SQRT, 1) Generate inline square root, optimize for latency. minline-sqrt-max-throughput -Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2) +Target RejectNegative Var(TARGET_INLINE_SQRT, 2) Generate inline square root, optimize for throughput. mno-inline-sqrt -Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0) +Target RejectNegative Var(TARGET_INLINE_SQRT, 0) Do not inline square root. mdwarf2-asm -Target Report Mask(DWARF2_ASM) +Target Mask(DWARF2_ASM) Enable DWARF line debug info via GNU as. mearly-stop-bits -Target Report Mask(EARLY_STOP_BITS) +Target Mask(EARLY_STOP_BITS) Enable earlier placing stop bits for better scheduling. mfixed-range= @@ -132,35 +132,35 @@ EnumValue Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2) msched-br-data-spec -Target Report Var(mflag_sched_br_data_spec) Init(0) +Target Var(mflag_sched_br_data_spec) Init(0) Use data speculation before reload. msched-ar-data-spec -Target Report Var(mflag_sched_ar_data_spec) Init(1) +Target Var(mflag_sched_ar_data_spec) Init(1) Use data speculation after reload. msched-control-spec -Target Report Var(mflag_sched_control_spec) Init(2) +Target Var(mflag_sched_control_spec) Init(2) Use control speculation. msched-br-in-data-spec -Target Report Var(mflag_sched_br_in_data_spec) Init(1) +Target Var(mflag_sched_br_in_data_spec) Init(1) Use in block data speculation before reload. msched-ar-in-data-spec -Target Report Var(mflag_sched_ar_in_data_spec) Init(1) +Target Var(mflag_sched_ar_in_data_spec) Init(1) Use in block data speculation after reload. msched-in-control-spec -Target Report Var(mflag_sched_in_control_spec) Init(1) +Target Var(mflag_sched_in_control_spec) Init(1) Use in block control speculation. msched-spec-ldc -Target Report Var(mflag_sched_spec_ldc) Init(1) +Target Var(mflag_sched_spec_ldc) Init(1) Use simple data speculation check. msched-spec-control-ldc -Target Report Var(mflag_sched_spec_control_ldc) Init(0) +Target Var(mflag_sched_spec_control_ldc) Init(0) Use simple data speculation check for control speculation. msched-prefer-non-data-spec-insns @@ -170,15 +170,15 @@ msched-prefer-non-control-spec-insns Target WarnRemoved msched-count-spec-in-critical-path -Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0) +Target Var(mflag_sched_count_spec_in_critical_path) Init(0) Count speculative dependencies while calculating priority of instructions. msched-stop-bits-after-every-cycle -Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1) +Target Var(mflag_sched_stop_bits_after_every_cycle) Init(1) Place a stop bit after every cycle when scheduling. msched-fp-mem-deps-zero-cost -Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0) +Target Var(mflag_sched_fp_mem_deps_zero_cost) Init(0) Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group. msched-max-memory-insns= @@ -186,11 +186,11 @@ Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1) Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1. msched-max-memory-insns-hard-limit -Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0) +Target Var(mflag_sched_mem_insns_hard_limit) Init(0) Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached). msel-sched-dont-check-control-spec -Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0) +Target Var(mflag_sel_sched_dont_check_control_spec) Init(0) Don't generate checks for control speculation in selective scheduling. ; This comment is to ensure we retain the blank line above. diff --git a/gcc/config/ia64/ilp32.opt b/gcc/config/ia64/ilp32.opt index 2083a25..5c9a5a3 100644 --- a/gcc/config/ia64/ilp32.opt +++ b/gcc/config/ia64/ilp32.opt @@ -1,7 +1,7 @@ milp32 -Target Report RejectNegative Mask(ILP32) +Target RejectNegative Mask(ILP32) Generate ILP32 code. mlp64 -Target Report RejectNegative InverseMask(ILP32) +Target RejectNegative InverseMask(ILP32) Generate LP64 code. diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md index c95ff04..800585d 100644 --- a/gcc/config/ia64/itanium2.md +++ b/gcc/config/ia64/itanium2.md @@ -1,5 +1,5 @@ ;; Itanium2 DFA descriptions for insn scheduling and bundling. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. ;; ;; This file is part of GCC. diff --git a/gcc/config/ia64/linux.h b/gcc/config/ia64/linux.h index ee38e21..ac40c3d 100644 --- a/gcc/config/ia64/linux.h +++ b/gcc/config/ia64/linux.h @@ -1,6 +1,6 @@ /* Definitions for ia64-linux target. -Copyright (C) 2000-2020 Free Software Foundation, Inc. +Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md index 70e4e13..113d531 100644 --- a/gcc/config/ia64/predicates.md +++ b/gcc/config/ia64/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for IA-64. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md index 99d96a7..6bf3145 100644 --- a/gcc/config/ia64/sync.md +++ b/gcc/config/ia64/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for IA-64 synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/sysv4.h b/gcc/config/ia64/sysv4.h index 108ec9a..a4133d3 100644 --- a/gcc/config/ia64/sysv4.h +++ b/gcc/config/ia64/sysv4.h @@ -1,6 +1,6 @@ /* Override definitions in elfos.h to be correct for IA64. -Copyright (C) 2000-2020 Free Software Foundation, Inc. +Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/t-hpux b/gcc/config/ia64/t-hpux index f693cae..1aa01e0 100644 --- a/gcc/config/ia64/t-hpux +++ b/gcc/config/ia64/t-hpux @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ia64/t-ia64 b/gcc/config/ia64/t-ia64 index 10ef7ed..a8361f3 100644 --- a/gcc/config/ia64/t-ia64 +++ b/gcc/config/ia64/t-ia64 @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2020 Free Software Foundation, Inc. +# Copyright (C) 2000-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index da8f0f5..1a24522 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -1,5 +1,5 @@ ;; IA-64 machine description for vector operations. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/vms.h b/gcc/config/ia64/vms.h index e14349a..ff285ae 100644 --- a/gcc/config/ia64/vms.h +++ b/gcc/config/ia64/vms.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA64-VMS version. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/ia64/vms.opt b/gcc/config/ia64/vms.opt index 69296e6..6c8e975 100644 --- a/gcc/config/ia64/vms.opt +++ b/gcc/config/ia64/vms.opt @@ -1,6 +1,6 @@ ; IA64 VMS options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/initfini-array.h b/gcc/config/initfini-array.h index 3c025e5..cf46547 100644 --- a/gcc/config/initfini-array.h +++ b/gcc/config/initfini-array.h @@ -1,6 +1,6 @@ /* Definitions for ELF systems with .init_array/.fini_array section support. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/abi b/gcc/config/iq2000/abi index 980a646..7a49908 100644 --- a/gcc/config/iq2000/abi +++ b/gcc/config/iq2000/abi @@ -232,7 +232,7 @@ caller passing as a "hidden" first argument a pointer to space allocated to receive the return value. -Copyright (C) 2003-2020 Free Software Foundation, Inc. +Copyright (C) 2003-2021 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/iq2000/constraints.md b/gcc/config/iq2000/constraints.md index 57f3b00..49c59e6 100644 --- a/gcc/config/iq2000/constraints.md +++ b/gcc/config/iq2000/constraints.md @@ -1,5 +1,5 @@ ;; Constraints for Vitesse IQ2000 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000-opts.h b/gcc/config/iq2000/iq2000-opts.h index 170229b..5e23aeb 100644 --- a/gcc/config/iq2000/iq2000-opts.h +++ b/gcc/config/iq2000/iq2000-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Vitesse IQ2000 processors. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000-protos.h b/gcc/config/iq2000/iq2000-protos.h index e9db1fb..325ede7 100644 --- a/gcc/config/iq2000/iq2000-protos.h +++ b/gcc/config/iq2000/iq2000-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for iq2000. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c index d956518..95a87d3 100644 --- a/gcc/config/iq2000/iq2000.c +++ b/gcc/config/iq2000/iq2000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Vitesse IQ2000 processors - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index 2a257e5..8a6ca22 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Vitesse IQ2000 processors - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md index afd0e63..fd25e05 100644 --- a/gcc/config/iq2000/iq2000.md +++ b/gcc/config/iq2000/iq2000.md @@ -1,5 +1,5 @@ ;; iq2000.md Machine Description for Vitesse IQ2000 processors -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.opt b/gcc/config/iq2000/iq2000.opt index 11eb180..df2ee20 100644 --- a/gcc/config/iq2000/iq2000.opt +++ b/gcc/config/iq2000/iq2000.opt @@ -1,6 +1,6 @@ ; Options for the Vitesse IQ2000 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md index 387925d..b3023c1 100644 --- a/gcc/config/iq2000/predicates.md +++ b/gcc/config/iq2000/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Vitesse IQ2000. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/kfreebsd-gnu.h b/gcc/config/kfreebsd-gnu.h index 6ba43a9..040abbb 100644 --- a/gcc/config/kfreebsd-gnu.h +++ b/gcc/config/kfreebsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for kFreeBSD-based GNU systems with ELF format - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/kopensolaris-gnu.h b/gcc/config/kopensolaris-gnu.h index 36b84c5..5429fc9 100644 --- a/gcc/config/kopensolaris-gnu.h +++ b/gcc/config/kopensolaris-gnu.h @@ -1,5 +1,5 @@ /* Definitions for kOpenSolaris-based GNU systems with ELF format - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/linux-android.h b/gcc/config/linux-android.h index 0bd6184..4883b0a 100644 --- a/gcc/config/linux-android.h +++ b/gcc/config/linux-android.h @@ -1,5 +1,5 @@ /* Configuration file for Linux Android targets. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Doug Kwan (dougkwan@google.com) Rewritten by CodeSourcery, Inc. diff --git a/gcc/config/linux-android.opt b/gcc/config/linux-android.opt index 665387e..6181c27 100644 --- a/gcc/config/linux-android.opt +++ b/gcc/config/linux-android.opt @@ -1,6 +1,6 @@ ; Android specific options. -; Copyright (C) 2008-2020 Free Software Foundation, Inc. +; Copyright (C) 2008-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. mandroid -Target Report Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0) +Target Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0) Generate code for the Android platform. tno-android-cc diff --git a/gcc/config/linux-protos.h b/gcc/config/linux-protos.h index c52778b..17f0c89 100644 --- a/gcc/config/linux-protos.h +++ b/gcc/config/linux-protos.h @@ -1,5 +1,5 @@ /* Prototypes. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/linux.c b/gcc/config/linux.c index 83ffff4..89b3eb1 100644 --- a/gcc/config/linux.c +++ b/gcc/config/linux.c @@ -1,5 +1,5 @@ /* Functions for Linux Android as target machine for GNU C compiler. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/linux.h b/gcc/config/linux.h index 95654bc..4e1db60 100644 --- a/gcc/config/linux.h +++ b/gcc/config/linux.h @@ -2,7 +2,7 @@ MMU, using ELF at the compiler level but possibly FLT for final linked executables and shared libraries in some no-MMU cases, and possibly with a choice of libc implementations. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org). diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt index bd4a625..716d6b7 100644 --- a/gcc/config/linux.opt +++ b/gcc/config/linux.opt @@ -1,6 +1,6 @@ ; Processor-independent options for GNU/Linux. ; -; Copyright (C) 2006-2020 Free Software Foundation, Inc. +; Copyright (C) 2006-2021 Free Software Foundation, Inc. ; Contributed by CodeSourcery. ; ; This file is part of GCC. @@ -20,17 +20,17 @@ ; <http://www.gnu.org/licenses/>. mbionic -Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc) +Target RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc) Use Bionic C library. mglibc -Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) +Target RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) Use GNU C library. muclibc -Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl) +Target RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl) Use uClibc C library. mmusl -Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic) +Target RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic) Use musl C library. diff --git a/gcc/config/lm32/constraints.md b/gcc/config/lm32/constraints.md index 24db7cd..ea5467b 100644 --- a/gcc/config/lm32/constraints.md +++ b/gcc/config/lm32/constraints.md @@ -1,7 +1,7 @@ ;; Constraint definitions for Lattice Mico32 architecture. ;; Contributed by Jon Beniston <jon@beniston.com> ;; -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/lm32/lm32-protos.h b/gcc/config/lm32/lm32-protos.h index d5184ca..367ba92 100644 --- a/gcc/config/lm32/lm32-protos.h +++ b/gcc/config/lm32/lm32-protos.h @@ -1,7 +1,7 @@ /* Prototypes of target machine functions, Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c index 9bc3824..9e442cf 100644 --- a/gcc/config/lm32/lm32.c +++ b/gcc/config/lm32/lm32.c @@ -1,7 +1,7 @@ /* Subroutines used for code generation on the Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h index 8482104..a13c0c5 100644 --- a/gcc/config/lm32/lm32.h +++ b/gcc/config/lm32/lm32.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GNU compiler, Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md index 4ef4d93..aa18aa8 100644 --- a/gcc/config/lm32/lm32.md +++ b/gcc/config/lm32/lm32.md @@ -1,7 +1,7 @@ ;; Machine description of the Lattice Mico32 architecture for GNU C compiler. ;; Contributed by Jon Beniston <jon@beniston.com> -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/lm32/lm32.opt b/gcc/config/lm32/lm32.opt index c19a183..7020d46 100644 --- a/gcc/config/lm32/lm32.opt +++ b/gcc/config/lm32/lm32.opt @@ -1,7 +1,7 @@ ; Options for the Lattice Mico32 port of the compiler. ; Contributed by Jon Beniston <jon@beniston.com> ; -; Copyright (C) 2009-2020 Free Software Foundation, Inc. +; Copyright (C) 2009-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -20,21 +20,21 @@ ; <http://www.gnu.org/licenses/>. mmultiply-enabled -Target Report Mask(MULTIPLY_ENABLED) +Target Mask(MULTIPLY_ENABLED) Enable multiply instructions. mdivide-enabled -Target Report Mask(DIVIDE_ENABLED) +Target Mask(DIVIDE_ENABLED) Enable divide and modulus instructions. mbarrel-shift-enabled -Target Report Mask(BARREL_SHIFT_ENABLED) +Target Mask(BARREL_SHIFT_ENABLED) Enable barrel shift instructions. msign-extend-enabled -Target Report Mask(SIGN_EXTEND_ENABLED) +Target Mask(SIGN_EXTEND_ENABLED) Enable sign extend instructions. muser-enabled -Target Report Mask(USER_ENABLED) +Target Mask(USER_ENABLED) Enable user-defined instructions. diff --git a/gcc/config/lm32/predicates.md b/gcc/config/lm32/predicates.md index a6f7667..1f95c05 100644 --- a/gcc/config/lm32/predicates.md +++ b/gcc/config/lm32/predicates.md @@ -1,7 +1,7 @@ ;; Predicate definitions for Lattice Mico32 architecture. ;; Contributed by Jon Beniston <jon@beniston.com> ;; -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/lm32/rtems.h b/gcc/config/lm32/rtems.h index 912e988..3c67642 100644 --- a/gcc/config/lm32/rtems.h +++ b/gcc/config/lm32/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a lm32 using ELF. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/uclinux-elf.h b/gcc/config/lm32/uclinux-elf.h index a459ccd..370df4c5 100644 --- a/gcc/config/lm32/uclinux-elf.h +++ b/gcc/config/lm32/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for LM32 running Linux-based GNU systems using ELF - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> This file is part of GCC. diff --git a/gcc/config/lynx.h b/gcc/config/lynx.h index 2c9ed81..020cc97 100644 --- a/gcc/config/lynx.h +++ b/gcc/config/lynx.h @@ -1,5 +1,5 @@ /* Target independent definitions for LynxOS. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lynx.opt b/gcc/config/lynx.opt index 927c9e1..d985bac 100644 --- a/gcc/config/lynx.opt +++ b/gcc/config/lynx.opt @@ -1,6 +1,6 @@ ; Processor-independent options for LynxOS. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md index 8c88878..fd00773 100644 --- a/gcc/config/m32c/addsub.md +++ b/gcc/config/m32c/addsub.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md index c87a848..8573aeb 100644 --- a/gcc/config/m32c/bitops.md +++ b/gcc/config/m32c/bitops.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/blkmov.md b/gcc/config/m32c/blkmov.md index 23557e5..c140509 100644 --- a/gcc/config/m32c/blkmov.md +++ b/gcc/config/m32c/blkmov.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md index b73ded7..b80b103 100644 --- a/gcc/config/m32c/cond.md +++ b/gcc/config/m32c/cond.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/constraints.md b/gcc/config/m32c/constraints.md index 93afc2d..5e18821 100644 --- a/gcc/config/m32c/constraints.md +++ b/gcc/config/m32c/constraints.md @@ -1,5 +1,5 @@ ;; m32c constraints -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md index 20858b4..4e93c95 100644 --- a/gcc/config/m32c/jump.md +++ b/gcc/config/m32c/jump.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/m32c-modes.def b/gcc/config/m32c/m32c-modes.def index db0be03..b5c613c 100644 --- a/gcc/config/m32c/m32c-modes.def +++ b/gcc/config/m32c/m32c-modes.def @@ -1,5 +1,5 @@ /* Target-Specific Modes for R8C/M16C/M32C - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c-pragma.c b/gcc/config/m32c/m32c-pragma.c index 754c334..54c09e5 100644 --- a/gcc/config/m32c/m32c-pragma.c +++ b/gcc/config/m32c/m32c-pragma.c @@ -1,5 +1,5 @@ /* M32C Pragma support - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h index 681b197..bebeff9 100644 --- a/gcc/config/m32c/m32c-protos.h +++ b/gcc/config/m32c/m32c-protos.h @@ -1,5 +1,5 @@ /* Target Prototypes for R8C/M16C/M32C - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.abi b/gcc/config/m32c/m32c.abi index 2a4cc1f..5f56a95 100644 --- a/gcc/config/m32c/m32c.abi +++ b/gcc/config/m32c/m32c.abi @@ -1,5 +1,5 @@ Target Definitions for R8C/M16C/M32C - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 01185f9..b1cb359 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -1,5 +1,5 @@ /* Target Code for R8C/M16C/M32C - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h index 895f8f3..635f592 100644 --- a/gcc/config/m32c/m32c.h +++ b/gcc/config/m32c/m32c.h @@ -1,5 +1,5 @@ /* Target Definitions for R8C/M16C/M32C - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md index eb39631..13aee2a 100644 --- a/gcc/config/m32c/m32c.md +++ b/gcc/config/m32c/m32c.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/m32c.opt b/gcc/config/m32c/m32c.opt index 48d9431..d414b45 100644 --- a/gcc/config/m32c/m32c.opt +++ b/gcc/config/m32c/m32c.opt @@ -1,5 +1,5 @@ ; Target Options for R8C/M16C/M32C -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. diff --git a/gcc/config/m32c/minmax.md b/gcc/config/m32c/minmax.md index e8fb2d5..e3ff148 100644 --- a/gcc/config/m32c/minmax.md +++ b/gcc/config/m32c/minmax.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md index 10ba712..b26ea54 100644 --- a/gcc/config/m32c/mov.md +++ b/gcc/config/m32c/mov.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md index 81edaba..ca2c1b4 100644 --- a/gcc/config/m32c/muldiv.md +++ b/gcc/config/m32c/muldiv.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md index 51ead56..dae5189 100644 --- a/gcc/config/m32c/predicates.md +++ b/gcc/config/m32c/predicates.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md index 1ce4d55..f4347af 100644 --- a/gcc/config/m32c/prologue.md +++ b/gcc/config/m32c/prologue.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/rtems.h b/gcc/config/m32c/rtems.h index 5413e27..80b69ec 100644 --- a/gcc/config/m32c/rtems.h +++ b/gcc/config/m32c/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a M32C using ELF. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/m32c/shift.md b/gcc/config/m32c/shift.md index 7d1c531..c26b637 100644 --- a/gcc/config/m32c/shift.md +++ b/gcc/config/m32c/shift.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/t-m32c b/gcc/config/m32c/t-m32c index eecd327..b637239 100644 --- a/gcc/config/m32c/t-m32c +++ b/gcc/config/m32c/t-m32c @@ -1,5 +1,5 @@ # Target Makefile Fragment for R8C/M16C/M32C -# Copyright (C) 2005-2020 Free Software Foundation, Inc. +# Copyright (C) 2005-2021 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/m32r/constraints.md b/gcc/config/m32r/constraints.md index ef84c8c..8f06566 100644 --- a/gcc/config/m32r/constraints.md +++ b/gcc/config/m32r/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas M32R cpu for GNU C compiler -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32r/linux.h b/gcc/config/m32r/linux.h index f498372..4fdebbc 100644 --- a/gcc/config/m32r/linux.h +++ b/gcc/config/m32r/linux.h @@ -1,5 +1,5 @@ /* Definitions for Renesas M32R running Linux-based GNU systems using ELF. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/little.h b/gcc/config/m32r/little.h index ecbaf34..7c96b3d 100644 --- a/gcc/config/m32r/little.h +++ b/gcc/config/m32r/little.h @@ -1,5 +1,5 @@ /* Definitions for Renesas little endian M32R cpu. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r-opts.h b/gcc/config/m32r/m32r-opts.h index eaa43e2..c81dbfa 100644 --- a/gcc/config/m32r/m32r-opts.h +++ b/gcc/config/m32r/m32r-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Renesas M32R cpu. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r-protos.h b/gcc/config/m32r/m32r-protos.h index 7da88df..23313fb 100644 --- a/gcc/config/m32r/m32r-protos.h +++ b/gcc/config/m32r/m32r-protos.h @@ -1,5 +1,5 @@ /* Prototypes for m32r.c functions used in the md file & elsewhere. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index 27fb495..3444ed4 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Renesas M32R cpu. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 4ef834b..83a4b0b 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Renesas M32R cpu. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index 6ecd9ce..ae73459 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1,5 +1,5 @@ ;; Machine description of the Renesas M32R cpu for GNU C compiler -;; Copyright (C) 1996-2020 Free Software Foundation, Inc. +;; Copyright (C) 1996-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/m32r/m32r.opt b/gcc/config/m32r/m32r.opt index 0ecafc9..1d37e15 100644 --- a/gcc/config/m32r/m32r.opt +++ b/gcc/config/m32r/m32r.opt @@ -1,6 +1,6 @@ ; Options for the Renesas M32R port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -30,11 +30,11 @@ Variable enum m32r_sdata m32r_sdata_selected = M32R_SDATA_DEFAULT m32rx -Target Report RejectNegative Mask(M32RX) +Target RejectNegative Mask(M32RX) Compile for the m32rx. m32r2 -Target Report RejectNegative Mask(M32R2) +Target RejectNegative Mask(M32R2) Compile for the m32r2. m32r @@ -42,15 +42,15 @@ Target RejectNegative Compile for the m32r. malign-loops -Target Report Mask(ALIGN_LOOPS) +Target Mask(ALIGN_LOOPS) Align all loops to 32 byte boundary. mbranch-cost=1 -Target Report RejectNegative Mask(BRANCH_COST) +Target RejectNegative Mask(BRANCH_COST) Prefer branches over conditional execution. mbranch-cost=2 -Target Report RejectNegative InverseMask(BRANCH_COST) +Target RejectNegative InverseMask(BRANCH_COST) Give branches their default cost. mdebug @@ -66,11 +66,11 @@ Target RejectNegative Joined UInteger Var(m32r_cache_flush_trap) Init(CACHE_FLUS Specify cache flush trap number. missue-rate=1 -Target Report RejectNegative Mask(LOW_ISSUE_RATE) +Target RejectNegative Mask(LOW_ISSUE_RATE) Only issue one instruction per cycle. missue-rate=2 -Target Report RejectNegative InverseMask(LOW_ISSUE_RATE) +Target RejectNegative InverseMask(LOW_ISSUE_RATE) Allow two instructions to be issued per cycle. mmodel= diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md index 7222986..9014364 100644 --- a/gcc/config/m32r/predicates.md +++ b/gcc/config/m32r/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas M32R. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32r/t-linux b/gcc/config/m32r/t-linux index 914e1cb..3384b8a 100644 --- a/gcc/config/m32r/t-linux +++ b/gcc/config/m32r/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m32r/t-m32r b/gcc/config/m32r/t-m32r index 5c3b07a..83f6f70 100644 --- a/gcc/config/m32r/t-m32r +++ b/gcc/config/m32r/t-m32r @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2020 Free Software Foundation, Inc. +# Copyright (C) 1997-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/cf.md b/gcc/config/m68k/cf.md index eb3ea09..845336d 100644 --- a/gcc/config/m68k/cf.md +++ b/gcc/config/m68k/cf.md @@ -1,5 +1,5 @@ ;; ColdFire V1, V2, V3 and V4/V4e DFA description. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery Inc., www.codesourcery.com ;; ;; This file is part of GCC. diff --git a/gcc/config/m68k/constraints.md b/gcc/config/m68k/constraints.md index 96ad9e9..3aae483 100644 --- a/gcc/config/m68k/constraints.md +++ b/gcc/config/m68k/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for m68k -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/m68k/genopt.sh b/gcc/config/m68k/genopt.sh index 7143cb1..e6e4696 100755 --- a/gcc/config/m68k/genopt.sh +++ b/gcc/config/m68k/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate m68k-tables.opt from the lists in *.def. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -23,7 +23,7 @@ cat <<EOF ; Generated automatically by genopt.sh from m68k-devices.def, ; m68k-isas.def and m68k-microarchs.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/ieee.opt b/gcc/config/m68k/ieee.opt index 41b322d..c46f6dc 100644 --- a/gcc/config/m68k/ieee.opt +++ b/gcc/config/m68k/ieee.opt @@ -1,6 +1,6 @@ ; Extra IEEE options for the Motorola 68000 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h index a01647c..ccf5d9f 100644 --- a/gcc/config/m68k/linux.h +++ b/gcc/config/m68k/linux.h @@ -1,6 +1,6 @@ /* Definitions for Motorola 68k running Linux-based GNU systems with ELF format. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68020-elf.h b/gcc/config/m68k/m68020-elf.h index 05b1072..d40c522 100644 --- a/gcc/config/m68k/m68020-elf.h +++ b/gcc/config/m68k/m68020-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. "naked" 68020, elf object files and debugging, version. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-devices.def b/gcc/config/m68k/m68k-devices.def index 2cb6139..7fc755b 100644 --- a/gcc/config/m68k/m68k-devices.def +++ b/gcc/config/m68k/m68k-devices.def @@ -1,5 +1,5 @@ /* m68k device names -*- C -*- - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Written by CodeSourcery This file is part of GCC. diff --git a/gcc/config/m68k/m68k-isas.def b/gcc/config/m68k/m68k-isas.def index 4437084..67aea2a 100644 --- a/gcc/config/m68k/m68k-isas.def +++ b/gcc/config/m68k/m68k-isas.def @@ -1,5 +1,5 @@ /* m68k ISA names. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-microarchs.def b/gcc/config/m68k/m68k-microarchs.def index 5fdfce1..b9bdd13 100644 --- a/gcc/config/m68k/m68k-microarchs.def +++ b/gcc/config/m68k/m68k-microarchs.def @@ -1,5 +1,5 @@ /* m68k microarchitecture names. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-modes.def b/gcc/config/m68k/m68k-modes.def index b4d7716..7ce317b 100644 --- a/gcc/config/m68k/m68k-modes.def +++ b/gcc/config/m68k/m68k-modes.def @@ -1,5 +1,5 @@ /* M68k extra machine modes. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-none.h b/gcc/config/m68k/m68k-none.h index 6d82364..6365308 100644 --- a/gcc/config/m68k/m68k-none.h +++ b/gcc/config/m68k/m68k-none.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. "naked" 68020. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-opts.h b/gcc/config/m68k/m68k-opts.h index 1550e63..d9d1b1f 100644 --- a/gcc/config/m68k/m68k-opts.h +++ b/gcc/config/m68k/m68k-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Motorola 680x0/ColdFire. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h index 1c502d7..1786166 100644 --- a/gcc/config/m68k/m68k-protos.h +++ b/gcc/config/m68k/m68k-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Sun 68000/68020 version. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-tables.opt b/gcc/config/m68k/m68k-tables.opt index a229da9..c15d303 100644 --- a/gcc/config/m68k/m68k-tables.opt +++ b/gcc/config/m68k/m68k-tables.opt @@ -2,7 +2,7 @@ ; Generated automatically by genopt.sh from m68k-devices.def, ; m68k-isas.def and m68k-microarchs.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 36a0e34..40bdcb0 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Motorola 68000 family. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 85e8f84..8dfa3a9 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 8e35357..59a456c 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler, Motorola 68000 Version -;; Copyright (C) 1987-2020 Free Software Foundation, Inc. +;; Copyright (C) 1987-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 3ff0545..f2a72ee 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -1,6 +1,6 @@ ; Options for the Motorola 68000 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -95,7 +95,7 @@ Target RejectNegative Mask(HARD_FLOAT) Generate code that uses 68881 floating-point instructions. malign-int -Target Report Mask(ALIGN_INT) +Target Mask(ALIGN_INT) Align variables on a 32-bit boundary. march= @@ -103,7 +103,7 @@ Target RejectNegative Joined Enum(m68k_isa) Var(m68k_arch_option) Specify the name of the target architecture. mbitfield -Target Report Mask(BITFIELD) +Target Mask(BITFIELD) Use the bit-field instructions. mc68000 @@ -127,7 +127,7 @@ Target RejectNegative Alias(mcpu=, 68332) Generate code for a cpu32. mdiv -Target Report Mask(CF_HWDIV) +Target Mask(CF_HWDIV) Use hardware division instructions on ColdFire. mfidoa @@ -139,11 +139,11 @@ Target RejectNegative Mask(HARD_FLOAT) Generate code which uses hardware floating point instructions. mid-shared-library -Target Report Mask(ID_SHARED_LIBRARY) +Target Mask(ID_SHARED_LIBRARY) Enable ID based shared library. mlong-jump-table-offsets -Target Report RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS) +Target RejectNegative Mask(LONG_JUMP_TABLE_OFFSETS) Use 32-bit offsets in jump tables rather than 16-bit offsets. mnobitfield @@ -159,15 +159,15 @@ Target RejectNegative InverseMask(SHORT) Consider type 'int' to be 32 bits wide. mpcrel -Target Report Mask(PCREL) +Target Mask(PCREL) Generate pc-relative code. mrtd -Target Report Mask(RTD) +Target Mask(RTD) Use different calling convention using 'rtd'. msep-data -Target Report Mask(SEP_DATA) +Target Mask(SEP_DATA) Enable separate data segment. mshared-library-id= @@ -175,7 +175,7 @@ Target RejectNegative Joined UInteger ID of shared library to build. mshort -Target Report Mask(SHORT) +Target Mask(SHORT) Consider type 'int' to be 16 bits wide. msoft-float @@ -183,7 +183,7 @@ Target RejectNegative InverseMask(HARD_FLOAT) Generate code with library calls for floating point. mstrict-align -Target Report Mask(STRICT_ALIGNMENT) +Target Mask(STRICT_ALIGNMENT) Do not use unaligned memory references. mtune= @@ -191,9 +191,9 @@ Target RejectNegative Joined Enum(uarch_type) Var(m68k_tune_option) Init(unk_arc Tune for the specified target CPU or architecture. mxgot -Target Report Mask(XGOT) +Target Mask(XGOT) Support more than 8192 GOT entries on ColdFire. mxtls -Target Report Mask(XTLS) +Target Mask(XTLS) Support TLS segment larger than 64K. diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h index f10dd32..b832064 100644 --- a/gcc/config/m68k/m68kelf.h +++ b/gcc/config/m68k/m68kelf.h @@ -1,7 +1,7 @@ /* m68kelf support, derived from m68kv4.h */ /* Target definitions for GNU compiler for mc680x0 running System V.4 - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@netcom.com) and Fred Fish (fnf@cygnus.com). diff --git a/gcc/config/m68k/m68kemb.h b/gcc/config/m68k/m68kemb.h index f2c3a35..a429575 100644 --- a/gcc/config/m68k/m68kemb.h +++ b/gcc/config/m68k/m68kemb.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. "embedded" 68XXX. This is meant to be included after m68k.h. - Copyright (C) 1994-2020 Free Software Foundation, Inc. */ + Copyright (C) 1994-2021 Free Software Foundation, Inc. */ /* Override the SVR4 ABI for this target. */ diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h index 616b3d4..5a2f8ff 100644 --- a/gcc/config/m68k/netbsd-elf.h +++ b/gcc/config/m68k/netbsd-elf.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GNU compiler, for m68k (including m68010) NetBSD platforms using the ELF object format. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems. Inc. This file is derived from <m68k/m68kv4.h>, <m68k/m68kelf.h>, diff --git a/gcc/config/m68k/openbsd.h b/gcc/config/m68k/openbsd.h index ffd6e8b..8fd10e1 100644 --- a/gcc/config/m68k/openbsd.h +++ b/gcc/config/m68k/openbsd.h @@ -1,5 +1,5 @@ /* Configuration file for an m68k OpenBSD target. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md index 812dfb3..23665df 100644 --- a/gcc/config/m68k/predicates.md +++ b/gcc/config/m68k/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Motorola 68000. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m68k/print-sysroot-suffix.sh b/gcc/config/m68k/print-sysroot-suffix.sh index 97d7aa6..1c5eab2 100644 --- a/gcc/config/m68k/print-sysroot-suffix.sh +++ b/gcc/config/m68k/print-sysroot-suffix.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (C) 2006-2020 Free Software Foundation, Inc. +# Copyright (C) 2006-2021 Free Software Foundation, Inc. # This file is part of GCC. # GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/m68k/rtemself.h b/gcc/config/m68k/rtemself.h index 26d614d..690da86 100644 --- a/gcc/config/m68k/rtemself.h +++ b/gcc/config/m68k/rtemself.h @@ -1,6 +1,6 @@ /* Definitions for rtems targeting a Motorola m68k using elf. Copyright (C) 1999, 2000, 2002 National Research Council of Canada. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. Contributed by Charles-Antoine Gauthier (charles.gauthier@nrc.ca). This file is part of GCC. diff --git a/gcc/config/m68k/sync.md b/gcc/config/m68k/sync.md index 517cf58..d5bc012 100644 --- a/gcc/config/m68k/sync.md +++ b/gcc/config/m68k/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for m68k synchronization instructions. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m68k/t-linux b/gcc/config/m68k/t-linux index 9d90b87..49f43d0 100644 --- a/gcc/config/m68k/t-linux +++ b/gcc/config/m68k/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2020 Free Software Foundation, Inc. +# Copyright (C) 2008-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/t-mlibs b/gcc/config/m68k/t-mlibs index 1c93517..158b976 100644 --- a/gcc/config/m68k/t-mlibs +++ b/gcc/config/m68k/t-mlibs @@ -1,6 +1,6 @@ # multilibs -*- mode:Makefile -*- # -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/t-uclinux b/gcc/config/m68k/t-uclinux index 665134a..3c0ccff 100644 --- a/gcc/config/m68k/t-uclinux +++ b/gcc/config/m68k/t-uclinux @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/uclinux.h b/gcc/config/m68k/uclinux.h index 52f92c5..8a670d5 100644 --- a/gcc/config/m68k/uclinux.h +++ b/gcc/config/m68k/uclinux.h @@ -2,7 +2,7 @@ using ELF objects with special linker post-processing to produce FLAT executables. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/uclinux.opt b/gcc/config/m68k/uclinux.opt index 34842f0..35dd17d 100644 --- a/gcc/config/m68k/uclinux.opt +++ b/gcc/config/m68k/uclinux.opt @@ -1,6 +1,6 @@ ; m68k/ColdFire uClinux options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mcore/constraints.md b/gcc/config/mcore/constraints.md index f1b67b5f..76ce6c3 100644 --- a/gcc/config/mcore/constraints.md +++ b/gcc/config/mcore/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the Motorola MCore -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mcore/mcore-elf.h b/gcc/config/mcore/mcore-elf.h index 3643120..d50f578 100644 --- a/gcc/config/mcore/mcore-elf.h +++ b/gcc/config/mcore/mcore-elf.h @@ -1,5 +1,5 @@ /* Definitions of MCore target. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/mcore/mcore-protos.h b/gcc/config/mcore/mcore-protos.h index 3c1895f..b1c0a91 100644 --- a/gcc/config/mcore/mcore-protos.h +++ b/gcc/config/mcore/mcore-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in mcore.c - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Nick Clifton (nickc@redhat.com) This file is part of GCC. diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index 9b68504..5f895b4 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -1,5 +1,5 @@ /* Output routines for Motorola MCore processor - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index ff746c1..68cf6dc 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Motorola M*CORE Processor. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md index 2be99e4..35d207e 100644 --- a/gcc/config/mcore/mcore.md +++ b/gcc/config/mcore/mcore.md @@ -1,5 +1,5 @@ ;; Machine description the Motorola MCore -;; Copyright (C) 1993-2020 Free Software Foundation, Inc. +;; Copyright (C) 1993-2021 Free Software Foundation, Inc. ;; Contributed by Motorola. ;; This file is part of GCC. diff --git a/gcc/config/mcore/mcore.opt b/gcc/config/mcore/mcore.opt index dc25e2b..de24439 100644 --- a/gcc/config/mcore/mcore.opt +++ b/gcc/config/mcore/mcore.opt @@ -1,6 +1,6 @@ ; Options for the Motorola MCore port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,35 +19,35 @@ ; <http://www.gnu.org/licenses/>. m210 -Target RejectNegative Report InverseMask(M340) +Target RejectNegative InverseMask(M340) Generate code for the M*Core M210. m340 -Target RejectNegative Report Mask(M340) +Target RejectNegative Mask(M340) Generate code for the M*Core M340. m4byte-functions -Target Report Mask(OVERALIGN_FUNC) +Target Mask(OVERALIGN_FUNC) Force functions to be aligned to a 4 byte boundary. mbig-endian -Target RejectNegative Report InverseMask(LITTLE_END) +Target RejectNegative InverseMask(LITTLE_END) Generate big-endian code. mcallgraph-data -Target Report Mask(CG_DATA) +Target Mask(CG_DATA) Emit call graph information. mdiv -Target Report Mask(DIV) +Target Mask(DIV) Use the divide instruction. mhardlit -Target Report Mask(HARDLIT) +Target Mask(HARDLIT) Inline constants if it can be done in 2 insns or less. mlittle-endian -Target RejectNegative Report Mask(LITTLE_END) +Target RejectNegative Mask(LITTLE_END) Generate little-endian code. ; Not used by the compiler proper. @@ -56,11 +56,11 @@ Target RejectNegative Assume that run-time support has been provided, so omit -lsim from the linker command line. mrelax-immediates -Target Report Mask(RELAX_IMM) +Target Mask(RELAX_IMM) Use arbitrary sized immediates in bit operations. mslow-bytes -Target Report Mask(SLOW_BYTES) +Target Mask(SLOW_BYTES) Prefer word accesses over byte accesses. ; Maximum size we are allowed to grow the stack in a single operation. @@ -71,5 +71,5 @@ Target RejectNegative Joined UInteger Var(mcore_stack_increment) Init(STACK_UNIT Set the maximum amount for a single stack increment operation. mwide-bitfields -Target Report Mask(W_FIELD) +Target Mask(W_FIELD) Always treat bitfields as int-sized. diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md index 2fa64d0..0f9722d 100644 --- a/gcc/config/mcore/predicates.md +++ b/gcc/config/mcore/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Motorola MCore. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mcore/t-mcore b/gcc/config/mcore/t-mcore index 638a2e0..070e637 100644 --- a/gcc/config/mcore/t-mcore +++ b/gcc/config/mcore/t-mcore @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2020 Free Software Foundation, Inc. +# Copyright (C) 2000-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md index b9fc6e3..b4d7ee3 100644 --- a/gcc/config/microblaze/constraints.md +++ b/gcc/config/microblaze/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Xilinx MicroBlaze processors. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h index 7eded69..a5cc480 100644 --- a/gcc/config/microblaze/linux.h +++ b/gcc/config/microblaze/linux.h @@ -1,5 +1,5 @@ /* Definitions for MicroBlaze running Linux. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c index d8c88e5..e0b29bc 100644 --- a/gcc/config/microblaze/microblaze-c.c +++ b/gcc/config/microblaze/microblaze-c.c @@ -1,5 +1,5 @@ /* Subroutines used for the C front end for Xilinx MicroBlaze. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h index 982b2ab..54c2696 100644 --- a/gcc/config/microblaze/microblaze-protos.h +++ b/gcc/config/microblaze/microblaze-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Xilinx MicroBlaze. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index a0f81b7..b444db1 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Xilinx MicroBlaze. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h index dc112f5..2ecec75 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 7049acd..472ef4c 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1,5 +1,5 @@ ;; microblaze.md -- Machine description for Xilinx MicroBlaze processors. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt index 725c2fa..8dfb134 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -1,6 +1,6 @@ ; Options for the MicroBlaze port of the compiler ; -; Copyright (C) 2009-2020 Free Software Foundation, Inc. +; Copyright (C) 2009-2021 Free Software Foundation, Inc. ; ; Contributed by Michael Eager <eager@eagercon.com>. ; @@ -36,11 +36,11 @@ Zxl-mode-xmdstub Driver msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target RejectNegative Mask(SOFT_FLOAT) Use software emulation for floating point (default). mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Use hardware floating point instructions. msmall-divides @@ -56,11 +56,11 @@ Target Mask(MEMCPY) Don't optimize block moves, use memcpy. mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target RejectNegative InverseMask(LITTLE_ENDIAN) Assume target CPU is configured as big endian. mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target RejectNegative Mask(LITTLE_ENDIAN) Assume target CPU is configured as little endian. mxl-soft-mul diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md index 35a121c..a327c3b 100644 --- a/gcc/config/microblaze/predicates.md +++ b/gcc/config/microblaze/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Xilinx MicroBlaze -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; Contributed by Michael Eager <eager@eagercon.com>. ;; diff --git a/gcc/config/microblaze/rtems.h b/gcc/config/microblaze/rtems.h index 1a9db25..a6c1d49 100644 --- a/gcc/config/microblaze/rtems.h +++ b/gcc/config/microblaze/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a microblaze using ELF. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md index 76f530b..23e0f1c 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -1,5 +1,5 @@ ;; Machine description for Xilinx MicroBlaze synchronization instructions. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/10000.md b/gcc/config/mips/10000.md index b8504d7..4f7d2b5 100644 --- a/gcc/config/mips/10000.md +++ b/gcc/config/mips/10000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the VR1x000. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/20kc.md b/gcc/config/mips/20kc.md index 3181369..327dee4 100644 --- a/gcc/config/mips/20kc.md +++ b/gcc/config/mips/20kc.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md index 4eb88ab..3a8a447 100644 --- a/gcc/config/mips/24k.md +++ b/gcc/config/mips/24k.md @@ -8,7 +8,7 @@ ;; References: ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." ;; -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md index 5638310..d5bab00 100644 --- a/gcc/config/mips/3000.md +++ b/gcc/config/mips/3000.md @@ -1,5 +1,5 @@ ;; R3000 and TX39 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4000.md b/gcc/config/mips/4000.md index 91ae2c1..675efc4 100644 --- a/gcc/config/mips/4000.md +++ b/gcc/config/mips/4000.md @@ -1,5 +1,5 @@ ;; R4000 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4100.md b/gcc/config/mips/4100.md index 0881fc4..a21fda9 100644 --- a/gcc/config/mips/4100.md +++ b/gcc/config/mips/4100.md @@ -1,5 +1,5 @@ ;; VR4100 and VR4120 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4130.md b/gcc/config/mips/4130.md index bf0832c..16d6670 100644 --- a/gcc/config/mips/4130.md +++ b/gcc/config/mips/4130.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/4300.md b/gcc/config/mips/4300.md index fcabc96..022866a 100644 --- a/gcc/config/mips/4300.md +++ b/gcc/config/mips/4300.md @@ -1,5 +1,5 @@ ;; VR4300 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4600.md b/gcc/config/mips/4600.md index fe986af..3b55d11 100644 --- a/gcc/config/mips/4600.md +++ b/gcc/config/mips/4600.md @@ -1,5 +1,5 @@ ;; R4600, R4650, and R4700 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4k.md b/gcc/config/mips/4k.md index 8bfc49b..839e39f 100644 --- a/gcc/config/mips/4k.md +++ b/gcc/config/mips/4k.md @@ -10,7 +10,7 @@ ;; 4km - pipelined multiplier and block address translator (BAT) ;; 4kp - non-pipelined multiplier and block address translator (BAT) ;; -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5000.md b/gcc/config/mips/5000.md index e583709..bb4120c 100644 --- a/gcc/config/mips/5000.md +++ b/gcc/config/mips/5000.md @@ -1,5 +1,5 @@ ;; VR5000 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/5400.md b/gcc/config/mips/5400.md index ee0e628..b334985 100644 --- a/gcc/config/mips/5400.md +++ b/gcc/config/mips/5400.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5500.md b/gcc/config/mips/5500.md index f615123..f3be5a6 100644 --- a/gcc/config/mips/5500.md +++ b/gcc/config/mips/5500.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5k.md b/gcc/config/mips/5k.md index 75ad1a1..ba79fda 100644 --- a/gcc/config/mips/5k.md +++ b/gcc/config/mips/5k.md @@ -10,7 +10,7 @@ ;; 5kf - Separate floating point pipe which can dual-issue with the ;; integer pipe. ;; -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/6000.md b/gcc/config/mips/6000.md index 1701e50..000a8ef 100644 --- a/gcc/config/mips/6000.md +++ b/gcc/config/mips/6000.md @@ -1,5 +1,5 @@ ;; R6000 pipeline description. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/7000.md b/gcc/config/mips/7000.md index cb67564..3b2b467 100644 --- a/gcc/config/mips/7000.md +++ b/gcc/config/mips/7000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the RM7000. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/74k.md b/gcc/config/mips/74k.md index 2c199fc..9a864ae 100644 --- a/gcc/config/mips/74k.md +++ b/gcc/config/mips/74k.md @@ -5,7 +5,7 @@ ;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006" ;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006" ;; -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/9000.md b/gcc/config/mips/9000.md index 4d0bd21..f9ddf60 100644 --- a/gcc/config/mips/9000.md +++ b/gcc/config/mips/9000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the RM9000. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 7c700a4..9f4b147 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for MIPS. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/driver-native.c b/gcc/config/mips/driver-native.c index 5fadddc..eaf5f7e 100644 --- a/gcc/config/mips/driver-native.c +++ b/gcc/config/mips/driver-native.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h index 0dbc635..9855452 100644 --- a/gcc/config/mips/elf.h +++ b/gcc/config/mips/elf.h @@ -1,5 +1,5 @@ /* Target macros for mips*-elf targets. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elfoabi.h b/gcc/config/mips/elfoabi.h index 6f7eb0e..2ff4d68 100644 --- a/gcc/config/mips/elfoabi.h +++ b/gcc/config/mips/elfoabi.h @@ -1,6 +1,6 @@ /* Target macros for mips*-elf targets that selected between o32 and o64 based on the target architecture. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elforion.h b/gcc/config/mips/elforion.h index 609f8ea..94217e5 100644 --- a/gcc/config/mips/elforion.h +++ b/gcc/config/mips/elforion.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. MIPS ORION version. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/frame-header-opt.c b/gcc/config/mips/frame-header-opt.c index d89260d..06fd689 100644 --- a/gcc/config/mips/frame-header-opt.c +++ b/gcc/config/mips/frame-header-opt.c @@ -4,7 +4,7 @@ targets, if a frame header is required, it is allocated by the callee. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/generic.md b/gcc/config/mips/generic.md index bbc11af..de9fdc2 100644 --- a/gcc/config/mips/generic.md +++ b/gcc/config/mips/generic.md @@ -1,5 +1,5 @@ ;; Generic DFA-based pipeline description for MIPS targets -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/genopt.sh b/gcc/config/mips/genopt.sh index 927ec80..19228ff 100755 --- a/gcc/config/mips/genopt.sh +++ b/gcc/config/mips/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate mips-tables.opt from the list of CPUs in mips-cpus.def. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from mips-cpus.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/gnu-user.h b/gcc/config/mips/gnu-user.h index 5d07821..a390bce 100644 --- a/gcc/config/mips/gnu-user.h +++ b/gcc/config/mips/gnu-user.h @@ -1,5 +1,5 @@ /* Definitions for MIPS systems using GNU userspace. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/gs264e.md b/gcc/config/mips/gs264e.md index 0b0c447..cfcbcf2 100644 --- a/gcc/config/mips/gs264e.md +++ b/gcc/config/mips/gs264e.md @@ -1,6 +1,6 @@ ;; Pipeline model for Loongson gs264e cores. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md index c936c74..7c5d4bb 100644 --- a/gcc/config/mips/gs464.md +++ b/gcc/config/mips/gs464.md @@ -1,6 +1,6 @@ ;; Pipeline model for Loongson gs464 cores. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/gs464e.md b/gcc/config/mips/gs464e.md index 872842f..7f55033 100644 --- a/gcc/config/mips/gs464e.md +++ b/gcc/config/mips/gs464e.md @@ -1,6 +1,6 @@ ;; Pipeline model for Loongson gs464e cores. -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md index 5db9f70..c2d63a2 100644 --- a/gcc/config/mips/i6400.md +++ b/gcc/config/mips/i6400.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for I6400. ;; -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/linux-common.h b/gcc/config/mips/linux-common.h index 9c77e36..00beda3 100644 --- a/gcc/config/mips/linux-common.h +++ b/gcc/config/mips/linux-common.h @@ -1,5 +1,5 @@ /* Definitions for MIPS running Linux-based GNU systems with ELF format. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h index 54446e5..44a85e4 100644 --- a/gcc/config/mips/linux.h +++ b/gcc/config/mips/linux.h @@ -1,5 +1,5 @@ /* Definitions for MIPS running Linux-based GNU systems with ELF format. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/loongson-mmi.md b/gcc/config/mips/loongson-mmi.md index 551341d..e6f19b4 100644 --- a/gcc/config/mips/loongson-mmi.md +++ b/gcc/config/mips/loongson-mmi.md @@ -1,5 +1,5 @@ ;; Machine description for Loongson MultiMedia extensions Instructions (MMI). -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/loongson-mmiintrin.h b/gcc/config/mips/loongson-mmiintrin.h index 58065b7..b9f9642 100644 --- a/gcc/config/mips/loongson-mmiintrin.h +++ b/gcc/config/mips/loongson-mmiintrin.h @@ -1,6 +1,6 @@ /* Intrinsics for Loongson MultiMedia extension Instructions operations. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/mips/loongson.h b/gcc/config/mips/loongson.h index 86ac407..e05ed8c 100644 --- a/gcc/config/mips/loongson.h +++ b/gcc/config/mips/loongson.h @@ -1,6 +1,6 @@ /* Intrinsics for Loongson MultiMedia extension Instructions operations. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/mips/loongson2ef.md b/gcc/config/mips/loongson2ef.md index 932b1cf..26e790f 100644 --- a/gcc/config/mips/loongson2ef.md +++ b/gcc/config/mips/loongson2ef.md @@ -1,6 +1,6 @@ ;; Pipeline model for ST Microelectronics Loongson-2E/2F cores. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md index 3e1c2e7..5f9f376 100644 --- a/gcc/config/mips/m5100.md +++ b/gcc/config/mips/m5100.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for MIPS32 models M5100. ;; -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/micromips.md b/gcc/config/mips/micromips.md index 8560322..925c3c9 100644 --- a/gcc/config/mips/micromips.md +++ b/gcc/config/mips/micromips.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; micromips.md Machine Description for the microMIPS instruction set ;; This file is part of GCC. diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index f308f99..b02294b 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -1,5 +1,5 @@ /* MIPS CPU names. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-d.c b/gcc/config/mips/mips-d.c index a9d4ba1..dad101c 100644 --- a/gcc/config/mips/mips-d.c +++ b/gcc/config/mips/mips-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the MIPS architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md index 845940e..5a5694f 100644 --- a/gcc/config/mips/mips-dsp.md +++ b/gcc/config/mips/mips-dsp.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index 9e84240..95ba712 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-fixed.md b/gcc/config/mips/mips-fixed.md index 39d02d3..3de02da 100644 --- a/gcc/config/mips/mips-fixed.md +++ b/gcc/config/mips/mips-fixed.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def index ece9a95..74f21f1 100644 --- a/gcc/config/mips/mips-ftypes.def +++ b/gcc/config/mips/mips-ftypes.def @@ -1,5 +1,5 @@ /* Definitions of prototypes for MIPS built-in functions. -*- C -*- - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-modes.def b/gcc/config/mips/mips-modes.def index ce0ac1c..5ab0324 100644 --- a/gcc/config/mips/mips-modes.def +++ b/gcc/config/mips/mips-modes.def @@ -1,5 +1,5 @@ /* MIPS extra machine modes. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 7a195dd..3ecf2bd 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -1,7 +1,7 @@ ;; Machine Description for MIPS MSA ASE ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014 ;; -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-opts.h b/gcc/config/mips/mips-opts.h index 23f8638..6214849 100644 --- a/gcc/config/mips/mips-opts.h +++ b/gcc/config/mips/mips-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for MIPS. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index f619d17..72bbbe2 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for GNU compiler. MIPS version. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md index 969777f..7b00236 100644 --- a/gcc/config/mips/mips-ps-3d.md +++ b/gcc/config/mips/mips-ps-3d.md @@ -1,5 +1,5 @@ ;; MIPS Paired-Single Floating and MIPS-3D Instructions. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 10e05ba..aef12f0 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from mips-cpus.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 58e474e..ebb04b7 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1,5 +1,5 @@ /* Subroutines used for MIPS code generation. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by A. Lichnewsky, lich@inria.inria.fr. Changes by Michael Meissner, meissner@osf.org. 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and @@ -21624,6 +21624,15 @@ mips_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, bool ok; d.target = target; + if (op0) + { + rtx nop0 = force_reg (vmode, op0); + if (op0 == op1) + op1 = nop0; + op0 = nop0; + } + if (op1) + op1 = force_reg (vmode, op1); d.op0 = op0; d.op1 = op1; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 3ce0c19..b4a60a5 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. MIPS version. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2e75a72..eef3cfd 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1,5 +1,5 @@ ;; Mips.md Machine Description for MIPS based processors -;; Copyright (C) 1989-2020 Free Software Foundation, Inc. +;; Copyright (C) 1989-2021 Free Software Foundation, Inc. ;; Contributed by A. Lichnewsky, lich@inria.inria.fr ;; Changes by Michael Meissner, meissner@osf.org ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 1f19296..6af8037 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -1,6 +1,6 @@ ; Options for the MIPS port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -51,15 +51,15 @@ EnumValue Enum(mips_abi) String(eabi) Value(ABI_EABI) mabicalls -Target Report Mask(ABICALLS) +Target Mask(ABICALLS) Generate code that can be used in SVR4-style dynamic objects. mmad -Target Report Var(TARGET_MAD) +Target Var(TARGET_MAD) Use PMC-style 'mad' instructions. mimadd -Target Report Mask(IMADD) +Target Mask(IMADD) Use integer madd/msub instructions. march= @@ -71,15 +71,15 @@ Target RejectNegative Joined UInteger Var(mips_branch_cost) -mbranch-cost=COST Set the cost of branches to roughly COST instructions. mbranch-likely -Target Report Mask(BRANCHLIKELY) +Target Mask(BRANCHLIKELY) Use Branch Likely instructions, overriding the architecture default. mflip-mips16 -Target Report Var(TARGET_FLIP_MIPS16) +Target Var(TARGET_FLIP_MIPS16) Switch on/off MIPS16 ASE on alternating functions for compiler testing. mcheck-zero-division -Target Report Mask(CHECK_ZERO_DIV) +Target Mask(CHECK_ZERO_DIV) Trap on integer divide by zero. mcode-readable= @@ -100,27 +100,27 @@ EnumValue Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO) mdivide-breaks -Target Report RejectNegative Mask(DIVIDE_BREAKS) +Target RejectNegative Mask(DIVIDE_BREAKS) Use branch-and-break sequences to check for integer divide by zero. mdivide-traps -Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS) +Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS) Use trap instructions to check for integer divide by zero. mdmx -Target Report RejectNegative Var(TARGET_MDMX) +Target RejectNegative Var(TARGET_MDMX) Allow the use of MDMX instructions. mdouble-float -Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) +Target RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations. mdsp -Target Report Var(TARGET_DSP) +Target Var(TARGET_DSP) Use MIPS-DSP instructions. mdspr2 -Target Report Var(TARGET_DSPR2) +Target Var(TARGET_DSPR2) Use MIPS-DSP REV 2 instructions. mdebug @@ -130,83 +130,83 @@ mdebugd Target Var(TARGET_DEBUG_D_MODE) Undocumented meb -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Use big-endian byte order. mel -Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) Use little-endian byte order. membedded-data -Target Report Var(TARGET_EMBEDDED_DATA) +Target Var(TARGET_EMBEDDED_DATA) Use ROM instead of RAM. meva -Target Report Var(TARGET_EVA) +Target Var(TARGET_EVA) Use Enhanced Virtual Addressing instructions. mexplicit-relocs -Target Report Mask(EXPLICIT_RELOCS) +Target Mask(EXPLICIT_RELOCS) Use NewABI-style %reloc() assembly operators. mextern-sdata -Target Report Var(TARGET_EXTERN_SDATA) Init(1) +Target Var(TARGET_EXTERN_SDATA) Init(1) Use -G for data that is not defined by the current object. mfix-24k -Target Report Var(TARGET_FIX_24K) +Target Var(TARGET_FIX_24K) Work around certain 24K errata. mfix-r4000 -Target Report Mask(FIX_R4000) +Target Mask(FIX_R4000) Work around certain R4000 errata. mfix-r4400 -Target Report Mask(FIX_R4400) +Target Mask(FIX_R4400) Work around certain R4400 errata. mfix-r5900 -Target Report Mask(FIX_R5900) +Target Mask(FIX_R5900) Work around the R5900 short loop erratum. mfix-rm7000 -Target Report Var(TARGET_FIX_RM7000) +Target Var(TARGET_FIX_RM7000) Work around certain RM7000 errata. mfix-r10000 -Target Report Mask(FIX_R10000) +Target Mask(FIX_R10000) Work around certain R10000 errata. mfix-sb1 -Target Report Var(TARGET_FIX_SB1) +Target Var(TARGET_FIX_SB1) Work around errata for early SB-1 revision 2 cores. mfix-vr4120 -Target Report Var(TARGET_FIX_VR4120) +Target Var(TARGET_FIX_VR4120) Work around certain VR4120 errata. mfix-vr4130 -Target Report Var(TARGET_FIX_VR4130) +Target Var(TARGET_FIX_VR4130) Work around VR4130 mflo/mfhi errata. mfix4300 -Target Report Var(TARGET_4300_MUL_FIX) +Target Var(TARGET_4300_MUL_FIX) Work around an early 4300 hardware bug. mfp-exceptions -Target Report Var(TARGET_FP_EXCEPTIONS) Init(1) +Target Var(TARGET_FP_EXCEPTIONS) Init(1) FP exceptions are enabled. mfp32 -Target Report RejectNegative InverseMask(FLOAT64) +Target RejectNegative InverseMask(FLOAT64) Use 32-bit floating-point registers. mfpxx -Target Report RejectNegative Mask(FLOATXX) +Target RejectNegative Mask(FLOATXX) Conform to the o32 FPXX ABI. mfp64 -Target Report RejectNegative Mask(FLOAT64) +Target RejectNegative Mask(FLOAT64) Use 64-bit floating-point registers. mflush-func= @@ -232,31 +232,31 @@ EnumValue Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY) mgp32 -Target Report RejectNegative InverseMask(64BIT) +Target RejectNegative InverseMask(64BIT) Use 32-bit general registers. mgp64 -Target Report RejectNegative Mask(64BIT) +Target RejectNegative Mask(64BIT) Use 64-bit general registers. mgpopt -Target Report Var(TARGET_GPOPT) Init(1) +Target Var(TARGET_GPOPT) Init(1) Use GP-relative addressing to access small data. mplt -Target Report Var(TARGET_PLT) +Target Var(TARGET_PLT) When generating -mabicalls code, allow executables to use PLTs and copy relocations. mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) +Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) Allow the use of hardware floating-point ABI and instructions. minterlink-compressed -Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0) +Target Var(TARGET_INTERLINK_COMPRESSED) Init(0) Generate code that is link-compatible with MIPS16 and microMIPS code. minterlink-mips16 -Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0) +Target Var(TARGET_INTERLINK_COMPRESSED) Init(0) An alias for minterlink-compressed provided for backward-compatibility. mips @@ -264,59 +264,59 @@ Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_opti -mipsN Generate code for ISA level N. mips16 -Target Report RejectNegative Mask(MIPS16) +Target RejectNegative Mask(MIPS16) Generate MIPS16 code. mips3d -Target Report RejectNegative Var(TARGET_MIPS3D) +Target RejectNegative Var(TARGET_MIPS3D) Use MIPS-3D instructions. mllsc -Target Report Mask(LLSC) +Target Mask(LLSC) Use ll, sc and sync instructions. mlocal-sdata -Target Report Var(TARGET_LOCAL_SDATA) Init(1) +Target Var(TARGET_LOCAL_SDATA) Init(1) Use -G for object-local data. mlong-calls -Target Report Var(TARGET_LONG_CALLS) +Target Var(TARGET_LONG_CALLS) Use indirect calls. mlong32 -Target Report RejectNegative InverseMask(LONG64, LONG32) +Target RejectNegative InverseMask(LONG64, LONG32) Use a 32-bit long type. mlong64 -Target Report RejectNegative Mask(LONG64) +Target RejectNegative Mask(LONG64) Use a 64-bit long type. mmcount-ra-address -Target Report Var(TARGET_MCOUNT_RA_ADDRESS) +Target Var(TARGET_MCOUNT_RA_ADDRESS) Pass the address of the ra save location to _mcount in $12. mmemcpy -Target Report Mask(MEMCPY) +Target Mask(MEMCPY) Don't optimize block moves. mmicromips -Target Report Mask(MICROMIPS) +Target Mask(MICROMIPS) Use microMIPS instructions. mmsa -Target Report Mask(MSA) +Target Mask(MSA) Use MIPS MSA Extension instructions. mmt -Target Report Var(TARGET_MT) +Target Var(TARGET_MT) Allow the use of MT instructions. mno-float -Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT) +Target RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT) Prevent the use of all floating-point operations. mmcu -Target Report Var(TARGET_MCU) +Target Var(TARGET_MCU) Use MCU instructions. mno-flush-func @@ -324,19 +324,19 @@ Target RejectNegative Do not use a cache-flushing function before calling stack trampolines. mno-mdmx -Target Report RejectNegative Var(TARGET_MDMX, 0) +Target RejectNegative Var(TARGET_MDMX, 0) Do not use MDMX instructions. mno-mips16 -Target Report RejectNegative InverseMask(MIPS16) +Target RejectNegative InverseMask(MIPS16) Generate normal-mode code. mno-mips3d -Target Report RejectNegative Var(TARGET_MIPS3D, 0) +Target RejectNegative Var(TARGET_MIPS3D, 0) Do not use MIPS-3D instructions. mpaired-single -Target Report Mask(PAIRED_SINGLE_FLOAT) +Target Mask(PAIRED_SINGLE_FLOAT) Use paired-single floating-point instructions. mr10k-cache-barrier= @@ -357,47 +357,47 @@ EnumValue Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE) mrelax-pic-calls -Target Report Mask(RELAX_PIC_CALLS) +Target Mask(RELAX_PIC_CALLS) Try to allow the linker to turn PIC calls into direct calls. mshared -Target Report Var(TARGET_SHARED) Init(1) +Target Var(TARGET_SHARED) Init(1) When generating -mabicalls code, make the code suitable for use in shared libraries. msingle-float -Target Report RejectNegative Mask(SINGLE_FLOAT) +Target RejectNegative Mask(SINGLE_FLOAT) Restrict the use of hardware floating-point instructions to 32-bit operations. msmartmips -Target Report Mask(SMARTMIPS) +Target Mask(SMARTMIPS) Use SmartMIPS instructions. msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT_ABI) +Target RejectNegative Mask(SOFT_FLOAT_ABI) Prevent the use of all hardware floating-point instructions. msplit-addresses -Target Report Mask(SPLIT_ADDRESSES) +Target Mask(SPLIT_ADDRESSES) Optimize lui/addiu address loads. msym32 -Target Report Var(TARGET_SYM32) +Target Var(TARGET_SYM32) Assume all symbols have 32-bit values. msynci -Target Report Mask(SYNCI) +Target Mask(SYNCI) Use synci instruction to invalidate i-cache. mlra -Target Report Var(mips_lra_flag) Init(1) Save +Target Var(mips_lra_flag) Init(1) Save Use LRA instead of reload. mlxc1-sxc1 -Target Report Var(mips_lxc1_sxc1) Init(1) +Target Var(mips_lxc1_sxc1) Init(1) Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable. mmadd4 -Target Report Var(mips_madd4) Init(1) +Target Var(mips_madd4) Init(1) Use 4-operand madd.s/madd.d and related instructions where applicable. mtune= @@ -405,50 +405,50 @@ Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_va -mtune=PROCESSOR Optimize the output for PROCESSOR. muninit-const-in-rodata -Target Report Var(TARGET_UNINIT_CONST_IN_RODATA) +Target Var(TARGET_UNINIT_CONST_IN_RODATA) Put uninitialized constants in ROM (needs -membedded-data). mvirt -Target Report Var(TARGET_VIRT) +Target Var(TARGET_VIRT) Use Virtualization (VZ) instructions. mxpa -Target Report Var(TARGET_XPA) +Target Var(TARGET_XPA) Use eXtended Physical Address (XPA) instructions. mcrc -Target Report Var(TARGET_CRC) +Target Var(TARGET_CRC) Use Cyclic Redundancy Check (CRC) instructions. mginv -Target Report Var(TARGET_GINV) +Target Var(TARGET_GINV) Use Global INValidate (GINV) instructions. mvr4130-align -Target Report Mask(VR4130_ALIGN) +Target Mask(VR4130_ALIGN) Perform VR4130-specific alignment optimizations. mxgot -Target Report Var(TARGET_XGOT) +Target Var(TARGET_XGOT) Lift restrictions on GOT size. modd-spreg -Target Report Mask(ODD_SPREG) +Target Mask(ODD_SPREG) Enable use of odd-numbered single-precision registers. mframe-header-opt -Target Report Var(flag_frame_header_optimization) Optimization +Target Var(flag_frame_header_optimization) Optimization Optimize frame header. noasmopt Driver mload-store-pairs -Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1) +Target Var(TARGET_LOAD_STORE_PAIRS) Init(1) Enable load/store bonding. mcompact-branches= -Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL) +Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL) Specify the compact branch usage policy. Enum @@ -465,13 +465,13 @@ EnumValue Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS) mloongson-mmi -Target Report Mask(LOONGSON_MMI) +Target Mask(LOONGSON_MMI) Use Loongson MultiMedia extensions Instructions (MMI) instructions. mloongson-ext -Target Report Mask(LOONGSON_EXT) +Target Mask(LOONGSON_EXT) Use Loongson EXTension (EXT) instructions. mloongson-ext2 -Target Report Var(TARGET_LOONGSON_EXT2) +Target Var(TARGET_LOONGSON_EXT2) Use Loongson EXTension R2 (EXT2) instructions. diff --git a/gcc/config/mips/msa.h b/gcc/config/mips/msa.h index 4f10699..4b65c77 100644 --- a/gcc/config/mips/msa.h +++ b/gcc/config/mips/msa.h @@ -1,6 +1,6 @@ /* MIPS MSA intrinsics include file. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Imagination Technologies Ltd. This file is part of GCC. diff --git a/gcc/config/mips/mti-elf.h b/gcc/config/mips/mti-elf.h index 227a90d..970beae 100644 --- a/gcc/config/mips/mti-elf.h +++ b/gcc/config/mips/mti-elf.h @@ -1,5 +1,5 @@ /* Target macros for mips*-mti-elf targets. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mti-linux.h b/gcc/config/mips/mti-linux.h index 94f7fc5..fed8250 100644 --- a/gcc/config/mips/mti-linux.h +++ b/gcc/config/mips/mti-linux.h @@ -1,5 +1,5 @@ /* Target macros for mips*-mti-linux* targets. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/n32-elf.h b/gcc/config/mips/n32-elf.h index 44a114d..f842711 100644 --- a/gcc/config/mips/n32-elf.h +++ b/gcc/config/mips/n32-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. n32 for embedded systems. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h index 9c93d29..5844f00 100644 --- a/gcc/config/mips/netbsd.h +++ b/gcc/config/mips/netbsd.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MIPS NetBSD systems. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/octeon.md b/gcc/config/mips/octeon.md index 1183029..887ecaa 100644 --- a/gcc/config/mips/octeon.md +++ b/gcc/config/mips/octeon.md @@ -1,5 +1,5 @@ ;; Octeon pipeline description. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mips/p5600.md b/gcc/config/mips/p5600.md index 29c2d2b..c726035 100644 --- a/gcc/config/mips/p5600.md +++ b/gcc/config/mips/p5600.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for P5600. ;; -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/p6600.md b/gcc/config/mips/p6600.md index c5e2672..109476c 100644 --- a/gcc/config/mips/p6600.md +++ b/gcc/config/mips/p6600.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for P6600. ;; -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index d44484d..b8d43e7 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for MIPS. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/r3900.h b/gcc/config/mips/r3900.h index c42ec7e..d34d7cb 100644 --- a/gcc/config/mips/r3900.h +++ b/gcc/config/mips/r3900.h @@ -1,7 +1,7 @@ /* Definitions of MIPS sub target machine for GNU compiler. Toshiba r3900. You should include mips.h after this. - Copyright (C) 1989-2020 Free Software Foundation, Inc. + Copyright (C) 1989-2021 Free Software Foundation, Inc. Contributed by Gavin Koch (gavin@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mips/rtems.h b/gcc/config/mips/rtems.h index 3bbca31..3118d4d 100644 --- a/gcc/config/mips/rtems.h +++ b/gcc/config/mips/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a MIPS using ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 0ef4321..6a625ed 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/sde.h b/gcc/config/mips/sde.h index 67f5c92..dab2dda 100644 --- a/gcc/config/mips/sde.h +++ b/gcc/config/mips/sde.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. MIPS SDE version. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sde.opt b/gcc/config/mips/sde.opt index 94c3b02..8c3447e 100644 --- a/gcc/config/mips/sde.opt +++ b/gcc/config/mips/sde.opt @@ -1,6 +1,6 @@ ; MIPS SDE options. ; -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/sdemtk.h b/gcc/config/mips/sdemtk.h index 6a5a817..ad886ef 100644 --- a/gcc/config/mips/sdemtk.h +++ b/gcc/config/mips/sdemtk.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. MIPS SDE version, for use with the SDE C library rather than newlib. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md index bdee8ac..1e8975a 100644 --- a/gcc/config/mips/sr71k.md +++ b/gcc/config/mips/sr71k.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/st.h b/gcc/config/mips/st.h index 90b151c..d518a1e 100644 --- a/gcc/config/mips/st.h +++ b/gcc/config/mips/st.h @@ -1,5 +1,5 @@ /* ST 2e / 2f GNU/Linux Configuration. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md index 9949100..e34958f 100644 --- a/gcc/config/mips/sync.md +++ b/gcc/config/mips/sync.md @@ -1,6 +1,6 @@ ;; Machine Description for MIPS based processor synchronization ;; instructions. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mips/t-elf b/gcc/config/mips/t-elf index ac66d33..4df281b 100644 --- a/gcc/config/mips/t-elf +++ b/gcc/config/mips/t-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1999-2020 Free Software Foundation, Inc. +# Copyright (C) 1999-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-img-elf b/gcc/config/mips/t-img-elf index 51b9fdb..fa5f228 100644 --- a/gcc/config/mips/t-img-elf +++ b/gcc/config/mips/t-img-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2014-2020 Free Software Foundation, Inc. +# Copyright (C) 2014-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-img-linux b/gcc/config/mips/t-img-linux index cd4994a..75e9b18 100644 --- a/gcc/config/mips/t-img-linux +++ b/gcc/config/mips/t-img-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2014-2020 Free Software Foundation, Inc. +# Copyright (C) 2014-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-isa3264 b/gcc/config/mips/t-isa3264 index 4c31234..658d1fb 100644 --- a/gcc/config/mips/t-isa3264 +++ b/gcc/config/mips/t-isa3264 @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-linux64 b/gcc/config/mips/t-linux64 index ceb58d3..130e1f0 100644 --- a/gcc/config/mips/t-linux64 +++ b/gcc/config/mips/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mips b/gcc/config/mips/t-mips index 40fb0da..3bdbf31 100644 --- a/gcc/config/mips/t-mips +++ b/gcc/config/mips/t-mips @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mti-elf b/gcc/config/mips/t-mti-elf index a633c80..b4cf0ae 100644 --- a/gcc/config/mips/t-mti-elf +++ b/gcc/config/mips/t-mti-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mti-linux b/gcc/config/mips/t-mti-linux index 2170278..ba290a6 100644 --- a/gcc/config/mips/t-mti-linux +++ b/gcc/config/mips/t-mti-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900 index 3ef69e9..5bf350a 100644 --- a/gcc/config/mips/t-r3900 +++ b/gcc/config/mips/t-r3900 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2020 Free Software Foundation, Inc. +# Copyright (C) 1998-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-rtems b/gcc/config/mips/t-rtems index 2b492fd..d1d89a0 100644 --- a/gcc/config/mips/t-rtems +++ b/gcc/config/mips/t-rtems @@ -1,6 +1,6 @@ # Custom multilibs for RTEMS # -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sb1 b/gcc/config/mips/t-sb1 index 3fd01ca..5842a31 100644 --- a/gcc/config/mips/t-sb1 +++ b/gcc/config/mips/t-sb1 @@ -1,4 +1,4 @@ -# Copyright (C) 2006-2020 Free Software Foundation, Inc. +# Copyright (C) 2006-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sde b/gcc/config/mips/t-sde index e609dd6..d7a9f69 100644 --- a/gcc/config/mips/t-sde +++ b/gcc/config/mips/t-sde @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sdemtk b/gcc/config/mips/t-sdemtk index f6646c0..372e062 100644 --- a/gcc/config/mips/t-sdemtk +++ b/gcc/config/mips/t-sdemtk @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2020 Free Software Foundation, Inc. +# Copyright (C) 2007-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sr71k b/gcc/config/mips/t-sr71k index d4a960b..a2ba5e9 100644 --- a/gcc/config/mips/t-sr71k +++ b/gcc/config/mips/t-sr71k @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-st b/gcc/config/mips/t-st index d718d88..5b564be 100644 --- a/gcc/config/mips/t-st +++ b/gcc/config/mips/t-st @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2020 Free Software Foundation, Inc. +# Copyright (C) 2008-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-vr b/gcc/config/mips/t-vr index b3cc062..26358ab 100644 --- a/gcc/config/mips/t-vr +++ b/gcc/config/mips/t-vr @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-vxworks b/gcc/config/mips/t-vxworks index fd1dd40..d76e5a8 100644 --- a/gcc/config/mips/t-vxworks +++ b/gcc/config/mips/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2020 Free Software Foundation, Inc. +# Copyright (C) 2003-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/vr.h b/gcc/config/mips/vr.h index e04d5bd..0eeb325 100644 --- a/gcc/config/mips/vr.h +++ b/gcc/config/mips/vr.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. NEC VR Series Processors - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/mips/vxworks.h b/gcc/config/mips/vxworks.h index 762e579..6d1b782 100644 --- a/gcc/config/mips/vxworks.h +++ b/gcc/config/mips/vxworks.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1999-2020 Free Software Foundation, Inc. +/* Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/xlp.md b/gcc/config/mips/xlp.md index d17ceba..723214b 100644 --- a/gcc/config/mips/xlp.md +++ b/gcc/config/mips/xlp.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the XLP. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; xlp.md Machine Description for the Broadcom XLP Microprocessor ;; This file is part of GCC. diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md index b2f1539..fadecdc 100644 --- a/gcc/config/mips/xlr.md +++ b/gcc/config/mips/xlr.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the XLR. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; ;; xlr.md Machine Description for the RMI XLR Microprocessor ;; This file is part of GCC. diff --git a/gcc/config/mmix/constraints.md b/gcc/config/mmix/constraints.md index c216c93..331232c 100644 --- a/gcc/config/mmix/constraints.md +++ b/gcc/config/mmix/constraints.md @@ -1,5 +1,5 @@ ;; MMIX constraints -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mmix/mmix-modes.def b/gcc/config/mmix/mmix-modes.def index 65e6de3..e9ab0c3 100644 --- a/gcc/config/mmix/mmix-modes.def +++ b/gcc/config/mmix/mmix-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix-protos.h b/gcc/config/mmix/mmix-protos.h index d82364d..75aab9e 100644 --- a/gcc/config/mmix/mmix-protos.h +++ b/gcc/config/mmix/mmix-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in mmix.c - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c index 4c4fb21..40bfb43 100644 --- a/gcc/config/mmix/mmix.c +++ b/gcc/config/mmix/mmix.c @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h index ac0be10..fc43e49 100644 --- a/gcc/config/mmix/mmix.h +++ b/gcc/config/mmix/mmix.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md index f41a5b2..a6d7608 100644 --- a/gcc/config/mmix/mmix.md +++ b/gcc/config/mmix/mmix.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMIX -;; Copyright (C) 2000-2020 Free Software Foundation, Inc. +;; Copyright (C) 2000-2021 Free Software Foundation, Inc. ;; Contributed by Hans-Peter Nilsson (hp@bitrange.com) ;; This file is part of GCC. diff --git a/gcc/config/mmix/mmix.opt b/gcc/config/mmix/mmix.opt index c0d3be3..32026f2 100644 --- a/gcc/config/mmix/mmix.opt +++ b/gcc/config/mmix/mmix.opt @@ -1,6 +1,6 @@ ; Options for the MMIX port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -20,48 +20,48 @@ ; FIXME: Get rid of this one. mlibfuncs -Target Report Mask(LIBFUNC) +Target Mask(LIBFUNC) For intrinsics library: pass all parameters in registers. mabi=mmixware -Target Report RejectNegative InverseMask(ABI_GNU) +Target RejectNegative InverseMask(ABI_GNU) Use register stack for parameters and return value. mabi=gnu -Target Report RejectNegative Mask(ABI_GNU) +Target RejectNegative Mask(ABI_GNU) Use call-clobbered registers for parameters and return value. ; FIXME: Provide a way to *load* the epsilon register. mepsilon -Target Report Mask(FCMP_EPSILON) +Target Mask(FCMP_EPSILON) Use epsilon-respecting floating point compare instructions. mzero-extend -Target Report Mask(ZERO_EXTEND) +Target Mask(ZERO_EXTEND) Use zero-extending memory loads, not sign-extending ones. mknuthdiv -Target Report Mask(KNUTH_DIVISION) +Target Mask(KNUTH_DIVISION) Generate divide results with reminder having the same sign as the divisor (not the dividend). mtoplevel-symbols -Target Report Mask(TOPLEVEL_SYMBOLS) +Target Mask(TOPLEVEL_SYMBOLS) Prepend global symbols with \":\" (for use with PREFIX). mno-set-program-start -Target Report RejectNegative +Target RejectNegative Do not provide a default start-address 0x100 of the program. melf -Target Report RejectNegative +Target RejectNegative Link to emit program in ELF format (rather than mmo). mbranch-predict -Target Report RejectNegative Mask(BRANCH_PREDICT) +Target RejectNegative Mask(BRANCH_PREDICT) Use P-mnemonics for branches statically predicted as taken. mno-branch-predict -Target Report RejectNegative InverseMask(BRANCH_PREDICT) +Target RejectNegative InverseMask(BRANCH_PREDICT) Don't use P-mnemonics for branches. ; We use the term "base address" since that's what Knuth uses. The base @@ -75,25 +75,25 @@ Don't use P-mnemonics for branches. ; registers, and you'll not find out until link time whether you ; should have compiled with -mno-base-addresses. mbase-addresses -Target Report RejectNegative Mask(BASE_ADDRESSES) +Target RejectNegative Mask(BASE_ADDRESSES) Use addresses that allocate global registers. mno-base-addresses -Target Report RejectNegative InverseMask(BASE_ADDRESSES) +Target RejectNegative InverseMask(BASE_ADDRESSES) Do not use addresses that allocate global registers. msingle-exit -Target Report RejectNegative InverseMask(USE_RETURN_INSN) +Target RejectNegative InverseMask(USE_RETURN_INSN) Generate a single exit point for each function. mno-single-exit -Target Report RejectNegative Mask(USE_RETURN_INSN) +Target RejectNegative Mask(USE_RETURN_INSN) Do not generate a single exit point for each function. mset-program-start= -Target Report RejectNegative Joined +Target RejectNegative Joined Set start-address of the program. mset-data-start= -Target Report RejectNegative Joined +Target RejectNegative Joined Set start-address of data. diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md index 3dd0a96..09180d1 100644 --- a/gcc/config/mmix/predicates.md +++ b/gcc/config/mmix/predicates.md @@ -1,5 +1,5 @@ ;; Operand and operator predicates for the GCC MMIX port. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; This file is part of GCC. ;; diff --git a/gcc/config/mmix/t-mmix b/gcc/config/mmix/t-mmix index ac2f0a0..ee4ab73 100644 --- a/gcc/config/mmix/t-mmix +++ b/gcc/config/mmix/t-mmix @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md index fb09bbf..45cc5cb 100644 --- a/gcc/config/mn10300/constraints.md +++ b/gcc/config/mn10300/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the MN10300. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mn10300/linux.h b/gcc/config/mn10300/linux.h index a336497..657bfe4 100644 --- a/gcc/config/mn10300/linux.h +++ b/gcc/config/mn10300/linux.h @@ -1,6 +1,6 @@ /* Definitions of taret machine for GNU compiler. Matsushita AM33/2.0 - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Alexandre Oliva <aoliva@redhat.com> This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-modes.def b/gcc/config/mn10300/mn10300-modes.def index 759dee7..b1128aa 100644 --- a/gcc/config/mn10300/mn10300-modes.def +++ b/gcc/config/mn10300/mn10300-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MN10300. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-opts.h b/gcc/config/mn10300/mn10300-opts.h index a7b4783..aade7be 100644 --- a/gcc/config/mn10300/mn10300-opts.h +++ b/gcc/config/mn10300/mn10300-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Matsushita MN10300 series. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-protos.h b/gcc/config/mn10300/mn10300-protos.h index b62c042..3ff03b5 100644 --- a/gcc/config/mn10300/mn10300-protos.h +++ b/gcc/config/mn10300/mn10300-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Matsushita MN10300 series - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index ee6e722..bdacade 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Matsushita MN10300 series - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index 2292c5b..d94d8e6 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Matsushita MN10300 series - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index e1a016b..6ce268ef 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -1,5 +1,5 @@ ;; GCC machine description for Matsushita MN10300 -;; Copyright (C) 1996-2020 Free Software Foundation, Inc. +;; Copyright (C) 1996-2021 Free Software Foundation, Inc. ;; Contributed by Jeff Law (law@cygnus.com). ;; This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.opt b/gcc/config/mn10300/mn10300.opt index 13b45e1..f93f1b9 100644 --- a/gcc/config/mn10300/mn10300.opt +++ b/gcc/config/mn10300/mn10300.opt @@ -1,6 +1,6 @@ ; Options for the Matsushita MN10300 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -34,7 +34,7 @@ Target Target the AM33/2.0 processor. mam34 -Target Report +Target Target the AM34 processor. mtune= @@ -42,7 +42,7 @@ Target RejectNegative Joined Var(mn10300_tune_string) Tune code for the given processor. mmult-bug -Target Report Mask(MULT_BUG) +Target Mask(MULT_BUG) Work around hardware multiply bug. ; Ignored by the compiler @@ -55,13 +55,13 @@ Target RejectNegative Enable linker relaxations. mreturn-pointer-on-d0 -Target Report Mask(PTR_A0D0) +Target Mask(PTR_A0D0) Return pointers in both a0 and d0. mliw -Target Report Mask(ALLOW_LIW) +Target Mask(ALLOW_LIW) Allow gcc to generate LIW instructions. msetlb -Target Report Mask(ALLOW_SETLB) +Target Mask(ALLOW_SETLB) Allow gcc to generate the SETLB and Lcc instructions. diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md index 149821e..753031c 100644 --- a/gcc/config/mn10300/predicates.md +++ b/gcc/config/mn10300/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Matsushita MN10300. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mn10300/t-mn10300 b/gcc/config/mn10300/t-mn10300 index 817c1982..b94e17a 100644 --- a/gcc/config/mn10300/t-mn10300 +++ b/gcc/config/mn10300/t-mn10300 @@ -1,4 +1,4 @@ -# Copyright (C) 1996-2020 Free Software Foundation, Inc. +# Copyright (C) 1996-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/moxie/constraints.md b/gcc/config/moxie/constraints.md index 0e555df..15518b0 100644 --- a/gcc/config/moxie/constraints.md +++ b/gcc/config/moxie/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Moxie -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/moxie-protos.h b/gcc/config/moxie/moxie-protos.h index 0b8864b..407c164 100644 --- a/gcc/config/moxie/moxie-protos.h +++ b/gcc/config/moxie/moxie-protos.h @@ -1,5 +1,5 @@ /* Prototypes for moxie.c functions used in the md file & elsewhere. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c index eb0f662..fe6680e 100644 --- a/gcc/config/moxie/moxie.c +++ b/gcc/config/moxie/moxie.c @@ -1,5 +1,5 @@ /* Target Code for moxie - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Anthony Green. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 137c0a3..55dee92 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -1,5 +1,5 @@ /* Target Definitions for moxie. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Anthony Green. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md index dacaaa1..17408c9 100644 --- a/gcc/config/moxie/moxie.md +++ b/gcc/config/moxie/moxie.md @@ -1,5 +1,5 @@ ;; Machine description for Moxie -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/moxie.opt b/gcc/config/moxie/moxie.opt index e84edd3..aa40242 100644 --- a/gcc/config/moxie/moxie.opt +++ b/gcc/config/moxie/moxie.opt @@ -1,6 +1,6 @@ ; Options for the moxie compiler port. -; Copyright (C) 2012-2020 Free Software Foundation, Inc. +; Copyright (C) 2012-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,15 +19,15 @@ ; <http://www.gnu.org/licenses/>. meb -Target RejectNegative Report InverseMask(LITTLE_ENDIAN) +Target RejectNegative InverseMask(LITTLE_ENDIAN) Generate big-endian code. mel -Target RejectNegative Report Mask(LITTLE_ENDIAN) +Target RejectNegative Mask(LITTLE_ENDIAN) Generate little-endian code. mmul.x -Target Report Mask(HAS_MULX) +Target Mask(HAS_MULX) Enable MUL.X and UMUL.X instructions. ; Ignored by the compiler diff --git a/gcc/config/moxie/moxiebox.h b/gcc/config/moxie/moxiebox.h index 288f1cb..e5c3f6e 100644 --- a/gcc/config/moxie/moxiebox.h +++ b/gcc/config/moxie/moxiebox.h @@ -1,5 +1,5 @@ /* Definitions for the moxiebox. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com) This file is part of GCC. diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md index f0d8d29..80d8a4c 100644 --- a/gcc/config/moxie/predicates.md +++ b/gcc/config/moxie/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Moxie -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/rtems.h b/gcc/config/moxie/rtems.h index a678edc..b5f1288 100644 --- a/gcc/config/moxie/rtems.h +++ b/gcc/config/moxie/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting the Moxie core. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com) This file is part of GCC. diff --git a/gcc/config/moxie/t-moxie b/gcc/config/moxie/t-moxie index a726143..405e946 100644 --- a/gcc/config/moxie/t-moxie +++ b/gcc/config/moxie/t-moxie @@ -1,5 +1,5 @@ # Target Makefile Fragment for moxie -# Copyright (C) 2008-2020 Free Software Foundation, Inc. +# Copyright (C) 2008-2021 Free Software Foundation, Inc. # Contributed by Anthony Green. # # This file is part of GCC. diff --git a/gcc/config/moxie/uclinux.h b/gcc/config/moxie/uclinux.h index 9478aaf..712d126 100644 --- a/gcc/config/moxie/uclinux.h +++ b/gcc/config/moxie/uclinux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2020 Free Software Foundation, Inc. +/* Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/constraints.md b/gcc/config/msp430/constraints.md index b8f9674..e809396 100644 --- a/gcc/config/msp430/constraints.md +++ b/gcc/config/msp430/constraints.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/driver-msp430.c b/gcc/config/msp430/driver-msp430.c index 7ce7a58..1294488 100644 --- a/gcc/config/msp430/driver-msp430.c +++ b/gcc/config/msp430/driver-msp430.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Georg-Johann Lay <avr@gjlay.de> This file is part of GCC. diff --git a/gcc/config/msp430/msp430-c.c b/gcc/config/msp430/msp430-c.c index a073d08..cd1eebf 100644 --- a/gcc/config/msp430/msp430-c.c +++ b/gcc/config/msp430/msp430-c.c @@ -1,5 +1,5 @@ /* MSP430 C-specific support - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-devices.c b/gcc/config/msp430/msp430-devices.c index 088b0ff..8a3d090 100644 --- a/gcc/config/msp430/msp430-devices.c +++ b/gcc/config/msp430/msp430-devices.c @@ -1,5 +1,5 @@ /* Subroutines used for reading MCU data on TI MSP430 processors. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Jozef Lawrynowicz <jozef.l@mittosystems.com>. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-devices.h b/gcc/config/msp430/msp430-devices.h index c012e13..06265df 100644 --- a/gcc/config/msp430/msp430-devices.h +++ b/gcc/config/msp430/msp430-devices.h @@ -1,5 +1,5 @@ /* Definitions of subroutines used for reading MCU data on TI MSP430 processors. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. Contributed by Jozef Lawrynowicz <jozef.l@mittosystems.com>. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-opts.h b/gcc/config/msp430/msp430-opts.h index fa64677..8916d73 100644 --- a/gcc/config/msp430/msp430-opts.h +++ b/gcc/config/msp430/msp430-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the TI MSP430 - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-protos.h b/gcc/config/msp430/msp430-protos.h index 33ad1ad..524fada 100644 --- a/gcc/config/msp430/msp430-protos.h +++ b/gcc/config/msp430/msp430-protos.h @@ -1,5 +1,5 @@ /* Exported function prototypes from the TI MSP430 backend. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index db3a9ff..581e051 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on TI MSP430 processors. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h index 049151e..cf64be2 100644 --- a/gcc/config/msp430/msp430.h +++ b/gcc/config/msp430/msp430.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the TI MSP430 Processor - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 1ec219c..752b062 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/msp430.opt b/gcc/config/msp430/msp430.opt index 692e7dc..56dc996 100644 --- a/gcc/config/msp430/msp430.opt +++ b/gcc/config/msp430/msp430.opt @@ -3,7 +3,7 @@ Target Use simulator runtime. mtiny-printf -Target Report Mask(TINY_PRINTF) +Target Mask(TINY_PRINTF) Use a lightweight configuration of printf and puts to reduce code size. For single-threaded applications, not requiring reentrant I/O only. Requires Newlib Nano IO. masm-hex @@ -11,19 +11,19 @@ Target Mask(ASM_HEX) Force assembly output to always use hex constants. mmcu= -Target Report ToLower Joined RejectNegative Var(target_mcu) +Target ToLower Joined RejectNegative Var(target_mcu) Specify the MCU to build for. mwarn-mcu -Target Report Var(msp430_warn_mcu) Init(1) +Target Var(msp430_warn_mcu) Init(1) Warn if an MCU name is unrecognized or conflicts with other options (default: on). mwarn-devices-csv -Target Report Var(msp430_warn_devices_csv) Init(1) +Target Var(msp430_warn_devices_csv) Init(1) Warn if devices.csv is not found or there are problem parsing it (default: on). mcpu= -Target Report Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT) +Target Joined RejectNegative Var(target_cpu) ToLower Enum(msp430_cpu_types) Init(MSP430_CPU_MSP430X_DEFAULT) Specify the ISA to build for: msp430, msp430x, msp430xv2. Enum @@ -48,29 +48,29 @@ EnumValue Enum(msp430_cpu_types) String(430xv2) Value(MSP430_CPU_MSP430XV2) mlarge -Target Report Mask(LARGE) RejectNegative +Target Mask(LARGE) RejectNegative Select large model - 20-bit addresses/pointers. msmall -Target Report InverseMask(LARGE) RejectNegative +Target InverseMask(LARGE) RejectNegative Select small model - 16-bit addresses/pointers (default). mrelax -Target Report +Target Optimize opcode sizes at link time. mOs Target Undocumented Mask(OPT_SPACE) minrt -Target Report Mask(MINRT) RejectNegative +Target Mask(MINRT) RejectNegative Use a minimum runtime (no static initializers or ctors) for memory-constrained devices. HeaderInclude config/msp430/msp430-opts.h mhwmult= -Target Joined RejectNegative Report ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO) +Target Joined RejectNegative ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(MSP430_HWMULT_AUTO) Specify the type of hardware multiply to support. Enum @@ -92,15 +92,15 @@ EnumValue Enum(msp430_hwmult_types) String(f5series) Value(MSP430_HWMULT_F5SERIES) mcode-region= -Target Joined RejectNegative Report ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) +Target Joined RejectNegative ToLower Var(msp430_code_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) Specify whether functions should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower). mdata-region= -Target Joined RejectNegative Report ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) +Target Joined RejectNegative ToLower Var(msp430_data_region) Enum(msp430_regions) Init(MSP430_REGION_LOWER) Specify whether variables should be placed into the lower or upper memory regions, or if they should be shuffled between the regions (either) for best fit (default: lower). muse-lower-region-prefix -Target Mask(USE_LOWER_REGION_PREFIX) Report +Target Mask(USE_LOWER_REGION_PREFIX) Add the .lower prefix to section names when compiling with -m{code,data}-region=lower (disabled by default). Enum @@ -119,20 +119,20 @@ EnumValue Enum(msp430_regions) String(upper) Value(MSP430_REGION_UPPER) msilicon-errata= -Target Joined RejectNegative Report ToLower +Target Joined RejectNegative ToLower Passes on a request to the assembler to enable fixes for various silicon errata. msilicon-errata-warn= -Target Joined RejectNegative Report ToLower +Target Joined RejectNegative ToLower Passes on a request to the assembler to warn about various silicon errata. mdevices-csv-loc= -Target Joined Var(msp430_devices_csv_loc) RejectNegative Report +Target Joined Var(msp430_devices_csv_loc) RejectNegative The path to devices.csv. The GCC driver can normally locate devices.csv itself and pass this option to the compiler, so the user shouldn't need to pass this. mmax-inline-shift= -Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65) Report +Target RejectNegative Joined UInteger IntegerRange(0,65) Var(msp430_max_inline_shift) Init(65) For shift operations by a constant amount, which require an individual instruction to shift by one position, set the maximum number of inline shift instructions (maximum value 64) to emit instead of using the corresponding __mspabi helper function. The default value is 4. diff --git a/gcc/config/msp430/predicates.md b/gcc/config/msp430/predicates.md index eb1f61d..9ab8cb4 100644 --- a/gcc/config/msp430/predicates.md +++ b/gcc/config/msp430/predicates.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/t-msp430 b/gcc/config/msp430/t-msp430 index 9710e7f..ecf4793 100644 --- a/gcc/config/msp430/t-msp430 +++ b/gcc/config/msp430/t-msp430 @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the TI MSP430 target. -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/nds32/constants.md b/gcc/config/nds32/constants.md index 0c14f86..4ec18a6 100644 --- a/gcc/config/nds32/constants.md +++ b/gcc/config/nds32/constants.md @@ -1,5 +1,5 @@ ;; Constant defintions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md index ab9601f..0bc7ca0 100644 --- a/gcc/config/nds32/constraints.md +++ b/gcc/config/nds32/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/elf.h b/gcc/config/nds32/elf.h index f78e20e9..1cd8a5f 100644 --- a/gcc/config/nds32/elf.h +++ b/gcc/config/nds32/elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/iterators.md b/gcc/config/nds32/iterators.md index 5a22a60..293e498 100644 --- a/gcc/config/nds32/iterators.md +++ b/gcc/config/nds32/iterators.md @@ -1,6 +1,6 @@ ;; Code and mode itertator and attribute definitions ;; of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/linux.h b/gcc/config/nds32/linux.h index b8ba05c..2cd66d5 100644 --- a/gcc/config/nds32/linux.h +++ b/gcc/config/nds32/linux.h @@ -1,5 +1,5 @@ /* Definitions of target machine of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-cost.c b/gcc/config/nds32/nds32-cost.c index 9112230..ce82cb3 100644 --- a/gcc/config/nds32/nds32-cost.c +++ b/gcc/config/nds32/nds32-cost.c @@ -1,5 +1,5 @@ /* Subroutines used for calculate rtx costs of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-doubleword.md b/gcc/config/nds32/nds32-doubleword.md index 3ba62c8..7e824bc 100644 --- a/gcc/config/nds32/nds32-doubleword.md +++ b/gcc/config/nds32/nds32-doubleword.md @@ -1,5 +1,5 @@ ;; DImode/DFmode patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-dspext.md b/gcc/config/nds32/nds32-dspext.md index 4e4015f..5035a7f 100644 --- a/gcc/config/nds32/nds32-dspext.md +++ b/gcc/config/nds32/nds32-dspext.md @@ -1,5 +1,5 @@ ;; Machine description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-e8.md b/gcc/config/nds32/nds32-e8.md index 6c3aa1f..171099d 100644 --- a/gcc/config/nds32/nds32-e8.md +++ b/gcc/config/nds32/nds32-e8.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c index 7828321..0c0ecef 100644 --- a/gcc/config/nds32/nds32-fp-as-gp.c +++ b/gcc/config/nds32/nds32-fp-as-gp.c @@ -1,5 +1,5 @@ /* The fp-as-gp pass of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-fpu.md b/gcc/config/nds32/nds32-fpu.md index 95c146a..69f3146 100644 --- a/gcc/config/nds32/nds32-fpu.md +++ b/gcc/config/nds32/nds32-fpu.md @@ -1,5 +1,5 @@ ;; Machine description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-graywolf.md b/gcc/config/nds32/nds32-graywolf.md index dedd5a7..e8f1fd0 100644 --- a/gcc/config/nds32/nds32-graywolf.md +++ b/gcc/config/nds32/nds32-graywolf.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-intrinsic.c b/gcc/config/nds32/nds32-intrinsic.c index 7645236..74c63c1 100644 --- a/gcc/config/nds32/nds32-intrinsic.c +++ b/gcc/config/nds32/nds32-intrinsic.c @@ -1,5 +1,5 @@ /* Intrinsic functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-intrinsic.md b/gcc/config/nds32/nds32-intrinsic.md index 0e335da..e8e06c0 100644 --- a/gcc/config/nds32/nds32-intrinsic.md +++ b/gcc/config/nds32/nds32-intrinsic.md @@ -1,5 +1,5 @@ ;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-isr.c b/gcc/config/nds32/nds32-isr.c index ceb10d2..129200e 100644 --- a/gcc/config/nds32/nds32-isr.c +++ b/gcc/config/nds32/nds32-isr.c @@ -1,5 +1,5 @@ /* Subroutines used for ISR of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c index 055a582..d05f97e 100644 --- a/gcc/config/nds32/nds32-md-auxiliary.c +++ b/gcc/config/nds32/nds32-md-auxiliary.c @@ -1,6 +1,6 @@ /* Auxiliary functions for output asm template or expand rtl pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-memory-manipulation.c b/gcc/config/nds32/nds32-memory-manipulation.c index b38d332..bede2d5 100644 --- a/gcc/config/nds32/nds32-memory-manipulation.c +++ b/gcc/config/nds32/nds32-memory-manipulation.c @@ -1,6 +1,6 @@ /* Auxiliary functions for expand cpymem, setmem, cmpmem, load_multiple and store_multiple pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-modes.def b/gcc/config/nds32/nds32-modes.def index 736602b..570c63b 100644 --- a/gcc/config/nds32/nds32-modes.def +++ b/gcc/config/nds32/nds32-modes.def @@ -1,5 +1,5 @@ /* Extra machine modes of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md index 4818cf0..469b566 100644 --- a/gcc/config/nds32/nds32-multiple.md +++ b/gcc/config/nds32/nds32-multiple.md @@ -1,5 +1,5 @@ ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation.for NDS32. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n10.md b/gcc/config/nds32/nds32-n10.md index 5f3d6ae..bbe5d11 100644 --- a/gcc/config/nds32/nds32-n10.md +++ b/gcc/config/nds32/nds32-n10.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n13.md b/gcc/config/nds32/nds32-n13.md index 7a554c6..cbebf08 100644 --- a/gcc/config/nds32/nds32-n13.md +++ b/gcc/config/nds32/nds32-n13.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n7.md b/gcc/config/nds32/nds32-n7.md index 25336ec..07d16fa 100644 --- a/gcc/config/nds32/nds32-n7.md +++ b/gcc/config/nds32/nds32-n7.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n8.md b/gcc/config/nds32/nds32-n8.md index 5b98928..2f91f9f 100644 --- a/gcc/config/nds32/nds32-n8.md +++ b/gcc/config/nds32/nds32-n8.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n9-2r1w.md b/gcc/config/nds32/nds32-n9-2r1w.md index d9ba928..4fa1702 100644 --- a/gcc/config/nds32/nds32-n9-2r1w.md +++ b/gcc/config/nds32/nds32-n9-2r1w.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-n9-3r2w.md b/gcc/config/nds32/nds32-n9-3r2w.md index c5ec9f0..7141765 100644 --- a/gcc/config/nds32/nds32-n9-3r2w.md +++ b/gcc/config/nds32/nds32-n9-3r2w.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-opts.h b/gcc/config/nds32/nds32-opts.h index e339e72..7bb030d 100644 --- a/gcc/config/nds32/nds32-opts.h +++ b/gcc/config/nds32/nds32-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-peephole2.md b/gcc/config/nds32/nds32-peephole2.md index c7900e7..7f51c21 100644 --- a/gcc/config/nds32/nds32-peephole2.md +++ b/gcc/config/nds32/nds32-peephole2.md @@ -1,5 +1,5 @@ ;; define_peephole2 optimization patterns of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c index 005402b..709e7bc 100644 --- a/gcc/config/nds32/nds32-pipelines-auxiliary.c +++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c @@ -1,6 +1,6 @@ /* Auxiliary functions for pipeline descriptions pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c index 7388970..b4b94ae 100644 --- a/gcc/config/nds32/nds32-predicates.c +++ b/gcc/config/nds32/nds32-predicates.c @@ -1,5 +1,5 @@ /* Predicate functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index d44d82f..7a762e4 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-relax-opt.c b/gcc/config/nds32/nds32-relax-opt.c index 4bd7238..9bd1545 100644 --- a/gcc/config/nds32/nds32-relax-opt.c +++ b/gcc/config/nds32/nds32-relax-opt.c @@ -1,5 +1,5 @@ /* relax-opt pass of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c index 6973da4..b3ee246 100644 --- a/gcc/config/nds32/nds32-utils.c +++ b/gcc/config/nds32/nds32-utils.c @@ -1,6 +1,6 @@ /* Auxiliary functions for pipeline descriptions pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index acf1371..226da0b 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index 17a9ddc..c5947cb 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -1,5 +1,5 @@ /* Definitions of target machine of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 146404c..bf73cd1 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -1,5 +1,5 @@ ;; Machine description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt index 053e810..b449074 100644 --- a/gcc/config/nds32/nds32.opt +++ b/gcc/config/nds32/nds32.opt @@ -1,5 +1,5 @@ ; Options of Andes NDS32 cpu for GNU compiler -; Copyright (C) 2012-2020 Free Software Foundation, Inc. +; Copyright (C) 2012-2021 Free Software Foundation, Inc. ; Contributed by Andes Technology Corporation. ; ; This file is part of GCC. @@ -67,11 +67,11 @@ Specify use soft floating point ABI which mean alias to -mabi=2fp+. ; --------------------------------------------------------------- mreduced-regs -Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) +Target RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS) Use reduced-set registers for register allocation. mfull-regs -Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) +Target RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS) Use full-set registers for register allocation. ; --------------------------------------------------------------- @@ -115,43 +115,43 @@ EnumValue Enum(nds32_ict_model_type) String(large) Value(ICT_MODEL_LARGE) mcmov -Target Report Mask(CMOV) +Target Mask(CMOV) Generate conditional move instructions. mhw-abs -Target Report Mask(HW_ABS) +Target Mask(HW_ABS) Generate hardware abs instructions. mext-perf -Target Report Mask(EXT_PERF) +Target Mask(EXT_PERF) Generate performance extension instructions. mext-perf2 -Target Report Mask(EXT_PERF2) +Target Mask(EXT_PERF2) Generate performance extension version 2 instructions. mext-string -Target Report Mask(EXT_STRING) +Target Mask(EXT_STRING) Generate string extension instructions. mext-dsp -Target Report Mask(EXT_DSP) +Target Mask(EXT_DSP) Generate DSP extension instructions. mv3push -Target Report Mask(V3PUSH) +Target Mask(V3PUSH) Generate v3 push25/pop25 instructions. m16-bit -Target Report Mask(16_BIT) +Target Mask(16_BIT) Generate 16-bit instructions. mrelax-hint -Target Report Mask(RELAX_HINT) +Target Mask(RELAX_HINT) Insert relax hint for linker to do relaxation. mvh -Target Report Mask(VH) Condition(!TARGET_LINUX_ABI) +Target Mask(VH) Condition(!TARGET_LINUX_ABI) Enable Virtual Hosting support. misr-vector-size= @@ -421,27 +421,27 @@ EnumValue Enum(nds32_register_ports) String(2r1w) Value(REG_PORT_2R1W) mctor-dtor -Target Report +Target Enable constructor/destructor feature. mrelax -Target Report +Target Guide linker to relax instructions. mext-fpu-fma -Target Report Mask(EXT_FPU_FMA) +Target Mask(EXT_FPU_FMA) Generate floating-point multiply-accumulation instructions. mext-fpu-sp -Target Report Mask(FPU_SINGLE) +Target Mask(FPU_SINGLE) Generate single-precision floating-point instructions. mext-fpu-dp -Target Report Mask(FPU_DOUBLE) +Target Mask(FPU_DOUBLE) Generate double-precision floating-point instructions. mforce-no-ext-dsp -Target Undocumented Report Mask(FORCE_NO_EXT_DSP) +Target Undocumented Mask(FORCE_NO_EXT_DSP) Force disable hardware loop, even use -mext-dsp. msched-prolog-epilog @@ -457,9 +457,9 @@ Target Var(flag_always_save_lp) Init(0) Always save $lp in the stack. munaligned-access -Target Report Var(flag_unaligned_access) Init(0) +Target Var(flag_unaligned_access) Init(0) Enable unaligned word and halfword accesses to packed data. minline-asm-r15 -Target Report Var(flag_inline_asm_r15) Init(0) +Target Var(flag_inline_asm_r15) Init(0) Allow use r15 for inline ASM. diff --git a/gcc/config/nds32/nds32_intrinsic.h b/gcc/config/nds32/nds32_intrinsic.h index f40a90a..93ffad6 100644 --- a/gcc/config/nds32/nds32_intrinsic.h +++ b/gcc/config/nds32/nds32_intrinsic.h @@ -1,5 +1,5 @@ /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32_isr.h b/gcc/config/nds32/nds32_isr.h index a43c4e6..3d6a72f 100644 --- a/gcc/config/nds32/nds32_isr.h +++ b/gcc/config/nds32/nds32_isr.h @@ -1,5 +1,5 @@ /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/pipelines.md b/gcc/config/nds32/pipelines.md index c98316b..42774b8 100644 --- a/gcc/config/nds32/pipelines.md +++ b/gcc/config/nds32/pipelines.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md index d1bdb1a..49b8650 100644 --- a/gcc/config/nds32/predicates.md +++ b/gcc/config/nds32/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/t-elf b/gcc/config/nds32/t-elf index c5da4c8..615686f 100644 --- a/gcc/config/nds32/t-elf +++ b/gcc/config/nds32/t-elf @@ -1,5 +1,5 @@ # The multilib settings of Andes NDS32 cpu for GNU compiler -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/nds32/t-linux b/gcc/config/nds32/t-linux index f77ecf0..54020e7 100644 --- a/gcc/config/nds32/t-linux +++ b/gcc/config/nds32/t-linux @@ -1,5 +1,5 @@ # The multilib settings of Andes NDS32 cpu for GNU compiler -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/nds32/t-mlibs b/gcc/config/nds32/t-mlibs index c60cd3e..a741bd9 100644 --- a/gcc/config/nds32/t-mlibs +++ b/gcc/config/nds32/t-mlibs @@ -1,5 +1,5 @@ # The multilib settings of Andes NDS32 cpu for GNU compiler -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/nds32/t-nds32 b/gcc/config/nds32/t-nds32 index 636e6b6..44e41d5 100644 --- a/gcc/config/nds32/t-nds32 +++ b/gcc/config/nds32/t-nds32 @@ -1,5 +1,5 @@ # General rules that all nds32/ targets must have. -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/netbsd-d.c b/gcc/config/netbsd-d.c index 7c30d02..c3ac010 100644 --- a/gcc/config/netbsd-d.c +++ b/gcc/config/netbsd-d.c @@ -1,5 +1,5 @@ /* Functions for generic NetBSD as target machine for GNU D compiler. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd-elf.h b/gcc/config/netbsd-elf.h index b1494af..ab1a958 100644 --- a/gcc/config/netbsd-elf.h +++ b/gcc/config/netbsd-elf.h @@ -1,5 +1,5 @@ /* Common configuration file for NetBSD ELF targets. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd-elf.opt b/gcc/config/netbsd-elf.opt index ea27c6c..b144afc 100644 --- a/gcc/config/netbsd-elf.opt +++ b/gcc/config/netbsd-elf.opt @@ -1,6 +1,6 @@ ; NetBSD ELF-only options. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/netbsd-protos.h b/gcc/config/netbsd-protos.h index b4e228f..7e38909 100644 --- a/gcc/config/netbsd-protos.h +++ b/gcc/config/netbsd-protos.h @@ -1,5 +1,5 @@ /* Prototypes. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd-stdint.h b/gcc/config/netbsd-stdint.h index 91ee236..371bc14 100644 --- a/gcc/config/netbsd-stdint.h +++ b/gcc/config/netbsd-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types for NetBSD systems. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd.c b/gcc/config/netbsd.c index 2c9fec3..31c54fc 100644 --- a/gcc/config/netbsd.c +++ b/gcc/config/netbsd.c @@ -1,5 +1,5 @@ /* Functions for generic NetBSD as target machine for GNU C compiler. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd.h b/gcc/config/netbsd.h index 59e8f37..37ddde1 100644 --- a/gcc/config/netbsd.h +++ b/gcc/config/netbsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all NetBSD targets. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd.opt b/gcc/config/netbsd.opt index e4e49ff..29fd310 100644 --- a/gcc/config/netbsd.opt +++ b/gcc/config/netbsd.opt @@ -1,6 +1,6 @@ ; NetBSD options. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/newlib-stdint.h b/gcc/config/newlib-stdint.h index 2e086f1..65d1fa2c 100644 --- a/gcc/config/newlib-stdint.h +++ b/gcc/config/newlib-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using newlib. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/constraints.md b/gcc/config/nios2/constraints.md index e122ac6..a3b00c2 100644 --- a/gcc/config/nios2/constraints.md +++ b/gcc/config/nios2/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Altera Nios II. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Chung-Lin Tang <cltang@codesourcery.com> ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/elf.h b/gcc/config/nios2/elf.h index 1ed9195..c8732396 100644 --- a/gcc/config/nios2/elf.h +++ b/gcc/config/nios2/elf.h @@ -1,5 +1,5 @@ /* Definitions of ELF target support for Altera Nios II. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/elf.opt b/gcc/config/nios2/elf.opt index 1a0a13e..34ed52a 100644 --- a/gcc/config/nios2/elf.opt +++ b/gcc/config/nios2/elf.opt @@ -1,5 +1,5 @@ ; Options for the Altera Nios II port of the compiler. -; Copyright (C) 2012-2020 Free Software Foundation, Inc. +; Copyright (C) 2012-2021 Free Software Foundation, Inc. ; Contributed by Altera and Mentor Graphics, Inc. ; ; This file is part of GCC. @@ -22,7 +22,7 @@ ; toolchains. msmallc -Target Report RejectNegative +Target RejectNegative Link with a limited version of the C library. msys-lib= @@ -34,5 +34,5 @@ Target RejectNegative Joined Var(nios2_sys_crt0_string) Name of the startfile. mhal -Target Report RejectNegative +Target RejectNegative Link with HAL BSP. diff --git a/gcc/config/nios2/ldstwm.md b/gcc/config/nios2/ldstwm.md index 08797b4..72bf79ba3 100644 --- a/gcc/config/nios2/ldstwm.md +++ b/gcc/config/nios2/ldstwm.md @@ -2,7 +2,7 @@ This file was automatically generated using nios2-ldstwm.sml. Please do not edit manually. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h index 4bdcdcc..08edf152 100644 --- a/gcc/config/nios2/linux.h +++ b/gcc/config/nios2/linux.h @@ -1,6 +1,6 @@ /* Definitions of target support for Altera Nios II systems running GNU/Linux with ELF format. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/nios2-ldstwm.sml b/gcc/config/nios2/nios2-ldstwm.sml index 22afc9c..92c8c9d 100644 --- a/gcc/config/nios2/nios2-ldstwm.sml +++ b/gcc/config/nios2/nios2-ldstwm.sml @@ -1,5 +1,5 @@ (* Auto-generate Nios II R2 CDX ldwm/stwm/push.n/pop.n patterns - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Mentor Graphics. This file is part of GCC. @@ -233,7 +233,7 @@ print " This file was automatically generated using nios2-ldstwm.sml.\n" ^ " Please do not edit manually.\n" ^ "\n" ^ - " Copyright (C) 2014-2020 Free Software Foundation, Inc.\n" ^ + " Copyright (C) 2014-2021 Free Software Foundation, Inc.\n" ^ " Contributed by Mentor Graphics.\n" ^ "\n" ^ " This file is part of GCC.\n" ^ diff --git a/gcc/config/nios2/nios2-opts.h b/gcc/config/nios2/nios2-opts.h index 057267d..25ad688 100644 --- a/gcc/config/nios2/nios2-opts.h +++ b/gcc/config/nios2/nios2-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Nios II. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/nios2-protos.h b/gcc/config/nios2/nios2-protos.h index 0f7e684..df5d0c9 100644 --- a/gcc/config/nios2/nios2-protos.h +++ b/gcc/config/nios2/nios2-protos.h @@ -1,5 +1,5 @@ /* Subroutine declarations for Altera Nios II target support. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c index 5566435..3ff4ff1 100644 --- a/gcc/config/nios2/nios2.c +++ b/gcc/config/nios2/nios2.c @@ -1,5 +1,5 @@ /* Target machine subroutines for Altera Nios II. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. @@ -1186,34 +1186,6 @@ nios2_custom_check_insns (void) break; } - /* Warn if the user has certain exotic operations that won't get used - without -funsafe-math-optimizations. See expand_builtin () in - builtins.c. */ - if (!flag_unsafe_math_optimizations) - for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++) - if (N2FPU_ENABLED_P (i) && N2FPU_UNSAFE_P (i)) - warning (0, "switch %<-mcustom-%s%> has no effect unless " - "%<-funsafe-math-optimizations%> is specified", - N2FPU_NAME (i)); - - /* Warn if the user is trying to use -mcustom-fmins et. al, that won't - get used without -ffinite-math-only. See fold_builtin_fmin_fmax () - in builtins.c. */ - if (!flag_finite_math_only) - for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++) - if (N2FPU_ENABLED_P (i) && N2FPU_FINITE_P (i)) - warning (0, "switch %<-mcustom-%s%> has no effect unless " - "%<-ffinite-math-only%> is specified", N2FPU_NAME (i)); - - /* Warn if the user is trying to use a custom rounding instruction - that won't get used without -fno-math-errno. See - expand_builtin_int_roundingfn_2 () in builtins.c. */ - if (flag_errno_math) - for (i = 0; i < ARRAY_SIZE (nios2_fpu_insn); i++) - if (N2FPU_ENABLED_P (i) && N2FPU_NO_ERRNO_P (i)) - warning (0, "switch %<-mcustom-%s%> has no effect unless " - "%<-fno-math-errno%> is specified", N2FPU_NAME (i)); - if (errors || custom_code_conflict) fatal_error (input_location, "conflicting use of %<-mcustom%> switches, target attributes, " @@ -1236,7 +1208,7 @@ struct nios2_fpu_config int code[n2fpu_code_num]; }; -#define NIOS2_FPU_CONFIG_NUM 3 +#define NIOS2_FPU_CONFIG_NUM 4 static struct nios2_fpu_config custom_fpu_config[NIOS2_FPU_CONFIG_NUM]; static void @@ -1280,6 +1252,27 @@ nios2_init_fpu_configs (void) cfg->code[n2fpu_fsubs] = 254; cfg->code[n2fpu_fdivs] = 255; + NEXT_FPU_CONFIG; + cfg->name = "fph2"; + cfg->code[n2fpu_fabss] = 224; + cfg->code[n2fpu_fnegs] = 225; + cfg->code[n2fpu_fcmpnes] = 226; + cfg->code[n2fpu_fcmpeqs] = 227; + cfg->code[n2fpu_fcmpges] = 228; + cfg->code[n2fpu_fcmpgts] = 229; + cfg->code[n2fpu_fcmples] = 230; + cfg->code[n2fpu_fcmplts] = 231; + cfg->code[n2fpu_fmaxs] = 232; + cfg->code[n2fpu_fmins] = 233; + cfg->code[n2fpu_round] = 248; + cfg->code[n2fpu_fixsi] = 249; + cfg->code[n2fpu_floatis] = 250; + cfg->code[n2fpu_fsqrts] = 251; + cfg->code[n2fpu_fmuls] = 252; + cfg->code[n2fpu_fadds] = 253; + cfg->code[n2fpu_fsubs] = 254; + cfg->code[n2fpu_fdivs] = 255; + #undef NEXT_FPU_CONFIG gcc_assert (i == NIOS2_FPU_CONFIG_NUM); } diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h index e81b928..1840a46 100644 --- a/gcc/config/nios2/nios2.h +++ b/gcc/config/nios2/nios2.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Altera Nios II. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.md b/gcc/config/nios2/nios2.md index be6c7a6..1d0d298 100644 --- a/gcc/config/nios2/nios2.md +++ b/gcc/config/nios2/nios2.md @@ -1,5 +1,5 @@ ;; Machine Description for Altera Nios II. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Jonah Graham (jgraham@altera.com) and ;; Will Reece (wreece@altera.com). ;; Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.opt b/gcc/config/nios2/nios2.opt index 4c6a62b..21cdbdd 100644 --- a/gcc/config/nios2/nios2.opt +++ b/gcc/config/nios2/nios2.opt @@ -1,5 +1,5 @@ ; Options for the Altera Nios II port of the compiler. -; Copyright (C) 2012-2020 Free Software Foundation, Inc. +; Copyright (C) 2012-2021 Free Software Foundation, Inc. ; Contributed by Altera and Mentor Graphics, Inc. ; ; This file is part of GCC. @@ -31,31 +31,31 @@ TargetSave int saved_custom_code_index[256] mhw-div -Target Report Mask(HAS_DIV) +Target Mask(HAS_DIV) Enable DIV, DIVU. mhw-mul -Target Report Mask(HAS_MUL) +Target Mask(HAS_MUL) Enable MUL instructions. mhw-mulx -Target Report Mask(HAS_MULX) +Target Mask(HAS_MULX) Enable MULX instructions, assume fast shifter. mfast-sw-div -Target Report Mask(FAST_SW_DIV) +Target Mask(FAST_SW_DIV) Use table based fast divide (default at -O3). mbypass-cache -Target Report Mask(BYPASS_CACHE) +Target Mask(BYPASS_CACHE) All memory accesses use I/O load/store instructions. mno-cache-volatile -Target Report RejectNegative Mask(BYPASS_CACHE_VOLATILE) +Target RejectNegative Mask(BYPASS_CACHE_VOLATILE) Volatile memory accesses use I/O load/store instructions. mcache-volatile -Target Report RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE) +Target RejectNegative Undocumented InverseMask(BYPASS_CACHE_VOLATILE) Volatile memory accesses do not use I/O load/store instructions. mgpopt= @@ -82,19 +82,19 @@ EnumValue Enum(nios2_gpopt_type) String(all) Value(gpopt_all) mgpopt -Target Report RejectNegative Var(nios2_gpopt_option, gpopt_local) +Target RejectNegative Var(nios2_gpopt_option, gpopt_local) Equivalent to -mgpopt=local. mno-gpopt -Target Report RejectNegative Var(nios2_gpopt_option, gpopt_none) +Target RejectNegative Var(nios2_gpopt_option, gpopt_none) Equivalent to -mgpopt=none. meb -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Use big-endian byte order. mel -Target Report RejectNegative InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Use little-endian byte order. mcustom-fpu-cfg= @@ -102,467 +102,467 @@ Target RejectNegative Joined Var(nios2_custom_fpu_cfg_string) Floating point custom instruction configuration name. mno-custom-ftruncds -Target Report RejectNegative Var(nios2_custom_ftruncds, -1) +Target RejectNegative Var(nios2_custom_ftruncds, -1) Do not use the ftruncds custom instruction. mcustom-ftruncds= -Target Report RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_ftruncds) Init(-1) Integer id (N) of ftruncds custom instruction. mno-custom-fextsd -Target Report RejectNegative Var(nios2_custom_fextsd, -1) +Target RejectNegative Var(nios2_custom_fextsd, -1) Do not use the fextsd custom instruction. mcustom-fextsd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fextsd) Init(-1) Integer id (N) of fextsd custom instruction. mno-custom-fixdu -Target Report RejectNegative Var(nios2_custom_fixdu, -1) +Target RejectNegative Var(nios2_custom_fixdu, -1) Do not use the fixdu custom instruction. mcustom-fixdu= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fixdu) Init(-1) Integer id (N) of fixdu custom instruction. mno-custom-fixdi -Target Report RejectNegative Var(nios2_custom_fixdi, -1) +Target RejectNegative Var(nios2_custom_fixdi, -1) Do not use the fixdi custom instruction. mcustom-fixdi= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fixdi) Init(-1) Integer id (N) of fixdi custom instruction. mno-custom-fixsu -Target Report RejectNegative Var(nios2_custom_fixsu, -1) +Target RejectNegative Var(nios2_custom_fixsu, -1) Do not use the fixsu custom instruction. mcustom-fixsu= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fixsu) Init(-1) Integer id (N) of fixsu custom instruction. mno-custom-fixsi -Target Report RejectNegative Var(nios2_custom_fixsi, -1) +Target RejectNegative Var(nios2_custom_fixsi, -1) Do not use the fixsi custom instruction. mcustom-fixsi= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fixsi) Init(-1) Integer id (N) of fixsi custom instruction. mno-custom-floatud -Target Report RejectNegative Var(nios2_custom_floatud, -1) +Target RejectNegative Var(nios2_custom_floatud, -1) Do not use the floatud custom instruction. mcustom-floatud= -Target Report RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_floatud) Init(-1) Integer id (N) of floatud custom instruction. mno-custom-floatid -Target Report RejectNegative Var(nios2_custom_floatid, -1) +Target RejectNegative Var(nios2_custom_floatid, -1) Do not use the floatid custom instruction. mcustom-floatid= -Target Report RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_floatid) Init(-1) Integer id (N) of floatid custom instruction. mno-custom-floatus -Target Report RejectNegative Var(nios2_custom_floatus, -1) +Target RejectNegative Var(nios2_custom_floatus, -1) Do not use the floatus custom instruction. mcustom-floatus= -Target Report RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_floatus) Init(-1) Integer id (N) of floatus custom instruction. mno-custom-floatis -Target Report RejectNegative Var(nios2_custom_floatis, -1) +Target RejectNegative Var(nios2_custom_floatis, -1) Do not use the floatis custom instruction. mcustom-floatis= -Target Report RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_floatis) Init(-1) Integer id (N) of floatis custom instruction. mno-custom-fcmpned -Target Report RejectNegative Var(nios2_custom_fcmpned, -1) +Target RejectNegative Var(nios2_custom_fcmpned, -1) Do not use the fcmpned custom instruction. mcustom-fcmpned= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpned) Init(-1) Integer id (N) of fcmpned custom instruction. mno-custom-fcmpeqd -Target Report RejectNegative Var(nios2_custom_fcmpeqd, -1) +Target RejectNegative Var(nios2_custom_fcmpeqd, -1) Do not use the fcmpeqd custom instruction. mcustom-fcmpeqd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqd) Init(-1) Integer id (N) of fcmpeqd custom instruction. mno-custom-fcmpged -Target Report RejectNegative Var(nios2_custom_fcmpged, -1) +Target RejectNegative Var(nios2_custom_fcmpged, -1) Do not use the fcmpged custom instruction. mcustom-fcmpged= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpged) Init(-1) Integer id (N) of fcmpged custom instruction. mno-custom-fcmpgtd -Target Report RejectNegative Var(nios2_custom_fcmpgtd, -1) +Target RejectNegative Var(nios2_custom_fcmpgtd, -1) Do not use the fcmpgtd custom instruction. mcustom-fcmpgtd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgtd) Init(-1) Integer id (N) of fcmpgtd custom instruction. mno-custom-fcmpled -Target Report RejectNegative Var(nios2_custom_fcmpled, -1) +Target RejectNegative Var(nios2_custom_fcmpled, -1) Do not use the fcmpled custom instruction. mcustom-fcmpled= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpled) Init(-1) Integer id (N) of fcmpled custom instruction. mno-custom-fcmpltd -Target Report RejectNegative Var(nios2_custom_fcmpltd, -1) +Target RejectNegative Var(nios2_custom_fcmpltd, -1) Do not use the fcmpltd custom instruction. mcustom-fcmpltd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpltd) Init(-1) Integer id (N) of fcmpltd custom instruction. mno-custom-flogd -Target Report RejectNegative Var(nios2_custom_flogd, -1) +Target RejectNegative Var(nios2_custom_flogd, -1) Do not use the flogd custom instruction. mcustom-flogd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_flogd) Init(-1) Integer id (N) of flogd custom instruction. mno-custom-fexpd -Target Report RejectNegative Var(nios2_custom_fexpd, -1) +Target RejectNegative Var(nios2_custom_fexpd, -1) Do not use the fexpd custom instruction. mcustom-fexpd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fexpd) Init(-1) Integer id (N) of fexpd custom instruction. mno-custom-fatand -Target Report RejectNegative Var(nios2_custom_fatand, -1) +Target RejectNegative Var(nios2_custom_fatand, -1) Do not use the fatand custom instruction. mcustom-fatand= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fatand) Init(-1) Integer id (N) of fatand custom instruction. mno-custom-ftand -Target Report RejectNegative Var(nios2_custom_ftand, -1) +Target RejectNegative Var(nios2_custom_ftand, -1) Do not use the ftand custom instruction. mcustom-ftand= -Target Report RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_ftand) Init(-1) Integer id (N) of ftand custom instruction. mno-custom-fsind -Target Report RejectNegative Var(nios2_custom_fsind, -1) +Target RejectNegative Var(nios2_custom_fsind, -1) Do not use the fsind custom instruction. mcustom-fsind= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsind) Init(-1) Integer id (N) of fsind custom instruction. mno-custom-fcosd -Target Report RejectNegative Var(nios2_custom_fcosd, -1) +Target RejectNegative Var(nios2_custom_fcosd, -1) Do not use the fcosd custom instruction. mcustom-fcosd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcosd) Init(-1) Integer id (N) of fcosd custom instruction. mno-custom-fsqrtd -Target Report RejectNegative Var(nios2_custom_fsqrtd, -1) +Target RejectNegative Var(nios2_custom_fsqrtd, -1) Do not use the fsqrtd custom instruction. mcustom-fsqrtd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsqrtd) Init(-1) Integer id (N) of fsqrtd custom instruction. mno-custom-fabsd -Target Report RejectNegative Var(nios2_custom_fabsd, -1) +Target RejectNegative Var(nios2_custom_fabsd, -1) Do not use the fabsd custom instruction. mcustom-fabsd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fabsd) Init(-1) Integer id (N) of fabsd custom instruction. mno-custom-fnegd -Target Report RejectNegative Var(nios2_custom_fnegd, -1) +Target RejectNegative Var(nios2_custom_fnegd, -1) Do not use the fnegd custom instruction. mcustom-fnegd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fnegd) Init(-1) Integer id (N) of fnegd custom instruction. mno-custom-fmaxd -Target Report RejectNegative Var(nios2_custom_fmaxd, -1) +Target RejectNegative Var(nios2_custom_fmaxd, -1) Do not use the fmaxd custom instruction. mcustom-fmaxd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmaxd) Init(-1) Integer id (N) of fmaxd custom instruction. mno-custom-fmind -Target Report RejectNegative Var(nios2_custom_fmind, -1) +Target RejectNegative Var(nios2_custom_fmind, -1) Do not use the fmind custom instruction. mcustom-fmind= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmind) Init(-1) Integer id (N) of fmind custom instruction. mno-custom-fdivd -Target Report RejectNegative Var(nios2_custom_fdivd, -1) +Target RejectNegative Var(nios2_custom_fdivd, -1) Do not use the fdivd custom instruction. mcustom-fdivd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fdivd) Init(-1) Integer id (N) of fdivd custom instruction. mno-custom-fmuld -Target Report RejectNegative Var(nios2_custom_fmuld, -1) +Target RejectNegative Var(nios2_custom_fmuld, -1) Do not use the fmuld custom instruction. mcustom-fmuld= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmuld) Init(-1) Integer id (N) of fmuld custom instruction. mno-custom-fsubd -Target Report RejectNegative Var(nios2_custom_fsubd, -1) +Target RejectNegative Var(nios2_custom_fsubd, -1) Do not use the fsubd custom instruction. mcustom-fsubd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsubd) Init(-1) Integer id (N) of fsubd custom instruction. mno-custom-faddd -Target Report RejectNegative Var(nios2_custom_faddd, -1) +Target RejectNegative Var(nios2_custom_faddd, -1) Do not use the faddd custom instruction. mcustom-faddd= -Target Report RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_faddd) Init(-1) Integer id (N) of faddd custom instruction. mno-custom-fcmpnes -Target Report RejectNegative Var(nios2_custom_fcmpnes, -1) +Target RejectNegative Var(nios2_custom_fcmpnes, -1) Do not use the fcmpnes custom instruction. mcustom-fcmpnes= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpnes) Init(-1) Integer id (N) of fcmpnes custom instruction. mno-custom-fcmpeqs -Target Report RejectNegative Var(nios2_custom_fcmpeqs, -1) +Target RejectNegative Var(nios2_custom_fcmpeqs, -1) Do not use the fcmpeqs custom instruction. mcustom-fcmpeqs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpeqs) Init(-1) Integer id (N) of fcmpeqs custom instruction. mno-custom-fcmpges -Target Report RejectNegative Var(nios2_custom_fcmpges, -1) +Target RejectNegative Var(nios2_custom_fcmpges, -1) Do not use the fcmpges custom instruction. mcustom-fcmpges= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpges) Init(-1) Integer id (N) of fcmpges custom instruction. mno-custom-fcmpgts -Target Report RejectNegative Var(nios2_custom_fcmpgts, -1) +Target RejectNegative Var(nios2_custom_fcmpgts, -1) Do not use the fcmpgts custom instruction. mcustom-fcmpgts= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmpgts) Init(-1) Integer id (N) of fcmpgts custom instruction. mno-custom-fcmples -Target Report RejectNegative Var(nios2_custom_fcmples, -1) +Target RejectNegative Var(nios2_custom_fcmples, -1) Do not use the fcmples custom instruction. mcustom-fcmples= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmples) Init(-1) Integer id (N) of fcmples custom instruction. mno-custom-fcmplts -Target Report RejectNegative Var(nios2_custom_fcmplts, -1) +Target RejectNegative Var(nios2_custom_fcmplts, -1) Do not use the fcmplts custom instruction. mcustom-fcmplts= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcmplts) Init(-1) Integer id (N) of fcmplts custom instruction. mno-custom-flogs -Target Report RejectNegative Var(nios2_custom_flogs, -1) +Target RejectNegative Var(nios2_custom_flogs, -1) Do not use the flogs custom instruction. mcustom-flogs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_flogs) Init(-1) Integer id (N) of flogs custom instruction. mno-custom-fexps -Target Report RejectNegative Var(nios2_custom_fexps, -1) +Target RejectNegative Var(nios2_custom_fexps, -1) Do not use the fexps custom instruction. mcustom-fexps= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fexps) Init(-1) Integer id (N) of fexps custom instruction. mno-custom-fatans -Target Report RejectNegative Var(nios2_custom_fatans, -1) +Target RejectNegative Var(nios2_custom_fatans, -1) Do not use the fatans custom instruction. mcustom-fatans= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fatans) Init(-1) Integer id (N) of fatans custom instruction. mno-custom-ftans -Target Report RejectNegative Var(nios2_custom_ftans, -1) +Target RejectNegative Var(nios2_custom_ftans, -1) Do not use the ftans custom instruction. mcustom-ftans= -Target Report RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_ftans) Init(-1) Integer id (N) of ftans custom instruction. mno-custom-fsins -Target Report RejectNegative Var(nios2_custom_fsins, -1) +Target RejectNegative Var(nios2_custom_fsins, -1) Do not use the fsins custom instruction. mcustom-fsins= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsins) Init(-1) Integer id (N) of fsins custom instruction. mno-custom-fcoss -Target Report RejectNegative Var(nios2_custom_fcoss, -1) +Target RejectNegative Var(nios2_custom_fcoss, -1) Do not use the fcoss custom instruction. mcustom-fcoss= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fcoss) Init(-1) Integer id (N) of fcoss custom instruction. mno-custom-fsqrts -Target Report RejectNegative Var(nios2_custom_fsqrts, -1) +Target RejectNegative Var(nios2_custom_fsqrts, -1) Do not use the fsqrts custom instruction. mcustom-fsqrts= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsqrts) Init(-1) Integer id (N) of fsqrts custom instruction. mno-custom-fabss -Target Report RejectNegative Var(nios2_custom_fabss, -1) +Target RejectNegative Var(nios2_custom_fabss, -1) Do not use the fabss custom instr. mcustom-fabss= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fabss) Init(-1) Integer id (N) of fabss custom instruction. mno-custom-fnegs -Target Report RejectNegative Var(nios2_custom_fnegs, -1) +Target RejectNegative Var(nios2_custom_fnegs, -1) Do not use the fnegs custom instruction. mcustom-fnegs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fnegs) Init(-1) Integer id (N) of fnegs custom instruction. mno-custom-fmaxs -Target Report RejectNegative Var(nios2_custom_fmaxs, -1) +Target RejectNegative Var(nios2_custom_fmaxs, -1) Do not use the fmaxs custom instruction. mcustom-fmaxs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmaxs) Init(-1) Integer id (N) of fmaxs custom instruction. mno-custom-fmins -Target Report RejectNegative Var(nios2_custom_fmins, -1) +Target RejectNegative Var(nios2_custom_fmins, -1) Do not use the fmins custom instruction. mcustom-fmins= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmins) Init(-1) Integer id (N) of fmins custom instruction. mno-custom-fdivs -Target Report RejectNegative Var(nios2_custom_fdivs, -1) +Target RejectNegative Var(nios2_custom_fdivs, -1) Do not use the fdivs custom instruction. mcustom-fdivs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fdivs) Init(-1) Integer id (N) of fdivs custom instruction. mno-custom-fmuls -Target Report RejectNegative Var(nios2_custom_fmuls, -1) +Target RejectNegative Var(nios2_custom_fmuls, -1) Do not use the fmuls custom instruction. mcustom-fmuls= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fmuls) Init(-1) Integer id (N) of fmuls custom instruction. mno-custom-fsubs -Target Report RejectNegative Var(nios2_custom_fsubs, -1) +Target RejectNegative Var(nios2_custom_fsubs, -1) Do not use the fsubs custom instruction. mcustom-fsubs= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fsubs) Init(-1) Integer id (N) of fsubs custom instruction. mno-custom-fadds -Target Report RejectNegative Var(nios2_custom_fadds, -1) +Target RejectNegative Var(nios2_custom_fadds, -1) Do not use the fadds custom instruction. mcustom-fadds= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fadds) Init(-1) Integer id (N) of fadds custom instruction. mno-custom-frdy -Target Report RejectNegative Var(nios2_custom_frdy, -1) +Target RejectNegative Var(nios2_custom_frdy, -1) Do not use the frdy custom instruction. mcustom-frdy= -Target Report RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_frdy) Init(-1) Integer id (N) of frdy custom instruction. mno-custom-frdxhi -Target Report RejectNegative Var(nios2_custom_frdxhi, -1) +Target RejectNegative Var(nios2_custom_frdxhi, -1) Do not use the frdxhi custom instruction. mcustom-frdxhi= -Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_frdxhi) Init(-1) Integer id (N) of frdxhi custom instruction. mno-custom-frdxlo -Target Report RejectNegative Var(nios2_custom_frdxlo, -1) +Target RejectNegative Var(nios2_custom_frdxlo, -1) Do not use the frdxlo custom instruction. mcustom-frdxlo= -Target Report RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_frdxlo) Init(-1) Integer id (N) of frdxlo custom instruction. mno-custom-fwry -Target Report RejectNegative Var(nios2_custom_fwry, -1) +Target RejectNegative Var(nios2_custom_fwry, -1) Do not use the fwry custom instruction. mcustom-fwry= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fwry) Init(-1) Integer id (N) of fwry custom instruction. mno-custom-fwrx -Target Report RejectNegative Var(nios2_custom_fwrx, -1) +Target RejectNegative Var(nios2_custom_fwrx, -1) Do not use the fwrx custom instruction. mcustom-fwrx= -Target Report RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_fwrx) Init(-1) Integer id (N) of fwrx custom instruction. mno-custom-round -Target Report RejectNegative Var(nios2_custom_round, -1) +Target RejectNegative Var(nios2_custom_round, -1) Do not use the round custom instruction. mcustom-round= -Target Report RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1) +Target RejectNegative Joined UInteger Var(nios2_custom_round) Init(-1) Integer id (N) of round custom instruction. march= @@ -580,11 +580,11 @@ EnumValue Enum(nios2_arch_type) String(r2) Value(ARCH_R2) mbmx -Target Report Mask(HAS_BMX) +Target Mask(HAS_BMX) Enable generation of R2 BMX instructions. mcdx -Target Report Mask(HAS_CDX) +Target Mask(HAS_CDX) Enable generation of R2 CDX instructions. mgprel-sec= diff --git a/gcc/config/nios2/predicates.md b/gcc/config/nios2/predicates.md index 914bb07..8099740 100644 --- a/gcc/config/nios2/predicates.md +++ b/gcc/config/nios2/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Altera Nios II. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Chung-Lin Tang <cltang@codesourcery.com> ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/rtems.h b/gcc/config/nios2/rtems.h index db66a5b..876e7cc 100644 --- a/gcc/config/nios2/rtems.h +++ b/gcc/config/nios2/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a NIOS2 using ELF. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Chris Johns (chrisj@rtems.org). diff --git a/gcc/config/nios2/sync.md b/gcc/config/nios2/sync.md index e3d3601..f0ef8e3 100644 --- a/gcc/config/nios2/sync.md +++ b/gcc/config/nios2/sync.md @@ -1,5 +1,5 @@ ;; Machine Description for Altera Nios II synchronization primitives. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by Mentor Graphics, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/t-nios2 b/gcc/config/nios2/t-nios2 index 8ce1061..b117512 100644 --- a/gcc/config/nios2/t-nios2 +++ b/gcc/config/nios2/t-nios2 @@ -1,5 +1,5 @@ # Target Makefile Fragment for Altera Nios II. -# Copyright (C) 2013-2020 Free Software Foundation, Inc. +# Copyright (C) 2013-2021 Free Software Foundation, Inc. # Contributed by Altera and Mentor Graphics, Inc. # # This file is part of GCC. diff --git a/gcc/config/nios2/t-rtems b/gcc/config/nios2/t-rtems index f95fa3c..beda832 100644 --- a/gcc/config/nios2/t-rtems +++ b/gcc/config/nios2/t-rtems @@ -1,133 +1,23 @@ # Custom RTEMS multilibs -MULTILIB_OPTIONS = mhw-mul mhw-mulx mhw-div mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254 +# Reset all MULTILIB variables + +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = # Enumeration of multilibs -# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fsubs=254 -# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mhw-div -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fsubs=254 -# MULTILIB_EXCEPTIONS += mhw-mul -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-mulx -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mhw-div/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mhw-div -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fadds=253 -MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fdivs=255 -MULTILIB_EXCEPTIONS += mcustom-fmuls=252/mcustom-fsubs=254 -MULTILIB_EXCEPTIONS += mcustom-fmuls=252 -MULTILIB_EXCEPTIONS += mcustom-fsubs=254 +MULTILIB_OPTIONS += mhw-mul mhw-mulx mhw-div +MULTILIB_DIRNAMES += mul mulx div + +MULTILIB_OPTIONS += mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254 mcustom-fpu-cfg=fph2 +MULTILIB_DIRNAMES += fadds fdivs fmuls fsubs fph2 + +MULTILIB_REQUIRED += mhw-mul +MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div +MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_REQUIRED += mhw-mul/mhw-mulx/mhw-div/mcustom-fpu-cfg=fph2 diff --git a/gcc/config/nvptx/mkoffload.c b/gcc/config/nvptx/mkoffload.c index a3c4099..b0a4dfa 100644 --- a/gcc/config/nvptx/mkoffload.c +++ b/gcc/config/nvptx/mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for PTX. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Nathan Sidwell <nathan@codesourcery.com> and Bernd Schmidt <bernds@codesourcery.com>. diff --git a/gcc/config/nvptx/nvptx-opts.h b/gcc/config/nvptx/nvptx-opts.h index 4044a30..ce88245 100644 --- a/gcc/config/nvptx/nvptx-opts.h +++ b/gcc/config/nvptx/nvptx-opts.h @@ -1,5 +1,5 @@ /* Definitions for the NVPTX port needed for option handling. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/nvptx/nvptx-protos.h b/gcc/config/nvptx/nvptx-protos.h index 68a2e42..1512209 100644 --- a/gcc/config/nvptx/nvptx-protos.h +++ b/gcc/config/nvptx/nvptx-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in nvptx.c. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index 1734947..f08b679 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -1,5 +1,5 @@ /* Target code for NVPTX. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h index 17fe157..2451703 100644 --- a/gcc/config/nvptx/nvptx.h +++ b/gcc/config/nvptx/nvptx.h @@ -1,5 +1,5 @@ /* Target Definitions for NVPTX. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index ccbcd09..0f15609 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -1,5 +1,5 @@ ;; Machine description for NVPTX. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; ;; This file is part of GCC. diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index 045e354..51363e4 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -1,5 +1,5 @@ ; Options for the NVPTX port -; Copyright (C) 2014-2020 Free Software Foundation, Inc. +; Copyright (C) 2014-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -20,35 +20,35 @@ ; It's not clear whether this was ever build/tested/used, so this is no longer ; exposed to the user. ;m32 -;Target Report RejectNegative InverseMask(ABI64) +;Target RejectNegative InverseMask(ABI64) ;Generate code for a 32-bit ABI. m64 -Target Report RejectNegative Mask(ABI64) +Target RejectNegative Mask(ABI64) Generate code for a 64-bit ABI. mmainkernel -Target Report RejectNegative +Target RejectNegative Link in code for a __main kernel. moptimize -Target Report Var(nvptx_optimize) Init(-1) +Target Var(nvptx_optimize) Init(-1) Optimize partition neutering. msoft-stack -Target Report Mask(SOFT_STACK) +Target Mask(SOFT_STACK) Use custom stacks instead of local memory for automatic storage. msoft-stack-reserve-local= -Target Report Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128) +Target Joined RejectNegative UInteger Var(nvptx_softstack_size) Init(128) Specify size of .local memory used for stack when the exact amount is not known. muniform-simt -Target Report Mask(UNIFORM_SIMT) +Target Mask(UNIFORM_SIMT) Generate code that can keep local state uniform across all lanes. mgomp -Target Report Mask(GOMP) +Target Mask(GOMP) Generate code for OpenMP offloading: enables -msoft-stack and -muniform-simt. Enum diff --git a/gcc/config/nvptx/offload.h b/gcc/config/nvptx/offload.h index 8d3e56f..86e9fe7 100644 --- a/gcc/config/nvptx/offload.h +++ b/gcc/config/nvptx/offload.h @@ -1,6 +1,6 @@ /* Support for Nvidia PTX offloading. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd-libpthread.h b/gcc/config/openbsd-libpthread.h index 5013dd3..1140143 100644 --- a/gcc/config/openbsd-libpthread.h +++ b/gcc/config/openbsd-libpthread.h @@ -1,6 +1,6 @@ /* LIB_SPEC appropriate for OpenBSD. Include -lpthread if -pthread is specified on the command line. */ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd.h b/gcc/config/openbsd.h index c99aac6..1538911 100644 --- a/gcc/config/openbsd.h +++ b/gcc/config/openbsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all OpenBSD targets. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd.opt b/gcc/config/openbsd.opt index ae7926a..a4b9171 100644 --- a/gcc/config/openbsd.opt +++ b/gcc/config/openbsd.opt @@ -1,6 +1,6 @@ ; OpenBSD options. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md index 1b75483..883fdd9 100644 --- a/gcc/config/or1k/constraints.md +++ b/gcc/config/or1k/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for OpenRISC -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by Stafford Horne ;; This file is part of GCC. diff --git a/gcc/config/or1k/elf.h b/gcc/config/or1k/elf.h index ecd6bf2..130be9a 100644 --- a/gcc/config/or1k/elf.h +++ b/gcc/config/or1k/elf.h @@ -1,5 +1,5 @@ /* Target Newlib Definitions for OpenRISC. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Stafford Horne. This file is part of GCC. diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt index e24ead1..962cb0b 100644 --- a/gcc/config/or1k/elf.opt +++ b/gcc/config/or1k/elf.opt @@ -1,6 +1,6 @@ ; OpenRISC command line options for newlib binaries -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h index 21cef06..196f3f3 100644 --- a/gcc/config/or1k/linux.h +++ b/gcc/config/or1k/linux.h @@ -1,5 +1,5 @@ /* Linux Definitions for OpenRISC. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Stafford Horne. This file is part of GCC. @@ -42,4 +42,6 @@ %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \ %{static-pie:-Bstatic -pie --no-dynamic-linker -z text}" +#define TARGET_ASM_FILE_END file_end_indicate_exec_stack + #endif /* GCC_OR1K_LINUX_H */ diff --git a/gcc/config/or1k/or1k-protos.h b/gcc/config/or1k/or1k-protos.h index 9ed52e0..bbb54c8 100644 --- a/gcc/config/or1k/or1k-protos.h +++ b/gcc/config/or1k/or1k-protos.h @@ -1,5 +1,5 @@ /* Prototypes for OpenRISC functions used in the md file & elsewhere. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c index 5fa5425..e772a7a 100644 --- a/gcc/config/or1k/or1k.c +++ b/gcc/config/or1k/or1k.c @@ -1,5 +1,5 @@ /* Target Code for OpenRISC - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Stafford Horne based on other ports. This file is part of GCC. diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h index 23db771..fe01ab8 100644 --- a/gcc/config/or1k/or1k.h +++ b/gcc/config/or1k/or1k.h @@ -1,5 +1,5 @@ /* Target Definitions for OpenRISC. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Stafford Horne. This file is part of GCC. @@ -30,6 +30,8 @@ builtin_define ("__or1k__"); \ if (TARGET_CMOV) \ builtin_define ("__or1k_cmov__"); \ + if (TARGET_HARD_FLOAT) \ + builtin_define ("__or1k_hard_float__"); \ builtin_assert ("cpu=or1k"); \ builtin_assert ("machine=or1k"); \ } \ @@ -379,8 +381,19 @@ do { \ /* Always pass the SYMBOL_REF for direct calls to the expanders. */ #define NO_FUNCTION_CSE 1 -/* Profiling */ -#define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0) +#define NO_PROFILE_COUNTERS 1 + +/* Emit rtl for profiling. Output assembler code to call "_mcount" for + profiling a function entry. */ +#define PROFILE_HOOK(LABEL) \ + { \ + rtx fun; \ + fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \ + emit_library_call (fun, LCT_NORMAL, VOIDmode); \ + } + +/* All the work is done in PROFILE_HOOK, but this is still required. */ +#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) /* Dwarf 2 Support */ #define DWARF2_DEBUGGING_INFO 1 @@ -395,4 +408,8 @@ do { \ ((N) < 4 ? HW_TO_GCC_REGNO (25) + (N) : INVALID_REGNUM) #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) +/* Select a format to encode pointers in exception handling data. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ + (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) + #endif /* GCC_OR1K_H */ diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 9028c2f..eb94efb 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -1,5 +1,5 @@ ;; Machine description for OpenRISC -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by Stafford Horne ;; This file is part of GCC. diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt index 03c9b8d..6bd0f3e 100644 --- a/gcc/config/or1k/or1k.opt +++ b/gcc/config/or1k/or1k.opt @@ -1,6 +1,6 @@ ; OpenRISC command line options -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index 751d2dec..ac4c2df 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for OpenRISC -;; Copyright (C) 2018-2020 Free Software Foundation, Inc. +;; Copyright (C) 2018-2021 Free Software Foundation, Inc. ;; Contributed by Stafford Horne ;; This file is part of GCC. diff --git a/gcc/config/or1k/rtems.h b/gcc/config/or1k/rtems.h index d4b8fef..9177a40 100644 --- a/gcc/config/or1k/rtems.h +++ b/gcc/config/or1k/rtems.h @@ -1,5 +1,5 @@ /* Target Newlib Definitions for OpenRISC. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel.sherrill@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/or1k/t-or1k b/gcc/config/or1k/t-or1k index f3d3268..b5b3f8e 100644 --- a/gcc/config/or1k/t-or1k +++ b/gcc/config/or1k/t-or1k @@ -1,5 +1,5 @@ # Target Makefile Fragment for OpenRISC -# Copyright (C) 2018-2020 Free Software Foundation, Inc. +# Copyright (C) 2018-2021 Free Software Foundation, Inc. # Contributed by Stafford Horne. # # This file is part of GCC. diff --git a/gcc/config/pa/constraints.md b/gcc/config/pa/constraints.md index 15c143e..89637ad 100644 --- a/gcc/config/pa/constraints.md +++ b/gcc/config/pa/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for pa -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/pa/elf.h b/gcc/config/pa/elf.h index 1872718..431ebe7 100644 --- a/gcc/config/pa/elf.h +++ b/gcc/config/pa/elf.h @@ -1,5 +1,5 @@ /* Definitions for ELF assembler support. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h index aa45eeb..2e698a6 100644 --- a/gcc/config/pa/pa-64.h +++ b/gcc/config/pa/pa-64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for HPs using the 64bit runtime model. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-d.c b/gcc/config/pa/pa-d.c index dda5558..1de49df 100644 --- a/gcc/config/pa/pa-d.c +++ b/gcc/config/pa/pa-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the HPPA architecture. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h index f5a88a4..771ea19 100644 --- a/gcc/config/pa/pa-hpux.h +++ b/gcc/config/pa/pa-hpux.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP-UX. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux.opt b/gcc/config/pa/pa-hpux.opt index 05676a3..f668f41 100644 --- a/gcc/config/pa/pa-hpux.opt +++ b/gcc/config/pa/pa-hpux.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h index 1aa5f87..a156fac 100644 --- a/gcc/config/pa/pa-hpux10.h +++ b/gcc/config/pa/pa-hpux10.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Tim Moore (moore@defmacro.cs.utah.edu) This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux10.opt b/gcc/config/pa/pa-hpux10.opt index 0fc6c40..86bd8ab 100644 --- a/gcc/config/pa/pa-hpux10.opt +++ b/gcc/config/pa/pa-hpux10.opt @@ -1,6 +1,6 @@ ; Options specific to HP-UX 10. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux1010.h b/gcc/config/pa/pa-hpux1010.h index 96f4919..0230838 100644 --- a/gcc/config/pa/pa-hpux1010.h +++ b/gcc/config/pa/pa-hpux1010.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1010.opt b/gcc/config/pa/pa-hpux1010.opt index a5e8ac8..cc54df1 100644 --- a/gcc/config/pa/pa-hpux1010.opt +++ b/gcc/config/pa/pa-hpux1010.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h index 2820720..1184ce9 100644 --- a/gcc/config/pa/pa-hpux11.h +++ b/gcc/config/pa/pa-hpux11.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1111.h b/gcc/config/pa/pa-hpux1111.h index bc75a83..cfa3072 100644 --- a/gcc/config/pa/pa-hpux1111.h +++ b/gcc/config/pa/pa-hpux1111.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1111.opt b/gcc/config/pa/pa-hpux1111.opt index b79e0c1..9eefd14 100644 --- a/gcc/config/pa/pa-hpux1111.opt +++ b/gcc/config/pa/pa-hpux1111.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux1131.h b/gcc/config/pa/pa-hpux1131.h index c44c929..4cddfc6 100644 --- a/gcc/config/pa/pa-hpux1131.h +++ b/gcc/config/pa/pa-hpux1131.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1131.opt b/gcc/config/pa/pa-hpux1131.opt index c978112..eeb4bd0 100644 --- a/gcc/config/pa/pa-hpux1131.opt +++ b/gcc/config/pa/pa-hpux1131.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h index 1326df0..758be76 100644 --- a/gcc/config/pa/pa-linux.h +++ b/gcc/config/pa/pa-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-modes.def b/gcc/config/pa/pa-modes.def index d17ee61..769de66 100644 --- a/gcc/config/pa/pa-modes.def +++ b/gcc/config/pa/pa-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the HP Spectrum. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah. diff --git a/gcc/config/pa/pa-netbsd.h b/gcc/config/pa/pa-netbsd.h index 567a708..6677bfe 100644 --- a/gcc/config/pa/pa-netbsd.h +++ b/gcc/config/pa/pa-netbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-openbsd.h b/gcc/config/pa/pa-openbsd.h index 4a56e91..494ddf2 100644 --- a/gcc/config/pa/pa-openbsd.h +++ b/gcc/config/pa/pa-openbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-opts.h b/gcc/config/pa/pa-opts.h index a2e38a5b..6ccf909 100644 --- a/gcc/config/pa/pa-opts.h +++ b/gcc/config/pa/pa-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for HP PA. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h index 5222ce6..0e1e471 100644 --- a/gcc/config/pa/pa-protos.h +++ b/gcc/config/pa/pa-protos.h @@ -1,5 +1,5 @@ /* Prototypes for pa.c functions used in the md file & elsewhere. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 210e44f..3921b5c 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for HPPA. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c This file is part of GCC. diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index b3eb81d7..3ec015a 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the HP Spectrum. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 3a82fac..b314f96 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -1,5 +1,5 @@ ;;- Machine description for HP PA-RISC architecture for GCC compiler -;; Copyright (C) 1992-2020 Free Software Foundation, Inc. +;; Copyright (C) 1992-2021 Free Software Foundation, Inc. ;; Contributed by the Center for Software Science at the University ;; of Utah. diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index c286663..09660c4 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -42,23 +42,23 @@ Target Ignore Does nothing. Preserved for backward compatibility. mcaller-copies -Target Report Mask(CALLER_COPIES) +Target Mask(CALLER_COPIES) Caller copies function arguments passed by hidden reference. mcoherent-ldcw -Target Report Var(TARGET_COHERENT_LDCW) Init(1) +Target Var(TARGET_COHERENT_LDCW) Init(1) Use ldcw/ldcd coherent cache-control hint. mdisable-fpregs -Target Report Mask(DISABLE_FPREGS) +Target Mask(DISABLE_FPREGS) Disable FP regs. mdisable-indexing -Target Report Mask(DISABLE_INDEXING) +Target Mask(DISABLE_INDEXING) Disable indexed addressing. mfast-indirect-calls -Target Report Mask(FAST_INDIRECT_CALLS) +Target Mask(FAST_INDIRECT_CALLS) Generate fast indirect calls. mfixed-range= @@ -66,7 +66,7 @@ Target RejectNegative Joined Var(pa_deferred_options) Defer Specify range of registers to make fixed. mgas -Target Report Mask(GAS) +Target Mask(GAS) Assume code will be assembled by GAS. mjump-in-delay @@ -79,11 +79,11 @@ Target RejectNegative Enable linker optimizations. mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Always generate long calls. mlong-load-store -Target Report Mask(LONG_LOAD_STORE) +Target Mask(LONG_LOAD_STORE) Emit long load/store sequences. mnosnake @@ -91,11 +91,11 @@ Target RejectNegative Generate PA1.0 code. mno-space-regs -Target RejectNegative Report Mask(NO_SPACE_REGS) +Target RejectNegative Mask(NO_SPACE_REGS) Disable space regs. mordered -Target Report Var(TARGET_ORDERED) Init(0) +Target Var(TARGET_ORDERED) Init(0) Assume memory references are ordered and barriers are not needed. mpa-risc-1-0 @@ -111,7 +111,7 @@ Target RejectNegative Mask(PA_20) Generate PA2.0 code (requires binutils 2.10 or later). mportable-runtime -Target Report Mask(PORTABLE_RUNTIME) +Target Mask(PORTABLE_RUNTIME) Use portable calling conventions. mschedule= @@ -140,7 +140,7 @@ EnumValue Enum(pa_schedule) String(7300) Value(PROCESSOR_7300) msoft-float -Target Report Mask(SOFT_FLOAT) +Target Mask(SOFT_FLOAT) Use software floating point. msnake @@ -148,5 +148,5 @@ Target RejectNegative Generate PA1.1 code. mspace-regs -Target RejectNegative Report InverseMask(NO_SPACE_REGS) +Target RejectNegative InverseMask(NO_SPACE_REGS) Do not disable space regs. diff --git a/gcc/config/pa/pa32-linux.h b/gcc/config/pa/pa32-linux.h index 970722a..c970006 100644 --- a/gcc/config/pa/pa32-linux.h +++ b/gcc/config/pa/pa32-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF-32 format - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa32-netbsd.h b/gcc/config/pa/pa32-netbsd.h index 0903de2..aa075a6 100644 --- a/gcc/config/pa/pa32-netbsd.h +++ b/gcc/config/pa/pa32-netbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF-32 format - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa32-openbsd.h b/gcc/config/pa/pa32-openbsd.h index 74cfdd9..2bdd0a5 100644 --- a/gcc/config/pa/pa32-openbsd.h +++ b/gcc/config/pa/pa32-openbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF-32 format - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index a5e8dfe..3fb631e 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2000-2020 Free Software Foundation, Inc. +/* Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-hpux.h b/gcc/config/pa/pa64-hpux.h index 096aa4b..c25bc38 100644 --- a/gcc/config/pa/pa64-hpux.h +++ b/gcc/config/pa/pa64-hpux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for HPs running HPUX using the 64bit runtime model. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-hpux.opt b/gcc/config/pa/pa64-hpux.opt index 3cb5027..97ee79a 100644 --- a/gcc/config/pa/pa64-hpux.opt +++ b/gcc/config/pa/pa64-hpux.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa64-linux.h b/gcc/config/pa/pa64-linux.h index 1e3d52f..fd2e23c 100644 --- a/gcc/config/pa/pa64-linux.h +++ b/gcc/config/pa/pa64-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format on 64-bit Linux - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 107d703..2737eef 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -1,5 +1,5 @@ /* Configuration for GCC-compiler for PA-RISC. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md index 42a236c..71a6f5b 100644 --- a/gcc/config/pa/predicates.md +++ b/gcc/config/pa/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for HP PA-RISC. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/pa/som.h b/gcc/config/pa/som.h index 81aee86..d25a2ed 100644 --- a/gcc/config/pa/som.h +++ b/gcc/config/pa/som.h @@ -1,5 +1,5 @@ /* Definitions for SOM assembler support. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pdp11/constraints.md b/gcc/config/pdp11/constraints.md index 2f3a59a..f87fe18 100644 --- a/gcc/config/pdp11/constraints.md +++ b/gcc/config/pdp11/constraints.md @@ -1,5 +1,5 @@ ;;- Constraint definitions for the pdp11 for GNU C compiler -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11-modes.def b/gcc/config/pdp11/pdp11-modes.def index 65a8802..8997ef6 100644 --- a/gcc/config/pdp11/pdp11-modes.def +++ b/gcc/config/pdp11/pdp11-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11-protos.h b/gcc/config/pdp11/pdp11-protos.h index 855ec756..fcdf4b1 100644 --- a/gcc/config/pdp11/pdp11-protos.h +++ b/gcc/config/pdp11/pdp11-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 25590be..bd6e0dc 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -1,5 +1,5 @@ /* Subroutines for gcc2 for pdp11. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index aedeb73..a21ae64 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index cdef49f..2a12c97 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -1,5 +1,5 @@ ;;- Machine description for the pdp11 for GNU C compiler -;; Copyright (C) 1994-2020 Free Software Foundation, Inc. +;; Copyright (C) 1994-2021 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. @@ -82,6 +82,8 @@ (define_code_iterator SHF [ashift ashiftrt lshiftrt]) +(define_mode_iterator PDPfp [SF DF]) + ;; Substitution to turn a CC clobber into a CC setter. We have four of ;; these: for CCmode vs. CCNZmode, and for CC_REGNUM vs. FCC_REGNUM. (define_subst "cc_cc" @@ -101,19 +103,19 @@ (set (match_dup 0) (match_dup 1))]) (define_subst "fcc_cc" - [(set (match_operand 0 "") (match_operand 1 "")) + [(set (match_operand:PDPfp 0 "") (match_operand:PDPfp 1 "")) (clobber (reg FCC_REGNUM))] "" [(set (reg:CC FCC_REGNUM) - (compare:CC (match_dup 1) (const_double_zero))) + (compare:CC (match_dup 1) (const_double_zero:PDPfp))) (set (match_dup 0) (match_dup 1))]) (define_subst "fcc_ccnz" - [(set (match_operand 0 "") (match_operand 1 "")) + [(set (match_operand:PDPfp 0 "") (match_operand:PDPfp 1 "")) (clobber (reg FCC_REGNUM))] "" [(set (reg:CCNZ FCC_REGNUM) - (compare:CCNZ (match_dup 1) (const_double_zero))) + (compare:CCNZ (match_dup 1) (const_double_zero:PDPfp))) (set (match_dup 0) (match_dup 1))]) (define_subst_attr "cc_cc" "cc_cc" "_nocc" "_cc") diff --git a/gcc/config/pdp11/pdp11.opt b/gcc/config/pdp11/pdp11.opt index 66095a5..522c311 100644 --- a/gcc/config/pdp11/pdp11.opt +++ b/gcc/config/pdp11/pdp11.opt @@ -1,6 +1,6 @@ ; Options for the PDP11 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -23,49 +23,49 @@ Target RejectNegative Generate code for an 11/10. m40 -Target Report Mask(40) +Target Mask(40) Generate code for an 11/40. m45 -Target Report Mask(45) +Target Mask(45) Generate code for an 11/45. mac0 -Target Report Mask(AC0) +Target Mask(AC0) Return floating-point results in ac0 (fr0 in Unix assembler syntax). mdec-asm -Target RejectNegative Report Mask(DEC_ASM) Negative(mgnu-asm) +Target RejectNegative Mask(DEC_ASM) Negative(mgnu-asm) Use the DEC assembler syntax. mgnu-asm -Target RejectNegative Report Mask(GNU_ASM) Negative(munix-asm) +Target RejectNegative Mask(GNU_ASM) Negative(munix-asm) Use the GNU assembler syntax. mfpu -Target RejectNegative Report Mask(FPU) +Target RejectNegative Mask(FPU) Use hardware floating point. mint16 -Target Report InverseMask(INT32, INT16) +Target InverseMask(INT32, INT16) Use 16 bit int. mint32 -Target Report Mask(INT32) +Target Mask(INT32) Use 32 bit int. msoft-float -Target RejectNegative Report InverseMask(FPU, SOFT_FLOAT) +Target RejectNegative InverseMask(FPU, SOFT_FLOAT) Do not use hardware floating point. msplit -Target Report Mask(SPLIT) +Target Mask(SPLIT) Target has split I&D. munix-asm -Target RejectNegative Report Mask(UNIX_ASM) Negative(mdec-asm) +Target RejectNegative Mask(UNIX_ASM) Negative(mdec-asm) Use UNIX assembler syntax. mlra -Target Report Mask(LRA) +Target Mask(LRA) Use LRA register allocator. diff --git a/gcc/config/pdp11/predicates.md b/gcc/config/pdp11/predicates.md index 1eb18ed..761479a 100644 --- a/gcc/config/pdp11/predicates.md +++ b/gcc/config/pdp11/predicates.md @@ -1,5 +1,5 @@ ;;- Predicate definitions for the pdp11 for GNU C compiler -;; Copyright (C) 1994-2020 Free Software Foundation, Inc. +;; Copyright (C) 1994-2021 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. diff --git a/gcc/config/pdp11/t-pdp11 b/gcc/config/pdp11/t-pdp11 index bdd8d70..90866c2 100644 --- a/gcc/config/pdp11/t-pdp11 +++ b/gcc/config/pdp11/t-pdp11 @@ -1,4 +1,4 @@ -# Copyright (C) 1995-2020 Free Software Foundation, Inc. +# Copyright (C) 1995-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/phoenix.h b/gcc/config/phoenix.h index c05d8f0..aed4fbf 100644 --- a/gcc/config/phoenix.h +++ b/gcc/config/phoenix.h @@ -1,5 +1,5 @@ /* Base configuration file for all Phoenix-RTOS targets. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/print-sysroot-suffix.sh b/gcc/config/print-sysroot-suffix.sh index bb1efc8..50a7b16 100644 --- a/gcc/config/print-sysroot-suffix.sh +++ b/gcc/config/print-sysroot-suffix.sh @@ -3,7 +3,7 @@ # Arguments are MULTILIB_OSDIRNAMES, MULTILIB_OPTIONS, MULTILIB_MATCHES, # and MULTILIB_REUSE. -# Copyright (C) 2009-2020 Free Software Foundation, Inc. +# Copyright (C) 2009-2021 Free Software Foundation, Inc. # This file is part of GCC. diff --git a/gcc/config/pru/alu-zext.md b/gcc/config/pru/alu-zext.md index 35a6dbd..f3ff6be 100644 --- a/gcc/config/pru/alu-zext.md +++ b/gcc/config/pru/alu-zext.md @@ -1,6 +1,6 @@ ;; ALU operations with zero extensions ;; -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by Dimitar Dimitrov <dimitar@dinux.eu> ;; ;; This file is part of GCC. diff --git a/gcc/config/pru/constraints.md b/gcc/config/pru/constraints.md index ad8192b..a31ae93 100644 --- a/gcc/config/pru/constraints.md +++ b/gcc/config/pru/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for TI PRU. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by Dimitar Dimitrov <dimitar@dinux.eu> ;; ;; This file is part of GCC. diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md index 1eb95d0..469002f 100644 --- a/gcc/config/pru/predicates.md +++ b/gcc/config/pru/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for TI PRU. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by Dimitar Dimitrov <dimitar@dinux.eu> ;; ;; This file is part of GCC. diff --git a/gcc/config/pru/pru-opts.h b/gcc/config/pru/pru-opts.h index 4a7936e..b7285aa 100644 --- a/gcc/config/pru/pru-opts.h +++ b/gcc/config/pru/pru-opts.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2017-2020 Free Software Foundation, Inc. +/* Copyright (C) 2017-2021 Free Software Foundation, Inc. Contributed by Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru-passes.c b/gcc/config/pru/pru-passes.c index 747b4c8..10079e3 100644 --- a/gcc/config/pru/pru-passes.c +++ b/gcc/config/pru/pru-passes.c @@ -1,5 +1,5 @@ /* PRU target specific passes - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru-pragma.c b/gcc/config/pru/pru-pragma.c index 5d6cc49..01d0761 100644 --- a/gcc/config/pru/pru-pragma.c +++ b/gcc/config/pru/pru-pragma.c @@ -1,5 +1,5 @@ /* PRU target specific pragmas - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru-protos.h b/gcc/config/pru/pru-protos.h index 6610ac9..74129e9 100644 --- a/gcc/config/pru/pru-protos.h +++ b/gcc/config/pru/pru-protos.h @@ -1,5 +1,5 @@ /* Subroutine declarations for TI PRU target support. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c index 65ad687..30d0da1 100644 --- a/gcc/config/pru/pru.c +++ b/gcc/config/pru/pru.c @@ -1,5 +1,5 @@ /* Target machine subroutines for TI PRU. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru.h b/gcc/config/pru/pru.h index 7f217fe..4c35a7d 100644 --- a/gcc/config/pru/pru.h +++ b/gcc/config/pru/pru.h @@ -1,5 +1,5 @@ /* Definitions of target machine for TI PRU. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. Contributed by Dimitar Dimitrov <dimitar@dinux.eu> This file is part of GCC. diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md index 125444c..e6cfa8e 100644 --- a/gcc/config/pru/pru.md +++ b/gcc/config/pru/pru.md @@ -1,5 +1,5 @@ ;; Machine Description for TI PRU. -;; Copyright (C) 2014-2020 Free Software Foundation, Inc. +;; Copyright (C) 2014-2021 Free Software Foundation, Inc. ;; Contributed by Dimitar Dimitrov <dimitar@dinux.eu> ;; Based on the NIOS2 GCC port. ;; diff --git a/gcc/config/pru/pru.opt b/gcc/config/pru/pru.opt index 5fe716d..d25cd92 100644 --- a/gcc/config/pru/pru.opt +++ b/gcc/config/pru/pru.opt @@ -1,5 +1,5 @@ ; Options for the TI PRU port of the compiler. -; Copyright (C) 2018-2020 Free Software Foundation, Inc. +; Copyright (C) 2018-2021 Free Software Foundation, Inc. ; Contributed by Dimitar Dimitrov <dimitar@dinux.eu> ; ; This file is part of GCC. @@ -22,7 +22,7 @@ HeaderInclude config/pru/pru-opts.h minrt -Target Report Mask(MINRT) RejectNegative +Target Mask(MINRT) RejectNegative Use a minimum runtime (no static initializers or ctors) for memory-constrained devices. @@ -31,7 +31,7 @@ Target RejectNegative Joined -mmcu=MCU Select the target System-On-Chip variant that embeds this PRU. mno-relax -Target Report RejectNegative +Target RejectNegative Make GCC pass the --no-relax command-line option to the linker instead of the --relax option. @@ -40,7 +40,7 @@ Target Mask(OPT_LOOP) Allow (or do not allow) gcc to use the LOOP instruction. mabi= -Target RejectNegative Report Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save +Target RejectNegative Joined Enum(pru_abi_t) Var(pru_current_abi) Init(PRU_ABI_GNU) Save Select target ABI variant. Enum diff --git a/gcc/config/pru/t-pru b/gcc/config/pru/t-pru index 3fe3371..d0ad8b2 100644 --- a/gcc/config/pru/t-pru +++ b/gcc/config/pru/t-pru @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the TI PRU target. -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # Contributed by Dimitar Dimitrov <dimitar.dinux.eu> # Based on the t-nios2 # diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 2b4289e..ea95a06 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -1,7 +1,7 @@ #!/usr/bin/env python # Tool for canonical RISC-V architecture string. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # Contributed by Andrew Waterman (andrew@sifive.com). # # This file is part of GCC. @@ -74,8 +74,20 @@ def arch_canonicalize(arch): # becasue we just append extensions list to the arch string. std_exts += list(filter(lambda x:len(x) == 1, long_exts)) + def longext_sort (exts): + if not exts.startswith("zxm") and exts.startswith("z"): + # If "Z" extensions are named, they should be ordered first by CANONICAL. + if exts[1] not in CANONICAL_ORDER: + raise Exception("Unsupported extension `%s`" % exts) + canonical_sort = CANONICAL_ORDER.index(exts[1]) + else: + canonical_sort = -1 + return (exts.startswith("x"), exts.startswith("zxm"), + LONG_EXT_PREFIXES.index(exts[0]), canonical_sort, exts[1:]) + # Multi-letter extension must be in lexicographic order. - long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts))) + long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts), + key=longext_sort)) # Put extensions in canonical order. for ext in CANONICAL_ORDER: diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index ef9c81e..8c15c6c 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for RISC-V target. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; Based on MIPS target for GNU compiler. ;; diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h index 4e2d646..d136d46 100644 --- a/gcc/config/riscv/elf.h +++ b/gcc/config/riscv/elf.h @@ -1,5 +1,5 @@ /* Target macros for riscv*-elf targets. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h index f7997e4..a48bf9b 100644 --- a/gcc/config/riscv/freebsd.h +++ b/gcc/config/riscv/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for RISC-V FreeBSD systems with ELF format. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index c70aa7c..10d8824 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -1,5 +1,5 @@ ;; Generic DFA-based pipeline description for RISC-V targets. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h index 4afef7c..9238de5 100644 --- a/gcc/config/riscv/linux.h +++ b/gcc/config/riscv/linux.h @@ -1,5 +1,5 @@ /* Definitions for RISC-V GNU/Linux systems with ELF format. - Copyright (C) 1998-2020 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/multilib-generator b/gcc/config/riscv/multilib-generator index 53c51df..a204543 100755 --- a/gcc/config/riscv/multilib-generator +++ b/gcc/config/riscv/multilib-generator @@ -1,7 +1,7 @@ #!/usr/bin/env python # RISC-V multilib list generator. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # Contributed by Andrew Waterman (andrew@sifive.com). # # This file is part of GCC. @@ -54,9 +54,10 @@ def arch_canonicalize(arch): this_file = os.path.abspath(os.path.join( __file__)) arch_can_script = \ os.path.join(os.path.dirname(this_file), "arch-canonicalize") - proc = subprocess.Popen([arch_can_script, arch], stdout=subprocess.PIPE) + proc = subprocess.Popen([sys.executable, arch_can_script, arch], + stdout=subprocess.PIPE) out, err = proc.communicate() - return out.strip() + return out.decode().strip() # # Handle expansion operation. @@ -67,15 +68,15 @@ def arch_canonicalize(arch): def _expand_combination(ext): exts = list(ext.split("*")) - # No need to expand if there is no `*`. - if len(exts) == 1: - return [(exts[0],)] - # Add underline to every extension. # e.g. # _b * zvamo => _b * _zvamo exts = list(map(lambda x: '_' + x, exts)) + # No need to expand if there is no `*`. + if len(exts) == 1: + return [(exts[0],)] + # Generate combination! ext_combs = [] for comb_len in range(1, len(exts)+1): @@ -146,7 +147,9 @@ for cfg in sys.argv[1:]: # Drop duplicated entry. alts = unique(alts) - for alt in alts[1:]: + for alt in alts: + if alt == arch: + continue arches[alt] = 1 reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi)) required.append('march=%s/mabi=%s' % (arch, abi)) diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md index b69ed8c..aacd7fb8 100644 --- a/gcc/config/riscv/peephole.md +++ b/gcc/config/riscv/peephole.md @@ -1,5 +1,5 @@ ;; Peephole optimizations for RISC-V for GNU compiler. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; This file is part of GCC. diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index ae2ec57..fc190c8 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -1,5 +1,5 @@ ;; PIC codegen for RISC-V for GNU compiler. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; This file is part of GCC. diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index f764fe7..ef821ad 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -1,5 +1,5 @@ ;; Predicate description for RISC-V target. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; Based on MIPS target for GNU compiler. ;; diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c index bc95938..97b1480 100644 --- a/gcc/config/riscv/riscv-builtins.c +++ b/gcc/config/riscv/riscv-builtins.c @@ -1,5 +1,5 @@ /* Subroutines used for expanding RISC-V builtins. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). This file is part of GCC. diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c index c600badb..efd4a61 100644 --- a/gcc/config/riscv/riscv-c.c +++ b/gcc/config/riscv/riscv-c.c @@ -1,5 +1,5 @@ /* RISC-V-specific code for C family languages. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). This file is part of GCC. @@ -20,12 +20,14 @@ along with GCC; see the file COPYING3. If not see #define IN_TARGET_CODE 1 +#define INCLUDE_STRING #include "config.h" #include "system.h" #include "coretypes.h" #include "tm.h" #include "c-family/c-common.h" #include "cpplib.h" +#include "riscv-subset.h" #define builtin_define(TXT) cpp_define (pfile, TXT) @@ -101,4 +103,34 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) break; } + + /* Define architecture extension test macros. */ + builtin_define_with_int_value ("__riscv_arch_test", 1); + + const riscv_subset_list *subset_list = riscv_current_subset_list (); + size_t max_ext_len = 0; + + /* Figure out the max length of extension name for reserving buffer. */ + for (const riscv_subset_t *subset = subset_list->begin (); + subset != subset_list->end (); + subset = subset->next) + max_ext_len = MAX (max_ext_len, subset->name.length ()); + + char *buf = (char *)alloca (max_ext_len + 10 /* For __riscv_ and '\0'. */); + + for (const riscv_subset_t *subset = subset_list->begin (); + subset != subset_list->end (); + subset = subset->next) + { + int version_value = (subset->major_version * 1000000) + + (subset->minor_version * 1000); + /* Special rule for zicsr and zifencei, it's used for ISA spec 2.2 or + earlier. */ + if ((subset->name == "zicsr" || subset->name == "zifencei") + && version_value == 0) + version_value = 2000000; + + sprintf (buf, "__riscv_%s", subset->name.c_str ()); + builtin_define_with_int_value (buf, version_value); + } } diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 6a13f3e..bf5aaba 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -1,5 +1,5 @@ /* List of supported core and tune info for RISC-V. - Copyright (C) 2020 Free Software Foundation, Inc. + Copyright (C) 2020-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/riscv-d.c b/gcc/config/riscv/riscv-d.c index 0fb08b4..2b690b1 100644 --- a/gcc/config/riscv/riscv-d.c +++ b/gcc/config/riscv/riscv-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the RISC-V architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 1c6bc4e..b19b731 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -1,5 +1,5 @@ /* Definitions of prototypes for RISC-V built-in functions. -*- C -*- - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index d66c198..0c87e06 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -1,5 +1,5 @@ /* Extra machine modes for RISC-V target. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 0b83f17..f4cf6ca 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -1,5 +1,5 @@ /* Definition of RISC-V target for GNU compiler. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). This file is part of GCC. diff --git a/gcc/config/riscv/riscv-passes.def b/gcc/config/riscv/riscv-passes.def index 8a4ea09..9dc05ac 100644 --- a/gcc/config/riscv/riscv-passes.def +++ b/gcc/config/riscv/riscv-passes.def @@ -1,5 +1,5 @@ /* Declaration of target-specific passes for RISC-V. - Copyright (C) 2019 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 256dab1..cc0be7e 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -1,5 +1,5 @@ /* Definition of RISC-V target for GNU compiler. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv-shorten-memrefs.c b/gcc/config/riscv/riscv-shorten-memrefs.c index 3686005..b1b57f1 100644 --- a/gcc/config/riscv/riscv-shorten-memrefs.c +++ b/gcc/config/riscv/riscv-shorten-memrefs.c @@ -1,5 +1,5 @@ /* Shorten memrefs pass for RISC-V. - Copyright (C) 2018-2019 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h new file mode 100644 index 0000000..793655a --- /dev/null +++ b/gcc/config/riscv/riscv-subset.h @@ -0,0 +1,95 @@ +/* Definition of data structure of RISC-V subset for GNU compiler. + Copyright (C) 2011-2021 Free Software Foundation, Inc. + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target for GNU compiler. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#ifndef GCC_RISCV_SUBSET_H +#define GCC_RISCV_SUBSET_H + +#define RISCV_DONT_CARE_VERSION -1 + +/* Subset info. */ +struct riscv_subset_t +{ + riscv_subset_t (); + + std::string name; + int major_version; + int minor_version; + struct riscv_subset_t *next; + + bool explicit_version_p; + bool implied_p; +}; + +/* Subset list. */ +class riscv_subset_list +{ +private: + /* Original arch string. */ + const char *m_arch; + + /* Location of arch string, used for report error. */ + location_t m_loc; + + /* Head of subset info list. */ + riscv_subset_t *m_head; + + /* Tail of subset info list. */ + riscv_subset_t *m_tail; + + /* X-len of m_arch. */ + unsigned m_xlen; + + riscv_subset_list (const char *, location_t); + + const char *parsing_subset_version (const char *, const char *, unsigned *, + unsigned *, bool, bool *); + + const char *parse_std_ext (const char *); + + const char *parse_multiletter_ext (const char *, const char *, + const char *); + + void handle_implied_ext (riscv_subset_t *); + +public: + ~riscv_subset_list (); + + void add (const char *, int, int, bool, bool); + + void add (const char *, bool); + + riscv_subset_t *lookup (const char *, + int major_version = RISCV_DONT_CARE_VERSION, + int minor_version = RISCV_DONT_CARE_VERSION) const; + + std::string to_string (bool) const; + + unsigned xlen () const {return m_xlen;}; + + static riscv_subset_list *parse (const char *, location_t); + + const riscv_subset_t *begin () const {return m_head;}; + const riscv_subset_t *end () const {return NULL;}; +}; + +extern const riscv_subset_list *riscv_current_subset_list (void); + +#endif /* ! GCC_RISCV_SUBSET_H */ diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 9b83da0..ff41795 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation for RISC-V. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index df3003f..c6f8bee 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1,5 +1,5 @@ /* Definition of RISC-V target for GNU compiler. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Andrew Waterman (andrew@sifive.com). Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 254147c..fcdcc3a 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1,5 +1,5 @@ ;; Machine description for RISC-V for GNU compiler. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9cf14bb..761a09d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -1,6 +1,6 @@ ; Options for the RISC-V port of the compiler ; -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -26,11 +26,11 @@ Target RejectNegative Joined UInteger Var(riscv_branch_cost) -mbranch-cost=N Set the cost of branches to roughly N instructions. mplt -Target Report Var(TARGET_PLT) Init(1) +Target Var(TARGET_PLT) Init(1) When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. mabi= -Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) +Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Specify integer and floating-point calling convention. mpreferred-stack-boundary= @@ -63,15 +63,15 @@ EnumValue Enum(abi_type) String(lp64d) Value(ABI_LP64D) mfdiv -Target Report Mask(FDIV) +Target Mask(FDIV) Use hardware floating-point divide and square root instructions. mdiv -Target Report Mask(DIV) +Target Mask(DIV) Use hardware instructions for integer division. march= -Target Report RejectNegative Joined +Target RejectNegative Joined -march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be lower-case. @@ -88,7 +88,7 @@ Target Joined Separate UInteger Var(g_switch_value) Init(8) -msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets). msave-restore -Target Report Mask(SAVE_RESTORE) +Target Mask(SAVE_RESTORE) Use smaller but slower prologue and epilogue code. mshorten-memrefs @@ -98,11 +98,11 @@ memory accesses to be generated as compressed instructions. Currently targets 32-bit integer load/stores. mcmodel= -Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) +Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) Specify the code model. mstrict-align -Target Report Mask(STRICT_ALIGN) Save +Target Mask(STRICT_ALIGN) Save Do not generate unaligned memory accesses. Enum @@ -116,7 +116,7 @@ EnumValue Enum(code_model) String(medany) Value(CM_MEDANY) mexplicit-relocs -Target Report Mask(EXPLICIT_RELOCS) +Target Mask(EXPLICIT_RELOCS) Use %reloc() operators, rather than assembly macros, to load addresses. mrelax @@ -139,7 +139,7 @@ Mask(RVC) Mask(RVE) mriscv-attribute -Target Report Var(riscv_emit_attribute_p) Init(-1) +Target Var(riscv_emit_attribute_p) Init(-1) Emit RISC-V ELF attribute. malign-data= @@ -201,5 +201,5 @@ EnumValue Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) misa-spec= -Target Report RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) +Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) Set the version of RISC-V ISA spec. diff --git a/gcc/config/riscv/rtems.h b/gcc/config/riscv/rtems.h index d222ab7..5b3719c 100644 --- a/gcc/config/riscv/rtems.h +++ b/gcc/config/riscv/rtems.h @@ -1,5 +1,5 @@ /* Definitions for RISC-V RTEMS systems with ELF format. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 8e64fc0..747a799 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -1,5 +1,5 @@ ;; Machine description for RISC-V atomic operations. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Andrew Waterman (andrew@sifive.com). ;; Based on MIPS target for GNU compiler. diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 702767c..1215ea8 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -25,4 +25,6 @@ riscv-shorten-memrefs.o: $(srcdir)/config/riscv/riscv-shorten-memrefs.c PASSES_EXTRA += $(srcdir)/config/riscv/riscv-passes.def -$(common_out_file): $(srcdir)/config/riscv/riscv-cores.def +$(common_out_file): $(srcdir)/config/riscv/riscv-cores.def \ + $(srcdir)/config/riscv/riscv-protos.h \ + $(srcdir)/config/riscv/riscv-subset.h diff --git a/gcc/config/rl78/constraints.md b/gcc/config/rl78/constraints.md index 7ce5a72..b63aa31 100644 --- a/gcc/config/rl78/constraints.md +++ b/gcc/config/rl78/constraints.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/predicates.md b/gcc/config/rl78/predicates.md index 72cf70a..5483855 100644 --- a/gcc/config/rl78/predicates.md +++ b/gcc/config/rl78/predicates.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-c.c b/gcc/config/rl78/rl78-c.c index cf27002..ee90b22 100644 --- a/gcc/config/rl78/rl78-c.c +++ b/gcc/config/rl78/rl78-c.c @@ -1,5 +1,5 @@ /* RL78 C-specific support - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md index 739855e..0942de1 100644 --- a/gcc/config/rl78/rl78-expand.md +++ b/gcc/config/rl78/rl78-expand.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-opts.h b/gcc/config/rl78/rl78-opts.h index 6c9e0b3..e2f4532 100644 --- a/gcc/config/rl78/rl78-opts.h +++ b/gcc/config/rl78/rl78-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the Renesas RL78 processor. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-protos.h b/gcc/config/rl78/rl78-protos.h index 7c94c90..d26586d 100644 --- a/gcc/config/rl78/rl78-protos.h +++ b/gcc/config/rl78/rl78-protos.h @@ -1,5 +1,5 @@ /* Prototypes for Renesas RL78 processors - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md index 7dd8650..afbf354 100644 --- a/gcc/config/rl78/rl78-real.md +++ b/gcc/config/rl78/rl78-real.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-virt.md b/gcc/config/rl78/rl78-virt.md index f755d2b..48fb115 100644 --- a/gcc/config/rl78/rl78-virt.md +++ b/gcc/config/rl78/rl78-virt.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c index 71f67b7..f275cd3 100644 --- a/gcc/config/rl78/rl78.c +++ b/gcc/config/rl78/rl78.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Renesas RL78 processors. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h index 8f9a51c..2a3649c 100644 --- a/gcc/config/rl78/rl78.h +++ b/gcc/config/rl78/rl78.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the Renesas RL78 processor. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md index eff0c74..7cf695b 100644 --- a/gcc/config/rl78/rl78.md +++ b/gcc/config/rl78/rl78.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78.opt b/gcc/config/rl78/rl78.opt index 489697b..0dc552c 100644 --- a/gcc/config/rl78/rl78.opt +++ b/gcc/config/rl78/rl78.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RL78 port of GCC. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. @@ -23,11 +23,11 @@ HeaderInclude config/rl78/rl78-opts.h msim -Target Report +Target Use the simulator runtime. mmul= -Target RejectNegative Joined Var(rl78_mul_type) Report Tolower Enum(rl78_mul_types) Init(MUL_UNINIT) +Target RejectNegative Joined Var(rl78_mul_type) Tolower Enum(rl78_mul_types) Init(MUL_UNINIT) Selects the type of hardware multiplication and division to use (none/g13/g14). Enum @@ -46,15 +46,15 @@ EnumValue Enum(rl78_mul_types) String(rl78) Value(MUL_G14) mallregs -Target Mask(ALLREGS) Report Optimization +Target Mask(ALLREGS) Optimization Use all registers, reserving none for interrupt handlers. mrelax -Target Report Optimization +Target Optimization Enable assembler and linker relaxation. Enabled by default at -Os. mcpu= -Target RejectNegative Joined Var(rl78_cpu_type) Report ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT) +Target RejectNegative Joined Var(rl78_cpu_type) ToLower Enum(rl78_cpu_types) Init(CPU_UNINIT) Selects the type of RL78 core being targeted (g10/g13/g14). The default is the G14. If set, also selects the hardware multiply support to be used. Enum @@ -73,19 +73,19 @@ EnumValue Enum(rl78_cpu_types) String(rl78) Value(CPU_G14) mg10 -Target RejectNegative Report Alias(mcpu=, g10) +Target RejectNegative Alias(mcpu=, g10) Alias for -mcpu=g10. mg13 -Target RejectNegative Report Alias(mcpu=, g13) +Target RejectNegative Alias(mcpu=, g13) Alias for -mcpu=g13. mg14 -Target RejectNegative Report Alias(mcpu=, g14) +Target RejectNegative Alias(mcpu=, g14) Alias for -mcpu=g14. mrl78 -Target RejectNegative Report Alias(mcpu=, g14) +Target RejectNegative Alias(mcpu=, g14) Alias for -mcpu=g14. mes0 diff --git a/gcc/config/rl78/t-rl78 b/gcc/config/rl78/t-rl78 index a320ef9..ebcfa4c 100644 --- a/gcc/config/rl78/t-rl78 +++ b/gcc/config/rl78/t-rl78 @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the Renesas RL78 target. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/rpath.opt b/gcc/config/rpath.opt index 6e80c15..c107ae6 100644 --- a/gcc/config/rpath.opt +++ b/gcc/config/rpath.opt @@ -1,6 +1,6 @@ ; -rpath option to the driver. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 2b89b42..a7ade34 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 0334e99..74262d0 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 440 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/476.h b/gcc/config/rs6000/476.h index f6622f9..9c1b116 100644 --- a/gcc/config/rs6000/476.h +++ b/gcc/config/rs6000/476.h @@ -1,5 +1,5 @@ /* Enable IBM PowerPC 476 support. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Peter Bergner (bergner@vnet.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index aa3a6c8..a55495d 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 476 processor. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Peter Bergner (bergner@vnet.ibm.com). ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/476.opt b/gcc/config/rs6000/476.opt index f073a0d..d3c074d 100644 --- a/gcc/config/rs6000/476.opt +++ b/gcc/config/rs6000/476.opt @@ -1,6 +1,6 @@ ; IBM PowerPC 476 options. ; -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; Contributed by Peter Bergner (bergner@vnet.ibm.com) ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index 63baffe..1e10b9a 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC 601 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index f24b511..8b5aa0a 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC 603 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 38722fd..457e014 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -1,6 +1,6 @@ ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, ;; and PowerPC 630 processors. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index fdebd0a..1034680 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 7450 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index c186591..74ecf12 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index 482956d..c68c2a9 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC 8540 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md index 25550ca..22529e3 100644 --- a/gcc/config/rs6000/a2.md +++ b/gcc/config/rs6000/a2.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC A2 processors. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Ben Elliston (bje@au.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/rs6000/aix-stdint.h b/gcc/config/rs6000/aix-stdint.h index d356d9a..c89b5e7 100644 --- a/gcc/config/rs6000/aix-stdint.h +++ b/gcc/config/rs6000/aix-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using AIX. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index edd6fdb..5e8743a 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h index 5b652d7..78c179b 100644 --- a/gcc/config/rs6000/aix61.h +++ b/gcc/config/rs6000/aix61.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V6.1. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix64.opt b/gcc/config/rs6000/aix64.opt index 48135ce..7673c91 100644 --- a/gcc/config/rs6000/aix64.opt +++ b/gcc/config/rs6000/aix64.opt @@ -1,6 +1,6 @@ ; Options for the 64-bit flavor of AIX. ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) +Target RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers. maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) +Target RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers. mcmodel= @@ -45,7 +45,7 @@ EnumValue Enum(rs6000_cmodel) String(large) Value(CMODEL_LARGE) mpe -Target Report RejectNegative Var(internal_nothing_1) Save +Target RejectNegative Var(internal_nothing_1) Save Support message passing with the Parallel Environment. posix diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 8b12a2d..3612ed2 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V7.1. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. @@ -62,6 +62,9 @@ do { \ /* aix/ppc doesn't support -mvsx and -maltivec with Go */ \ rs6000_isa_flags &= ~(OPTION_MASK_VSX | OPTION_MASK_ALTIVEC); \ } \ + if (!global_options_set.x_dwarf_version) \ + /* AIX only supports DWARF 4. */ \ + dwarf_version = 4; \ } while (0) #define ASM_SPEC32 "-a32" diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index 121420b..d349092 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V7.2. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. @@ -62,6 +62,9 @@ do { \ /* aix/ppc doesn't support -mvsx and -maltivec with Go */ \ rs6000_isa_flags &= ~(OPTION_MASK_VSX | OPTION_MASK_ALTIVEC); \ } \ + if (!global_options_set.x_dwarf_version) \ + /* AIX only supports DWARF 4. */ \ + dwarf_version = 4; \ } while (0) #define ASM_SPEC32 "-a32" diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index e1884f5..961621a 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -1,5 +1,5 @@ /* PowerPC AltiVec include file. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). Rewritten by Paolo Bonzini (bonzini@gnu.org). @@ -750,6 +750,10 @@ __altivec_scalar_pred(vec_any_nle, #define vec_strir_p(a) __builtin_vec_strir_p (a) #define vec_stril_p(a) __builtin_vec_stril_p (a) +#define vec_mulh(a, b) __builtin_vec_mulh ((a), (b)) +#define vec_dive(a, b) __builtin_vec_dive ((a), (b)) +#define vec_mod(a, b) __builtin_vec_mod ((a), (b)) + /* VSX Mask Manipulation builtin. */ #define vec_genbm __builtin_vec_mtvsrbm #define vec_genhm __builtin_vec_mtvsrhm diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6a6ce0f..27a269b 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1,5 +1,5 @@ ;; AltiVec patterns. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) ;; This file is part of GCC. @@ -193,8 +193,6 @@ ;; Short vec int modes (define_mode_iterator VIshort [V8HI V16QI]) -;; Longer vec int modes for rotate/mask ops -(define_mode_iterator VIlong [V2DI V4SI]) ;; Vec float modes (define_mode_iterator VF [V4SF]) ;; Vec modes, pity mode iterators are not composable diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h index 3ccd579..7fe4249 100644 --- a/gcc/config/rs6000/amo.h +++ b/gcc/config/rs6000/amo.h @@ -1,5 +1,5 @@ /* Power ISA 3.0 atomic memory operation include file. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>. This file is part of GCC. diff --git a/gcc/config/rs6000/biarch64.h b/gcc/config/rs6000/biarch64.h index 7d4080f..08293d3 100644 --- a/gcc/config/rs6000/biarch64.h +++ b/gcc/config/rs6000/biarch64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for 32/64 bit powerpc. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/bmi2intrin.h b/gcc/config/rs6000/bmi2intrin.h index a167d27..5b7b761 100644 --- a/gcc/config/rs6000/bmi2intrin.h +++ b/gcc/config/rs6000/bmi2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/bmiintrin.h b/gcc/config/rs6000/bmiintrin.h index c2369e3..71220b7 100644 --- a/gcc/config/rs6000/bmiintrin.h +++ b/gcc/config/rs6000/bmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2020 Free Software Foundation, Inc. +/* Copyright (C) 2010-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 8465989..fbeda3b 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -1,5 +1,5 @@ ;; Scheduling description for cell processor. -;; Copyright (C) 2001-2020 Free Software Foundation, Inc. +;; Copyright (C) 2001-2021 Free Software Foundation, Inc. ;; Contributed by Sony Computer Entertainment, Inc., diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c600535..561ce97 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for RS6000 -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md index 6e2bb7d..569ce35 100644 --- a/gcc/config/rs6000/crypto.md +++ b/gcc/config/rs6000/crypto.md @@ -1,5 +1,5 @@ ;; Cryptographic instructions added in ISA 2.07 -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index ce27508..42f39e6 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for PowerPC running Darwin (Mac OS X). - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 05948c8..9375342 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -1,5 +1,5 @@ /* Machine description patterns for PowerPC running Darwin (Mac OS X). - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.opt b/gcc/config/rs6000/darwin.opt index 1b27a78..284eae3 100644 --- a/gcc/config/rs6000/darwin.opt +++ b/gcc/config/rs6000/darwin.opt @@ -1,6 +1,6 @@ ; Darwin options for PPC port. ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/darwin32-biarch.h b/gcc/config/rs6000/darwin32-biarch.h index f5e8835..0e9c9e1 100644 --- a/gcc/config/rs6000/darwin32-biarch.h +++ b/gcc/config/rs6000/darwin32-biarch.h @@ -1,6 +1,6 @@ /* Target definitions for PowerPC running Darwin (Mac OS X) for a 32b host with a 64b miultilib. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index ab19fa7..5a3b8e2 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -1,6 +1,6 @@ /* Target definitions for PowerPC64 running Darwin (Mac OS X) for a 64b host supporting a 32b multilib. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin7.h b/gcc/config/rs6000/darwin7.h index 765a3df..98eeb3b 100644 --- a/gcc/config/rs6000/darwin7.h +++ b/gcc/config/rs6000/darwin7.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin 7.x (Mac OS X) systems. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin8.h b/gcc/config/rs6000/darwin8.h deleted file mode 100644 index 01b2dc8..0000000 --- a/gcc/config/rs6000/darwin8.h +++ /dev/null @@ -1,21 +0,0 @@ -/* Target definitions for Darwin 8.0 and above (Mac OS X) systems. - Copyright (C) 2004-2020 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#undef DEF_MIN_OSX_VERSION -#define DEF_MIN_OSX_VERSION "10.4" diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index efed871..be014a6 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit powerpc linux defaulting to -m64. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 9a95230..c8cdb64 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -1,5 +1,5 @@ ;; Decimal Floating Point (DFP) patterns. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner ;; (bergner@vnet.ibm.com). diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c index 6b6439c..e23c445 100644 --- a/gcc/config/rs6000/driver-rs6000.c +++ b/gcc/config/rs6000/driver-rs6000.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index c19485f..33125dc 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC e300c3 core. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md index 306f621..fb00d17 100644 --- a/gcc/config/rs6000/e500mc.md +++ b/gcc/config/rs6000/e500mc.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC e500mc core. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md index 3d316b7..dc79d8b 100644 --- a/gcc/config/rs6000/e500mc64.md +++ b/gcc/config/rs6000/e500mc64.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e500mc64 core. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md index af93d7b..84da7f0 100644 --- a/gcc/config/rs6000/e5500.md +++ b/gcc/config/rs6000/e5500.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e5500 core. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index 1eeba7c..0aa2ac5 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e6500 core. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index b4e9dba..1106b39 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for IBM RS/6000 PowerPC targeted to embedded ELF systems. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index d52852a..af0ddc3 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for PowerPC targeted systems with AltiVec support. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/eabisim.h b/gcc/config/rs6000/eabisim.h index 14fd9ac..4cc6817 100644 --- a/gcc/config/rs6000/eabisim.h +++ b/gcc/config/rs6000/eabisim.h @@ -1,6 +1,6 @@ /* Support for GCC on simulated PowerPC systems targeted to embedded ELF systems. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h index b957c1b..ce1287e 100644 --- a/gcc/config/rs6000/emmintrin.h +++ b/gcc/config/rs6000/emmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/freebsd.h b/gcc/config/rs6000/freebsd.h index ca83caa..38311ad 100644 --- a/gcc/config/rs6000/freebsd.h +++ b/gcc/config/rs6000/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for PowerPC running FreeBSD using the ELF format - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index 6984ca5..11ea22e 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit PowerPC running FreeBSD using the ELF format - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -51,11 +51,10 @@ extern int dot_symbols; #define SET_CMODEL(opt) do {} while (0) #endif -/* Until now the 970 is the only Processor where FreeBSD 64-bit runs on. */ #undef PROCESSOR_DEFAULT -#define PROCESSOR_DEFAULT PROCESSOR_POWER4 +#define PROCESSOR_DEFAULT PROCESSOR_PPC7450 #undef PROCESSOR_DEFAULT64 -#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4 +#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8 /* We don't need to generate entries in .fixup, except when -mrelocatable or -mrelocatable-lib is given. */ @@ -100,8 +99,8 @@ extern int dot_symbols; #define ASM_SPEC64 "-a64" #define ASM_SPEC_COMMON "%(asm_cpu) \ -%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \ -%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian}" +%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \ + ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) #undef SUBSUBTARGET_EXTRA_SPECS #define SUBSUBTARGET_EXTRA_SPECS \ @@ -123,9 +122,15 @@ extern int dot_symbols; %{static:-Bstatic}} \ %{symbolic:-Bsymbolic}" +#undef DEFAULT_ASM_ENDIAN #define LINK_OS_FREEBSD_SPEC32 "-melf32ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF - +#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +#define DEFAULT_ASM_ENDIAN " -mlittle" +#define LINK_OS_FREEBSD_SPEC64 "-melf64lppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF +#else +#define DEFAULT_ASM_ENDIAN " -mbig" #define LINK_OS_FREEBSD_SPEC64 "-melf64ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF +#endif #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS { "m64" } diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md new file mode 100644 index 0000000..1ddbe7f --- /dev/null +++ b/gcc/config/rs6000/fusion.md @@ -0,0 +1,2533 @@ +;; -*- buffer-read-only: t -*- +;; Generated automatically by genfusion.pl + +;; Copyright (C) 2020 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is DI result mode is clobber compare mode is CC extend is none +(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:DI 1 "non_update_memory_operand" "m") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "ld%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is DI result mode is clobber compare mode is CCUNS extend is none +(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "m") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:DI 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "ld%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is DI result mode is DI compare mode is CC extend is none +(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:DI 1 "non_update_memory_operand" "m") + (match_operand:DI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "ld%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is DI result mode is DI compare mode is CCUNS extend is none +(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "m") + (match_operand:DI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "ld%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is clobber compare mode is CC extend is none +(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:SI 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwa%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is clobber compare mode is CCUNS extend is none +(define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:SI 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is SI compare mode is CC extend is none +(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwa%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is SI compare mode is CCUNS extend is none +(define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is EXTSI compare mode is CC extend is sign +(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwa%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))" + [(set (match_dup 0) (sign_extend:EXTSI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is SI result mode is EXTSI compare mode is CCUNS extend is zero +(define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") + (match_operand:SI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (zero_extend:EXTSI (match_dup 1)))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lwz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))" + [(set (match_dup 0) (zero_extend:EXTSI (match_dup 1))) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is HI result mode is clobber compare mode is CC extend is sign +(define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") + (match_operand:HI 3 "const_m1_to_1_operand" "n"))) + (clobber (match_scratch:GPR 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lha%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))" + [(set (match_dup 0) (sign_extend:GPR (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is HI result mode is clobber compare mode is CCUNS extend is zero +(define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") + (match_operand:HI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:GPR 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lhz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))" + [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is HI result mode is EXTHI compare mode is CC extend is sign +(define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign" + [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") + (match_operand:HI 3 "const_m1_to_1_operand" "n"))) + (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (sign_extend:EXTHI (match_dup 1)))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lha%X1 %0,%1\;cmpdi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))" + [(set (match_dup 0) (sign_extend:EXTHI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is HI result mode is EXTHI compare mode is CCUNS extend is zero +(define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") + (match_operand:HI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (zero_extend:EXTHI (match_dup 1)))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lhz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))" + [(set (match_dup 0) (zero_extend:EXTHI (match_dup 1))) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is QI result mode is clobber compare mode is CCUNS extend is zero +(define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") + (match_operand:QI 3 "const_0_to_1_operand" "n"))) + (clobber (match_scratch:GPR 0 "=r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lbz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), QImode, NON_PREFIXED_D))" + [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + +;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 +;; load mode is QI result mode is GPR compare mode is CCUNS extend is zero +(define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" + [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") + (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") + (match_operand:QI 3 "const_0_to_1_operand" "n"))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)" + "lbz%X1 %0,%1\;cmpldi 0,%0,%3" + "&& reload_completed + && (cc_reg_not_cr0_operand (operands[2], CCmode) + || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), QImode, NON_PREFIXED_D))" + [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) + (set (match_dup 2) + (compare:CCUNS (match_dup 0) + (match_dup 3)))] + "" + [(set_attr "type" "load") + (set_attr "cost" "8") + (set_attr "length" "8")]) + + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;and %3,%3,%2 + and %0,%1,%0\;and %0,%0,%2 + and %1,%1,%0\;and %1,%1,%2 + and %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;and %3,%3,%2 + andc %0,%1,%0\;and %0,%0,%2 + andc %1,%1,%0\;and %1,%1,%2 + andc %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;and %3,%3,%2 + eqv %0,%1,%0\;and %0,%0,%2 + eqv %1,%1,%0\;and %1,%1,%2 + eqv %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;and %3,%3,%2 + nand %0,%1,%0\;and %0,%0,%2 + nand %1,%1,%0\;and %1,%1,%2 + nand %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;and %3,%3,%2 + nor %0,%1,%0\;and %0,%0,%2 + nor %1,%1,%0\;and %1,%1,%2 + nor %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;and %3,%3,%2 + or %0,%1,%0\;and %0,%0,%2 + or %1,%1,%0\;and %1,%1,%2 + or %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;and %3,%3,%2 + orc %0,%1,%0\;and %0,%0,%2 + orc %1,%1,%0\;and %1,%1,%2 + orc %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: and op and rtl and inv 0 comp 0 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_and" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;and %3,%3,%2 + xor %0,%1,%0\;and %0,%0,%2 + xor %1,%1,%0\;and %1,%1,%2 + xor %4,%1,%0\;and %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;andc %3,%3,%2 + and %0,%1,%0\;andc %0,%0,%2 + and %1,%1,%0\;andc %1,%1,%2 + and %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;andc %3,%3,%2 + andc %0,%1,%0\;andc %0,%0,%2 + andc %1,%1,%0\;andc %1,%1,%2 + andc %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;andc %3,%3,%2 + eqv %0,%1,%0\;andc %0,%0,%2 + eqv %1,%1,%0\;andc %1,%1,%2 + eqv %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;andc %3,%3,%2 + nand %0,%1,%0\;andc %0,%0,%2 + nand %1,%1,%0\;andc %1,%1,%2 + nand %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;andc %3,%3,%2 + nor %0,%1,%0\;andc %0,%0,%2 + nor %1,%1,%0\;andc %1,%1,%2 + nor %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;andc %3,%3,%2 + or %0,%1,%0\;andc %0,%0,%2 + or %1,%1,%0\;andc %1,%1,%2 + or %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;andc %3,%3,%2 + orc %0,%1,%0\;andc %0,%0,%2 + orc %1,%1,%0\;andc %1,%1,%2 + orc %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_andc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;andc %3,%3,%2 + xor %0,%1,%0\;andc %0,%0,%2 + xor %1,%1,%0\;andc %1,%1,%2 + xor %4,%1,%0\;andc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;eqv %3,%3,%2 + and %0,%1,%0\;eqv %0,%0,%2 + and %1,%1,%0\;eqv %1,%1,%2 + and %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;eqv %3,%3,%2 + andc %0,%1,%0\;eqv %0,%0,%2 + andc %1,%1,%0\;eqv %1,%1,%2 + andc %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;eqv %3,%3,%2 + eqv %0,%1,%0\;eqv %0,%0,%2 + eqv %1,%1,%0\;eqv %1,%1,%2 + eqv %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;eqv %3,%3,%2 + nand %0,%1,%0\;eqv %0,%0,%2 + nand %1,%1,%0\;eqv %1,%1,%2 + nand %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;eqv %3,%3,%2 + nor %0,%1,%0\;eqv %0,%0,%2 + nor %1,%1,%0\;eqv %1,%1,%2 + nor %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;eqv %3,%3,%2 + or %0,%1,%0\;eqv %0,%0,%2 + or %1,%1,%0\;eqv %1,%1,%2 + or %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;eqv %3,%3,%2 + orc %0,%1,%0\;eqv %0,%0,%2 + orc %1,%1,%0\;eqv %1,%1,%2 + orc %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_eqv" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;eqv %3,%3,%2 + xor %0,%1,%0\;eqv %0,%0,%2 + xor %1,%1,%0\;eqv %1,%1,%2 + xor %4,%1,%0\;eqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;nand %3,%3,%2 + and %0,%1,%0\;nand %0,%0,%2 + and %1,%1,%0\;nand %1,%1,%2 + and %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;nand %3,%3,%2 + andc %0,%1,%0\;nand %0,%0,%2 + andc %1,%1,%0\;nand %1,%1,%2 + andc %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;nand %3,%3,%2 + eqv %0,%1,%0\;nand %0,%0,%2 + eqv %1,%1,%0\;nand %1,%1,%2 + eqv %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;nand %3,%3,%2 + nand %0,%1,%0\;nand %0,%0,%2 + nand %1,%1,%0\;nand %1,%1,%2 + nand %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;nand %3,%3,%2 + nor %0,%1,%0\;nand %0,%0,%2 + nor %1,%1,%0\;nand %1,%1,%2 + nor %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;nand %3,%3,%2 + or %0,%1,%0\;nand %0,%0,%2 + or %1,%1,%0\;nand %1,%1,%2 + or %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;nand %3,%3,%2 + orc %0,%1,%0\;nand %0,%0,%2 + orc %1,%1,%0\;nand %1,%1,%2 + orc %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_nand" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;nand %3,%3,%2 + xor %0,%1,%0\;nand %0,%0,%2 + xor %1,%1,%0\;nand %1,%1,%2 + xor %4,%1,%0\;nand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;nor %3,%3,%2 + and %0,%1,%0\;nor %0,%0,%2 + and %1,%1,%0\;nor %1,%1,%2 + and %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;nor %3,%3,%2 + andc %0,%1,%0\;nor %0,%0,%2 + andc %1,%1,%0\;nor %1,%1,%2 + andc %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;nor %3,%3,%2 + eqv %0,%1,%0\;nor %0,%0,%2 + eqv %1,%1,%0\;nor %1,%1,%2 + eqv %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;nor %3,%3,%2 + nand %0,%1,%0\;nor %0,%0,%2 + nand %1,%1,%0\;nor %1,%1,%2 + nand %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;nor %3,%3,%2 + nor %0,%1,%0\;nor %0,%0,%2 + nor %1,%1,%0\;nor %1,%1,%2 + nor %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;nor %3,%3,%2 + or %0,%1,%0\;nor %0,%0,%2 + or %1,%1,%0\;nor %1,%1,%2 + or %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;nor %3,%3,%2 + orc %0,%1,%0\;nor %0,%0,%2 + orc %1,%1,%0\;nor %1,%1,%2 + orc %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_nor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;nor %3,%3,%2 + xor %0,%1,%0\;nor %0,%0,%2 + xor %1,%1,%0\;nor %1,%1,%2 + xor %4,%1,%0\;nor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;or %3,%3,%2 + and %0,%1,%0\;or %0,%0,%2 + and %1,%1,%0\;or %1,%1,%2 + and %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;or %3,%3,%2 + andc %0,%1,%0\;or %0,%0,%2 + andc %1,%1,%0\;or %1,%1,%2 + andc %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;or %3,%3,%2 + eqv %0,%1,%0\;or %0,%0,%2 + eqv %1,%1,%0\;or %1,%1,%2 + eqv %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;or %3,%3,%2 + nand %0,%1,%0\;or %0,%0,%2 + nand %1,%1,%0\;or %1,%1,%2 + nand %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;or %3,%3,%2 + nor %0,%1,%0\;or %0,%0,%2 + nor %1,%1,%0\;or %1,%1,%2 + nor %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;or %3,%3,%2 + or %0,%1,%0\;or %0,%0,%2 + or %1,%1,%0\;or %1,%1,%2 + or %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;or %3,%3,%2 + orc %0,%1,%0\;or %0,%0,%2 + orc %1,%1,%0\;or %1,%1,%2 + orc %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: or op or rtl ior inv 0 comp 0 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_or" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;or %3,%3,%2 + xor %0,%1,%0\;or %0,%0,%2 + xor %1,%1,%0\;or %1,%1,%2 + xor %4,%1,%0\;or %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;orc %3,%3,%2 + and %0,%1,%0\;orc %0,%0,%2 + and %1,%1,%0\;orc %1,%1,%2 + and %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;orc %3,%3,%2 + andc %0,%1,%0\;orc %0,%0,%2 + andc %1,%1,%0\;orc %1,%1,%2 + andc %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;orc %3,%3,%2 + eqv %0,%1,%0\;orc %0,%0,%2 + eqv %1,%1,%0\;orc %1,%1,%2 + eqv %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;orc %3,%3,%2 + nand %0,%1,%0\;orc %0,%0,%2 + nand %1,%1,%0\;orc %1,%1,%2 + nand %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;orc %3,%3,%2 + nor %0,%1,%0\;orc %0,%0,%2 + nor %1,%1,%0\;orc %1,%1,%2 + nor %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;orc %3,%3,%2 + or %0,%1,%0\;orc %0,%0,%2 + or %1,%1,%0\;orc %1,%1,%2 + or %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;orc %3,%3,%2 + orc %0,%1,%0\;orc %0,%0,%2 + orc %1,%1,%0\;orc %1,%1,%2 + orc %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_orc" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;orc %3,%3,%2 + xor %0,%1,%0\;orc %0,%0,%2 + xor %1,%1,%0\;orc %1,%1,%2 + xor %4,%1,%0\;orc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: and op and rtl and inv 0 comp 0 +(define_insn "*fuse_and_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + and %3,%1,%0\;xor %3,%3,%2 + and %0,%1,%0\;xor %0,%0,%2 + and %1,%1,%0\;xor %1,%1,%2 + and %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: andc op andc rtl and inv 0 comp 1 +(define_insn "*fuse_andc_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + andc %3,%1,%0\;xor %3,%3,%2 + andc %0,%1,%0\;xor %0,%0,%2 + andc %1,%1,%0\;xor %1,%1,%2 + andc %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: eqv op eqv rtl xor inv 1 comp 0 +(define_insn "*fuse_eqv_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + eqv %3,%1,%0\;xor %3,%3,%2 + eqv %0,%1,%0\;xor %0,%0,%2 + eqv %1,%1,%0\;xor %1,%1,%2 + eqv %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: nand op nand rtl ior inv 0 comp 3 +(define_insn "*fuse_nand_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nand %3,%1,%0\;xor %3,%3,%2 + nand %0,%1,%0\;xor %0,%0,%2 + nand %1,%1,%0\;xor %1,%1,%2 + nand %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: nor op nor rtl and inv 0 comp 3 +(define_insn "*fuse_nor_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + nor %3,%1,%0\;xor %3,%3,%2 + nor %0,%1,%0\;xor %0,%0,%2 + nor %1,%1,%0\;xor %1,%1,%2 + nor %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: or op or rtl ior inv 0 comp 0 +(define_insn "*fuse_or_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + or %3,%1,%0\;xor %3,%3,%2 + or %0,%1,%0\;xor %0,%0,%2 + or %1,%1,%0\;xor %1,%1,%2 + or %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: orc op orc rtl ior inv 0 comp 1 +(define_insn "*fuse_orc_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + orc %3,%1,%0\;xor %3,%3,%2 + orc %0,%1,%0\;xor %0,%0,%2 + orc %1,%1,%0\;xor %1,%1,%2 + orc %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 +;; inner: xor op xor rtl xor inv 0 comp 0 +(define_insn "*fuse_xor_xor" + [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") + (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + xor %3,%1,%0\;xor %3,%3,%2 + xor %0,%1,%0\;xor %0,%0,%2 + xor %1,%1,%0\;xor %1,%1,%2 + xor %4,%1,%0\;xor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vand %3,%3,%2 + vand %0,%1,%0\;vand %0,%0,%2 + vand %1,%1,%0\;vand %1,%1,%2 + vand %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vand %3,%3,%2 + vandc %0,%1,%0\;vand %0,%0,%2 + vandc %1,%1,%0\;vand %1,%1,%2 + vandc %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vand %3,%3,%2 + veqv %0,%1,%0\;vand %0,%0,%2 + veqv %1,%1,%0\;vand %1,%1,%2 + veqv %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vand %3,%3,%2 + vnand %0,%1,%0\;vand %0,%0,%2 + vnand %1,%1,%0\;vand %1,%1,%2 + vnand %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vand %3,%3,%2 + vnor %0,%1,%0\;vand %0,%0,%2 + vnor %1,%1,%0\;vand %1,%1,%2 + vnor %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vand %3,%3,%2 + vor %0,%1,%0\;vand %0,%0,%2 + vor %1,%1,%0\;vand %1,%1,%2 + vor %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vand %3,%3,%2 + vorc %0,%1,%0\;vand %0,%0,%2 + vorc %1,%1,%0\;vand %1,%1,%2 + vorc %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: and op vand rtl and inv 0 comp 0 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vand %3,%3,%2 + vxor %0,%1,%0\;vand %0,%0,%2 + vxor %1,%1,%0\;vand %1,%1,%2 + vxor %4,%1,%0\;vand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vandc %3,%3,%2 + vand %0,%1,%0\;vandc %0,%0,%2 + vand %1,%1,%0\;vandc %1,%1,%2 + vand %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vandc %3,%3,%2 + vandc %0,%1,%0\;vandc %0,%0,%2 + vandc %1,%1,%0\;vandc %1,%1,%2 + vandc %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vandc %3,%3,%2 + veqv %0,%1,%0\;vandc %0,%0,%2 + veqv %1,%1,%0\;vandc %1,%1,%2 + veqv %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vandc %3,%3,%2 + vnand %0,%1,%0\;vandc %0,%0,%2 + vnand %1,%1,%0\;vandc %1,%1,%2 + vnand %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vandc %3,%3,%2 + vnor %0,%1,%0\;vandc %0,%0,%2 + vnor %1,%1,%0\;vandc %1,%1,%2 + vnor %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vandc %3,%3,%2 + vor %0,%1,%0\;vandc %0,%0,%2 + vor %1,%1,%0\;vandc %1,%1,%2 + vor %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vandc %3,%3,%2 + vorc %0,%1,%0\;vandc %0,%0,%2 + vorc %1,%1,%0\;vandc %1,%1,%2 + vorc %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vandc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vandc %3,%3,%2 + vxor %0,%1,%0\;vandc %0,%0,%2 + vxor %1,%1,%0\;vandc %1,%1,%2 + vxor %4,%1,%0\;vandc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;veqv %3,%3,%2 + vand %0,%1,%0\;veqv %0,%0,%2 + vand %1,%1,%0\;veqv %1,%1,%2 + vand %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;veqv %3,%3,%2 + vandc %0,%1,%0\;veqv %0,%0,%2 + vandc %1,%1,%0\;veqv %1,%1,%2 + vandc %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;veqv %3,%3,%2 + veqv %0,%1,%0\;veqv %0,%0,%2 + veqv %1,%1,%0\;veqv %1,%1,%2 + veqv %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;veqv %3,%3,%2 + vnand %0,%1,%0\;veqv %0,%0,%2 + vnand %1,%1,%0\;veqv %1,%1,%2 + vnand %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;veqv %3,%3,%2 + vnor %0,%1,%0\;veqv %0,%0,%2 + vnor %1,%1,%0\;veqv %1,%1,%2 + vnor %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;veqv %3,%3,%2 + vor %0,%1,%0\;veqv %0,%0,%2 + vor %1,%1,%0\;veqv %1,%1,%2 + vor %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;veqv %3,%3,%2 + vorc %0,%1,%0\;veqv %0,%0,%2 + vorc %1,%1,%0\;veqv %1,%1,%2 + vorc %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_veqv" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;veqv %3,%3,%2 + vxor %0,%1,%0\;veqv %0,%0,%2 + vxor %1,%1,%0\;veqv %1,%1,%2 + vxor %4,%1,%0\;veqv %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vnand %3,%3,%2 + vand %0,%1,%0\;vnand %0,%0,%2 + vand %1,%1,%0\;vnand %1,%1,%2 + vand %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vnand %3,%3,%2 + vandc %0,%1,%0\;vnand %0,%0,%2 + vandc %1,%1,%0\;vnand %1,%1,%2 + vandc %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vnand %3,%3,%2 + veqv %0,%1,%0\;vnand %0,%0,%2 + veqv %1,%1,%0\;vnand %1,%1,%2 + veqv %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vnand %3,%3,%2 + vnand %0,%1,%0\;vnand %0,%0,%2 + vnand %1,%1,%0\;vnand %1,%1,%2 + vnand %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vnand %3,%3,%2 + vnor %0,%1,%0\;vnand %0,%0,%2 + vnor %1,%1,%0\;vnand %1,%1,%2 + vnor %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vnand %3,%3,%2 + vor %0,%1,%0\;vnand %0,%0,%2 + vor %1,%1,%0\;vnand %1,%1,%2 + vor %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vnand %3,%3,%2 + vorc %0,%1,%0\;vnand %0,%0,%2 + vorc %1,%1,%0\;vnand %1,%1,%2 + vorc %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vnand" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vnand %3,%3,%2 + vxor %0,%1,%0\;vnand %0,%0,%2 + vxor %1,%1,%0\;vnand %1,%1,%2 + vxor %4,%1,%0\;vnand %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vnor %3,%3,%2 + vand %0,%1,%0\;vnor %0,%0,%2 + vand %1,%1,%0\;vnor %1,%1,%2 + vand %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vnor %3,%3,%2 + vandc %0,%1,%0\;vnor %0,%0,%2 + vandc %1,%1,%0\;vnor %1,%1,%2 + vandc %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vnor %3,%3,%2 + veqv %0,%1,%0\;vnor %0,%0,%2 + veqv %1,%1,%0\;vnor %1,%1,%2 + veqv %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vnor %3,%3,%2 + vnand %0,%1,%0\;vnor %0,%0,%2 + vnand %1,%1,%0\;vnor %1,%1,%2 + vnand %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vnor %3,%3,%2 + vnor %0,%1,%0\;vnor %0,%0,%2 + vnor %1,%1,%0\;vnor %1,%1,%2 + vnor %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vnor %3,%3,%2 + vor %0,%1,%0\;vnor %0,%0,%2 + vor %1,%1,%0\;vnor %1,%1,%2 + vor %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vnor %3,%3,%2 + vorc %0,%1,%0\;vnor %0,%0,%2 + vorc %1,%1,%0\;vnor %1,%1,%2 + vorc %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vnor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vnor %3,%3,%2 + vxor %0,%1,%0\;vnor %0,%0,%2 + vxor %1,%1,%0\;vnor %1,%1,%2 + vxor %4,%1,%0\;vnor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vor %3,%3,%2 + vand %0,%1,%0\;vor %0,%0,%2 + vand %1,%1,%0\;vor %1,%1,%2 + vand %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vor %3,%3,%2 + vandc %0,%1,%0\;vor %0,%0,%2 + vandc %1,%1,%0\;vor %1,%1,%2 + vandc %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vor %3,%3,%2 + veqv %0,%1,%0\;vor %0,%0,%2 + veqv %1,%1,%0\;vor %1,%1,%2 + veqv %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vor %3,%3,%2 + vnand %0,%1,%0\;vor %0,%0,%2 + vnand %1,%1,%0\;vor %1,%1,%2 + vnand %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vor %3,%3,%2 + vnor %0,%1,%0\;vor %0,%0,%2 + vnor %1,%1,%0\;vor %1,%1,%2 + vnor %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vor %3,%3,%2 + vor %0,%1,%0\;vor %0,%0,%2 + vor %1,%1,%0\;vor %1,%1,%2 + vor %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vor %3,%3,%2 + vorc %0,%1,%0\;vor %0,%0,%2 + vorc %1,%1,%0\;vor %1,%1,%2 + vorc %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: or op vor rtl ior inv 0 comp 0 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vor %3,%3,%2 + vxor %0,%1,%0\;vor %0,%0,%2 + vxor %1,%1,%0\;vor %1,%1,%2 + vxor %4,%1,%0\;vor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vorc %3,%3,%2 + vand %0,%1,%0\;vorc %0,%0,%2 + vand %1,%1,%0\;vorc %1,%1,%2 + vand %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vorc %3,%3,%2 + vandc %0,%1,%0\;vorc %0,%0,%2 + vandc %1,%1,%0\;vorc %1,%1,%2 + vandc %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vorc %3,%3,%2 + veqv %0,%1,%0\;vorc %0,%0,%2 + veqv %1,%1,%0\;vorc %1,%1,%2 + veqv %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vorc %3,%3,%2 + vnand %0,%1,%0\;vorc %0,%0,%2 + vnand %1,%1,%0\;vorc %1,%1,%2 + vnand %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vorc %3,%3,%2 + vnor %0,%1,%0\;vorc %0,%0,%2 + vnor %1,%1,%0\;vorc %1,%1,%2 + vnor %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vorc %3,%3,%2 + vor %0,%1,%0\;vorc %0,%0,%2 + vor %1,%1,%0\;vorc %1,%1,%2 + vor %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vorc %3,%3,%2 + vorc %0,%1,%0\;vorc %0,%0,%2 + vorc %1,%1,%0\;vorc %1,%1,%2 + vorc %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vorc" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vorc %3,%3,%2 + vxor %0,%1,%0\;vorc %0,%0,%2 + vxor %1,%1,%0\;vorc %1,%1,%2 + vxor %4,%1,%0\;vorc %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: and op vand rtl and inv 0 comp 0 +(define_insn "*fuse_vand_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vand %3,%1,%0\;vxor %3,%3,%2 + vand %0,%1,%0\;vxor %0,%0,%2 + vand %1,%1,%0\;vxor %1,%1,%2 + vand %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: andc op vandc rtl and inv 0 comp 1 +(define_insn "*fuse_vandc_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vandc %3,%1,%0\;vxor %3,%3,%2 + vandc %0,%1,%0\;vxor %0,%0,%2 + vandc %1,%1,%0\;vxor %1,%1,%2 + vandc %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: eqv op veqv rtl xor inv 1 comp 0 +(define_insn "*fuse_veqv_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + veqv %3,%1,%0\;vxor %3,%3,%2 + veqv %0,%1,%0\;vxor %0,%0,%2 + veqv %1,%1,%0\;vxor %1,%1,%2 + veqv %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: nand op vnand rtl ior inv 0 comp 3 +(define_insn "*fuse_vnand_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnand %3,%1,%0\;vxor %3,%3,%2 + vnand %0,%1,%0\;vxor %0,%0,%2 + vnand %1,%1,%0\;vxor %1,%1,%2 + vnand %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: nor op vnor rtl and inv 0 comp 3 +(define_insn "*fuse_vnor_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vnor %3,%1,%0\;vxor %3,%3,%2 + vnor %0,%1,%0\;vxor %0,%0,%2 + vnor %1,%1,%0\;vxor %1,%1,%2 + vnor %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: or op vor rtl ior inv 0 comp 0 +(define_insn "*fuse_vor_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vor %3,%1,%0\;vxor %3,%3,%2 + vor %0,%1,%0\;vxor %0,%0,%2 + vor %1,%1,%0\;vxor %1,%1,%2 + vor %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: orc op vorc rtl ior inv 0 comp 1 +(define_insn "*fuse_vorc_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vorc %3,%1,%0\;vxor %3,%3,%2 + vorc %0,%1,%0\;vxor %0,%0,%2 + vorc %1,%1,%0\;vxor %1,%1,%2 + vorc %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 +;; inner: xor op vxor rtl xor inv 0 comp 0 +(define_insn "*fuse_vxor_vxor" + [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + vxor %3,%1,%0\;vxor %3,%3,%2 + vxor %0,%1,%0\;vxor %0,%0,%2 + vxor %1,%1,%0\;vxor %1,%1,%2 + vxor %4,%1,%0\;vxor %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl new file mode 100755 index 0000000..837af7a --- /dev/null +++ b/gcc/config/rs6000/genfusion.pl @@ -0,0 +1,241 @@ +#!/usr/bin/perl +# Generate fusion.md +# +# Copyright (C) 2020,2021 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +use warnings; +use strict; + +print <<'EOF'; +;; Generated automatically by genfusion.pl + +;; Copyright (C) 2020,2021 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +EOF + +sub mode_to_ldst_char +{ + my ($mode) = @_; + my %x = (DI => 'd', SI => 'w', HI => 'h', QI => 'b'); + return $x{$mode} if exists $x{$mode}; + return '?'; +} + +sub gen_ld_cmpi_p10 +{ + my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred, + $ccmode, $np, $extend, $resultmode); + LMODE: foreach $lmode ('DI','SI','HI','QI') { + $ldst = mode_to_ldst_char($lmode); + $clobbermode = $lmode; + # For clobber, we need a SI/DI reg in case we + # split because we have to sign/zero extend. + if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; } + RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) { + # EXTDI does not exist, and we cannot directly produce HI/QI results. + next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI"; + # Don't allow EXTQI because that would allow HI result which we can't do. + $result = "GPR" if $result eq "EXTQI"; + CCMODE: foreach $ccmode ('CC','CCUNS') { + $np = "NON_PREFIXED_D"; + if ( $ccmode eq 'CC' ) { + next CCMODE if $lmode eq 'QI'; + if ( $lmode eq 'DI' || $lmode eq 'SI' ) { + # ld and lwa are both DS-FORM. + $np = "NON_PREFIXED_DS"; + } + $cmpl = ""; + $echr = "a"; + $constpred = "const_m1_to_1_operand"; + } else { + if ( $lmode eq 'DI' ) { + # ld is DS-form, but lwz is not. + $np = "NON_PREFIXED_DS"; + } + $cmpl = "l"; + $echr = "z"; + $constpred = "const_0_to_1_operand"; + } + if ($lmode eq 'DI') { $echr = ""; } + if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') { + # We always need extension if result > lmode. + if ( $ccmode eq 'CC' ) { + $extend = "sign"; + } else { + $extend = "zero"; + } + } else { + # Result of SI/DI does not need sign extension. + $extend = "none"; + } + print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n"; + print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n"; + + print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n"; + print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n"; + print " (compare:${ccmode} (match_operand:${lmode} 1 \"non_update_memory_operand\" \"m\")\n"; + if ($ccmode eq 'CCUNS') { print " "; } + print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n"; + if ($result eq 'clobber') { + print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n"; + } elsif ($result eq $lmode) { + print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n"; + } else { + print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n"; + } + print " \"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)\"\n"; + print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n"; + print " \"&& reload_completed\n"; + print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n"; + print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n"; + print " ${lmode}mode, ${np}))\"\n"; + + if ($extend eq "none") { + print " [(set (match_dup 0) (match_dup 1))\n"; + } else { + $resultmode = $result; + if ( $result eq 'clobber' ) { $resultmode = $clobbermode } + print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n"; + } + print " (set (match_dup 2)\n"; + print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n"; + print " \"\"\n"; + print " [(set_attr \"type\" \"load\")\n"; + print " (set_attr \"cost\" \"8\")\n"; + print " (set_attr \"length\" \"8\")])\n"; + print "\n"; + } + } + } +} + +sub gen_2logical +{ + my @logicals = ( "and", "andc", "eqv", "nand", "nor", "or", "orc", "xor" ); + my %complement = ( "and"=> 0, "andc"=> 1, "eqv"=> 0, "nand"=> 3, + "nor"=> 3, "or"=> 0, "orc"=> 1, "xor"=> 0 ); + my %invert = ( "and"=> 0, "andc"=> 0, "eqv"=> 1, "nand"=> 0, + "nor"=> 0, "or"=> 0, "orc"=> 0, "xor"=> 0 ); + my %commute2 = ( "and"=> 1, "andc"=> 0, "eqv"=> 1, "nand"=> 0, + "nor"=> 0, "or"=> 1, "orc"=> 0, "xor"=> 1 ); + my %rtlop = ( "and"=>"and", "andc"=>"and", "eqv"=>"xor", "nand"=>"ior", + "nor"=>"and", "or"=>"ior", "orc"=>"ior", "xor"=>"xor" ); + + my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op, + $outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv, + $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, + $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn); + KIND: foreach $kind ('scalar','vector') { + if ( $kind eq 'vector' ) { + $vchr = "v"; + $mode = "VM"; + $pred = "altivec_register_operand"; + $constraint = "v"; + } else { + $vchr = ""; + $mode = "GPR"; + $pred = "gpc_reg_operand"; + $constraint = "r"; + } + $c4 = "${constraint},${constraint},${constraint},${constraint}"; + OUTER: foreach $outer ( @logicals ) { + $outer_op = "${vchr}${outer}"; + $outer_comp = $complement{$outer}; + $outer_inv = $invert{$outer}; + $outer_rtl = $rtlop{$outer}; + INNER: foreach $inner ( @logicals ) { + $inner_comp = $complement{$inner}; + $inner_inv = $invert{$inner}; + $inner_rtl = $rtlop{$inner}; + $inner_op = "${vchr}${inner}"; + # If both ops commute then we can specify % on operand 1 + # so the pattern will let operands 1 and 2 interchange. + $both_commute = ($inner eq $outer) && ($commute2{$inner} == 1); + $bc = ""; if ( $both_commute ) { $bc = "%"; } + $inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")"; + $inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")"; + if ( ($inner_comp & 1) == 1 ) { + $inner_arg0 = "(not:${mode} $inner_arg0)"; + } + if ( ($inner_comp & 2) == 2 ) { + $inner_arg1 = "(not:${mode} $inner_arg1)"; + } + $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; + if ( $inner_inv == 1 ) { + $inner_exp = "(not:${mode} $inner_exp)"; + } + $outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")"; + if ( ($outer_comp & 1) == 1 ) { + $outer_arg2 = "(not:${mode} $outer_arg2)"; + } + if ( ($outer_comp & 2) == 2 ) { + $inner_exp = "(not:${mode} $inner_exp)"; + } + $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + if ( $outer_inv == 1 ) { + $outer_exp = "(not:${mode} $outer_exp)"; + } + + $insn = <<"EOF"; + +;; logical-logical fusion pattern generated by gen_2logical +;; kind: $kind outer: $outer op $outer_op rtl $outer_rtl inv $outer_inv comp $outer_comp +;; inner: $inner op $inner_op rtl $inner_rtl inv $inner_inv comp $inner_comp +(define_insn "*fuse_${inner_op}_${outer_op}" + [(set (match_operand:${mode} 3 "${pred}" "=&${constraint},0,1,${constraint}") + ${outer_exp}) + (clobber (match_scratch:${mode} 4 "=X,X,X,r"))] + "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" + "@ + ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 + ${inner_op} %0,%1,%0\\;${outer_op} %0,%0,%2 + ${inner_op} %1,%1,%0\\;${outer_op} %1,%1,%2 + ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2" + [(set_attr "type" "logical") + (set_attr "cost" "6") + (set_attr "length" "8")]) +EOF + + print $insn; + } + } + } +} + +gen_ld_cmpi_p10(); +gen_2logical(); + +exit(0); + diff --git a/gcc/config/rs6000/genopt.sh b/gcc/config/rs6000/genopt.sh index 3c6dd90..873a2d8 100755 --- a/gcc/config/rs6000/genopt.sh +++ b/gcc/config/rs6000/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate rs6000-tables.opt from the list of CPUs in rs6000-cpus.def. -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from rs6000-cpus.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/host-darwin.c b/gcc/config/rs6000/host-darwin.c index e3166c7..ee5cfc3 100644 --- a/gcc/config/rs6000/host-darwin.c +++ b/gcc/config/rs6000/host-darwin.c @@ -1,5 +1,5 @@ /* Darwin/powerpc host-specific hook definitions. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/host-ppc64-darwin.c b/gcc/config/rs6000/host-ppc64-darwin.c index 14cc20b..710329a 100644 --- a/gcc/config/rs6000/host-ppc64-darwin.c +++ b/gcc/config/rs6000/host-ppc64-darwin.c @@ -1,5 +1,5 @@ /* ppc64-darwin host-specific hook definitions. - Copyright (C) 2006-2020 Free Software Foundation, Inc. + Copyright (C) 2006-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md index a79bfcb..165544f 100644 --- a/gcc/config/rs6000/htm.md +++ b/gcc/config/rs6000/htm.md @@ -1,5 +1,5 @@ ;; Hardware Transactional Memory (HTM) patterns. -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; Contributed by Peter Bergner <bergner@vnet.ibm.com>. ;; This file is part of GCC. diff --git a/gcc/config/rs6000/htmintrin.h b/gcc/config/rs6000/htmintrin.h index 6cf8d36..1f655b7 100644 --- a/gcc/config/rs6000/htmintrin.h +++ b/gcc/config/rs6000/htmintrin.h @@ -1,5 +1,5 @@ /* Hardware Transactional Memory (HTM) intrinsics. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Peter Bergner <bergner@vnet.ibm.com>. This file is free software; you can redistribute it and/or modify it under diff --git a/gcc/config/rs6000/htmxlintrin.h b/gcc/config/rs6000/htmxlintrin.h index 89dba99..3690086 100644 --- a/gcc/config/rs6000/htmxlintrin.h +++ b/gcc/config/rs6000/htmxlintrin.h @@ -1,5 +1,5 @@ /* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Peter Bergner <bergner@vnet.ibm.com>. This file is free software; you can redistribute it and/or modify it under diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index b7026fc..47c9d9a 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC machines running Linux. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@cygnus.com). This file is part of GCC. diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 73b6c01..e3f2cd2 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit PowerPC linux. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/linux64.opt b/gcc/config/rs6000/linux64.opt index a0d7864..01ff3ec 100644 --- a/gcc/config/rs6000/linux64.opt +++ b/gcc/config/rs6000/linux64.opt @@ -1,6 +1,6 @@ ; Options for 64-bit PowerPC Linux. ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. @@ -20,7 +20,7 @@ ; <http://www.gnu.org/licenses/>. mprofile-kernel -Target Report Var(profile_kernel) Save +Target Var(profile_kernel) Save Call mcount for profiling before a function prologue. mcmodel= diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index 6422444..6ea0053 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for AltiVec enhanced PowerPC machines running GNU/Linux. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/lynx.h b/gcc/config/rs6000/lynx.h index 28f439a..3434c8b 100644 --- a/gcc/config/rs6000/lynx.h +++ b/gcc/config/rs6000/lynx.h @@ -1,5 +1,5 @@ /* Definitions for Rs6000 running LynxOS. - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com) Rewritten by Adam Nemet, LynuxWorks Inc. diff --git a/gcc/config/rs6000/mm_malloc.h b/gcc/config/rs6000/mm_malloc.h index 163f087..c0434806 100644 --- a/gcc/config/rs6000/mm_malloc.h +++ b/gcc/config/rs6000/mm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 4d291c4..87569f1 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -1,5 +1,5 @@ ;; Matrix-Multiply Assist (MMA) patterns. -;; Copyright (C) 2020 Free Software Foundation, Inc. +;; Copyright (C) 2020-2021 Free Software Foundation, Inc. ;; Contributed by Peter Bergner <bergner@linux.ibm.com> and ;; Michael Meissner <meissner@linux.ibm.com> ;; @@ -318,7 +318,7 @@ DONE; } [(set_attr "type" "vecload,vecstore,veclogical") - (set_attr "length" "8,8,16") + (set_attr "length" "*,*,16") (set_attr "max_prefixed_insns" "2,2,*")]) (define_expand "mma_assemble_pair" @@ -539,8 +539,7 @@ MMA_VVI4I4I8))] "TARGET_MMA" "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<avvi4i4i8>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -553,8 +552,7 @@ MMA_AVVI4I4I8))] "TARGET_MMA" "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<vvi4i4i2>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -566,8 +564,7 @@ MMA_VVI4I4I2))] "TARGET_MMA" "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<avvi4i4i2>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -580,8 +577,7 @@ MMA_AVVI4I4I2))] "TARGET_MMA" "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<vvi4i4>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -592,8 +588,7 @@ MMA_VVI4I4))] "TARGET_MMA" "<vvi4i4> %A0,%x1,%x2,%3,%4" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<avvi4i4>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -605,8 +600,7 @@ MMA_AVVI4I4))] "TARGET_MMA" "<avvi4i4> %A0,%x2,%x3,%4,%5" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<pvi4i2>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -617,8 +611,7 @@ MMA_PVI4I2))] "TARGET_MMA" "<pvi4i2> %A0,%x1,%x2,%3,%4" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<apvi4i2>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -630,8 +623,7 @@ MMA_APVI4I2))] "TARGET_MMA" "<apvi4i2> %A0,%x2,%x3,%4,%5" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<vvi4i4i4>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -643,8 +635,7 @@ MMA_VVI4I4I4))] "TARGET_MMA" "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) (define_insn "mma_<avvi4i4i4>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") @@ -657,5 +648,4 @@ MMA_AVVI4I4I4))] "TARGET_MMA" "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6" - [(set_attr "type" "mma") - (set_attr "length" "8")]) + [(set_attr "type" "mma")]) diff --git a/gcc/config/rs6000/mmintrin.h b/gcc/config/rs6000/mmintrin.h index b735cbf..0bd929c 100644 --- a/gcc/config/rs6000/mmintrin.h +++ b/gcc/config/rs6000/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -58,7 +58,8 @@ #include <altivec.h> /* The Intel API is flexible enough that we must allow aliasing with other vector types, and their scalar components. */ -typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64; +typedef __attribute__ ((__aligned__ (8), + __may_alias__)) unsigned long long __m64; typedef __attribute__ ((__aligned__ (8))) union diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index c1726aa..40e9f00 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC processor cores. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/netbsd.h b/gcc/config/rs6000/netbsd.h index 576b20f..3219b8d 100644 --- a/gcc/config/rs6000/netbsd.h +++ b/gcc/config/rs6000/netbsd.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC NetBSD systems. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index e5f401b..7ebd115 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -1,5 +1,5 @@ /* Definitions of default options for config/rs6000 configurations. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/pmmintrin.h b/gcc/config/rs6000/pmmintrin.h index 4f1b8d4..eab712f 100644 --- a/gcc/config/rs6000/pmmintrin.h +++ b/gcc/config/rs6000/pmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 2b4d882..f9632b6 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER10 processor. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; This is a clone of power9.md. It is intended to be a placeholder until a ;; real scheduler model can be contributed. diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index 881eba2..68a47a8 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM Power4 and PowerPC 970 processors. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index d406d5f..a845734 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER5 processor. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index e2e7582..18f1038 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER6 processor. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index b958181..9095828 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER7 processor. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index a3f46c6..27294d3 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER8 processor. -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). diff --git a/gcc/config/rs6000/power9.md b/gcc/config/rs6000/power9.md index c86d643..cb2b448 100644 --- a/gcc/config/rs6000/power9.md +++ b/gcc/config/rs6000/power9.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER9 processor. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). diff --git a/gcc/config/rs6000/ppc-asm.h b/gcc/config/rs6000/ppc-asm.h index e0bce9c..1b576a0 100644 --- a/gcc/config/rs6000/ppc-asm.h +++ b/gcc/config/rs6000/ppc-asm.h @@ -1,6 +1,6 @@ /* PowerPC asm definitions for GNU C. -Copyright (C) 2002-2020 Free Software Foundation, Inc. +Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h index 7a5ba0e..ffb9e7b 100644 --- a/gcc/config/rs6000/ppc-auxv.h +++ b/gcc/config/rs6000/ppc-auxv.h @@ -1,7 +1,7 @@ /* PowerPC support for accessing the AUXV AT_PLATFORM, AT_HWCAP and AT_HWCAP2 values from the Thread Control Block (TCB). - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. Contributed by Peter Bergner <bergner@vnet.ibm.com>. This file is part of GCC. diff --git a/gcc/config/rs6000/ppu_intrinsics.h b/gcc/config/rs6000/ppu_intrinsics.h index ff6a1ac..e17faae 100644 --- a/gcc/config/rs6000/ppu_intrinsics.h +++ b/gcc/config/rs6000/ppu_intrinsics.h @@ -1,5 +1,5 @@ /* PPU intrinsics as defined by the C/C++ Language extension for Cell BEA. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 9ad5ae6..76328ec 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for POWER and PowerPC. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -297,6 +297,11 @@ (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) +;; Match op = -1, op = 0, or op = 1. +(define_predicate "const_m1_to_1_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -1, 1)"))) + ;; Match op = 0..3. (define_predicate "const_0_to_3_operand" (and (match_code "const_int") @@ -847,6 +852,15 @@ || GET_CODE (XEXP (op, 0)) == PRE_DEC || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) +;; Anything that matches memory_operand but does not update the address. +(define_predicate "non_update_memory_operand" + (match_code "mem") +{ + if (update_address_mem (op, mode)) + return 0; + return memory_operand (op, mode); +}) + ;; Return 1 if the operand is a MEM with an indexed-form address. (define_special_predicate "indexed_address_mem" (match_test "(MEM_P (op) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 47b1f74..058a32a 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1,5 +1,5 @@ /* Builtin functions for rs6000/powerpc. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) This file is part of GCC. @@ -2883,6 +2883,24 @@ BU_P10V_AV_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi) BU_P10V_AV_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si) BU_P10V_AV_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di) +BU_P10V_AV_2 (DIVES_V4SI, "vdivesw", CONST, dives_v4si) +BU_P10V_AV_2 (DIVES_V2DI, "vdivesd", CONST, dives_v2di) +BU_P10V_AV_2 (DIVEU_V4SI, "vdiveuw", CONST, diveu_v4si) +BU_P10V_AV_2 (DIVEU_V2DI, "vdiveud", CONST, diveu_v2di) +BU_P10V_AV_2 (DIVS_V4SI, "vdivsw", CONST, divv4si3) +BU_P10V_AV_2 (DIVS_V2DI, "vdivsd", CONST, divv2di3) +BU_P10V_AV_2 (DIVU_V4SI, "vdivuw", CONST, udivv4si3) +BU_P10V_AV_2 (DIVU_V2DI, "vdivud", CONST, udivv2di3) +BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, mods_v2di) +BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, mods_v4si) +BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, modu_v2di) +BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, modu_v4si) +BU_P10V_AV_2 (MULHS_V2DI, "vmulhsd", CONST, mulhs_v2di) +BU_P10V_AV_2 (MULHS_V4SI, "vmulhsw", CONST, mulhs_v4si) +BU_P10V_AV_2 (MULHU_V2DI, "vmulhud", CONST, mulhu_v2di) +BU_P10V_AV_2 (MULHU_V4SI, "vmulhuw", CONST, mulhu_v4si) +BU_P10V_AV_2 (MULLD_V2DI, "vmulld", CONST, mulv2di3) + BU_P10V_VSX_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si) BU_P10V_VSX_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf) @@ -2958,6 +2976,9 @@ BU_P10_OVERLOAD_1 (VSTRIL_P, "stril_p") BU_P10_OVERLOAD_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros") BU_P10_OVERLOAD_1 (XVTLSBB_ONES, "xvtlsbb_all_ones") +BU_P10_OVERLOAD_2 (MULH, "mulh") +BU_P10_OVERLOAD_2 (DIVE, "dive") +BU_P10_OVERLOAD_2 (MOD, "mod") BU_P10_OVERLOAD_1 (MTVSRBM, "mtvsrbm") BU_P10_OVERLOAD_1 (MTVSRHM, "mtvsrhm") diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index cc1e997..06b3bc0 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1,5 +1,5 @@ /* Subroutines for the C front end on the PowerPC architecture. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Zack Weinberg <zack@codesourcery.com> and Paolo Bonzini <bonzini@gnu.org> @@ -483,6 +483,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, /* Define this when supporting context-sensitive keywords. */ if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); + if (rs6000_aix_extabi) + rs6000_define_or_undefine_macro (define_p, "__EXTABI__"); } /* Note that the OPTION_MASK_VSX flag is automatically turned on in the following conditions: @@ -1512,9 +1514,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, tree arg1; tree arg2; tree arg1_type; - tree arg1_inner_type; tree decl, stmt; - tree innerptrtype; machine_mode mode; /* No second or third arguments. */ @@ -1566,8 +1566,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, return build_call_expr (call, 3, arg1, arg0, arg2); } - /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ - arg1_inner_type = TREE_TYPE (arg1_type); + /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0 with + VIEW_CONVERT_EXPR. i.e.: + D.3192 = v1; + _1 = n & 3; + VIEW_CONVERT_EXPR<int[4]>(D.3192)[_1] = i; + v1 = D.3192; + D.3194 = v1; */ if (TYPE_VECTOR_SUBPARTS (arg1_type) == 1) arg2 = build_int_cst (TREE_TYPE (arg2), 0); else @@ -1582,6 +1587,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, TREE_USED (decl) = 1; TREE_TYPE (decl) = arg1_type; TREE_READONLY (decl) = TYPE_READONLY (arg1_type); + TREE_ADDRESSABLE (decl) = 1; if (c_dialect_cxx ()) { stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, @@ -1592,20 +1598,32 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, { DECL_INITIAL (decl) = arg1; stmt = build1 (DECL_EXPR, arg1_type, decl); - TREE_ADDRESSABLE (decl) = 1; SET_EXPR_LOCATION (stmt, loc); stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); } - innerptrtype = build_pointer_type (arg1_inner_type); - - stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); - stmt = convert (innerptrtype, stmt); - stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); - stmt = build_indirect_ref (loc, stmt, RO_NULL); - stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, - convert (TREE_TYPE (stmt), arg0)); - stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); + if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT) + { + stmt = build_array_ref (loc, stmt, arg2); + stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt, + convert (TREE_TYPE (stmt), arg0)); + stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); + } + else + { + tree arg1_inner_type; + tree innerptrtype; + arg1_inner_type = TREE_TYPE (arg1_type); + innerptrtype = build_pointer_type (arg1_inner_type); + + stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); + stmt = convert (innerptrtype, stmt); + stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); + stmt = build_indirect_ref (loc, stmt, RO_NULL); + stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, + convert (TREE_TYPE (stmt), arg0)); + stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); + } return stmt; } diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 45bc048..de0ce50 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -1,6 +1,6 @@ /* Subroutines used to generate function calls and handle built-in instructions on IBM RS/6000. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -1069,6 +1069,40 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + + { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + + { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, @@ -1909,6 +1943,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V4SI, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V4SI, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, @@ -9519,7 +9564,9 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) else if (icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs - || icode == CODE_FOR_altivec_vctuxs) + || icode == CODE_FOR_altivec_vctuxs + || icode == CODE_FOR_vsx_xvcvuxddp_scale + || icode == CODE_FOR_vsx_xvcvsxddp_scale) { /* Only allow 5-bit unsigned literals. */ STRIP_NOPS (arg1); @@ -14438,6 +14485,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, case P10V_BUILTIN_XXGENPCVM_V8HI: case P10V_BUILTIN_XXGENPCVM_V4SI: case P10V_BUILTIN_XXGENPCVM_V2DI: + case P10V_BUILTIN_DIVEU_V4SI: + case P10V_BUILTIN_DIVEU_V2DI: + case P10V_BUILTIN_DIVU_V4SI: + case P10V_BUILTIN_DIVU_V2DI: + case P10V_BUILTIN_MODU_V2DI: + case P10V_BUILTIN_MODU_V4SI: + case P10V_BUILTIN_MULHU_V2DI: + case P10V_BUILTIN_MULHU_V4SI: h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 482e1b6..f0cf79e 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -1,5 +1,5 @@ /* IBM RS/6000 CPU names.. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -81,7 +81,10 @@ #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ - | OTHER_POWER10_MASKS) + | OTHER_POWER10_MASKS \ + | OPTION_MASK_P10_FUSION \ + | OPTION_MASK_P10_FUSION_LD_CMPI \ + | OPTION_MASK_P10_FUSION_2LOGICAL) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -128,6 +131,9 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ + | OPTION_MASK_P10_FUSION \ + | OPTION_MASK_P10_FUSION_LD_CMPI \ + | OPTION_MASK_P10_FUSION_2LOGICAL \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ diff --git a/gcc/config/rs6000/rs6000-d.c b/gcc/config/rs6000/rs6000-d.c index fd16e80..14c4133 100644 --- a/gcc/config/rs6000/rs6000-d.c +++ b/gcc/config/rs6000/rs6000-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the PowerPC architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index 32681b6..428a786 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -1,6 +1,6 @@ /* Internal to rs6000 type, variable, and function declarations and definitons shared between the various rs6000 source files. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-linux.c b/gcc/config/rs6000/rs6000-linux.c index 14aa273..e91ff92 100644 --- a/gcc/config/rs6000/rs6000-linux.c +++ b/gcc/config/rs6000/rs6000-linux.c @@ -1,5 +1,5 @@ /* Functions for Linux on PowerPC. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-logue.c b/gcc/config/rs6000/rs6000-logue.c index d90cd57..b0ac183 100644 --- a/gcc/config/rs6000/rs6000-logue.c +++ b/gcc/config/rs6000/rs6000-logue.c @@ -1,6 +1,6 @@ /* Subroutines used to generate function prologues and epilogues on IBM RS/6000. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index e81a32c..e6f0806 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-modes.h b/gcc/config/rs6000/rs6000-modes.h index 573e6de..5d554f8 100644 --- a/gcc/config/rs6000/rs6000-modes.h +++ b/gcc/config/rs6000/rs6000-modes.h @@ -1,5 +1,5 @@ /* Definitions 128-bit floating point precisions used by PowerPC. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index eaf6edc..51d6c65 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -1,6 +1,6 @@ /* Definitions of target machine needed for option handling for GNU compiler, for IBM RS/6000. - Copyright (C) 2010-2020 Free Software Foundation, Inc. + Copyright (C) 2010-2021 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-p8swap.c b/gcc/config/rs6000/rs6000-p8swap.c index fff1b08..ad2b302 100644 --- a/gcc/config/rs6000/rs6000-p8swap.c +++ b/gcc/config/rs6000/rs6000-p8swap.c @@ -1,6 +1,6 @@ /* Subroutines used to remove unnecessary doubleword swaps for p8 little-endian VSX code. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-passes.def b/gcc/config/rs6000/rs6000-passes.def index 5164c52..606ad3e 100644 --- a/gcc/config/rs6000/rs6000-passes.def +++ b/gcc/config/rs6000/rs6000-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for rs6000 - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 3c4682b..d9d44fe 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -191,6 +191,8 @@ enum non_prefixed_form { extern enum insn_form address_to_insn_form (rtx, machine_mode, enum non_prefixed_form); +extern bool address_is_non_pfx_d_or_x (rtx addr, machine_mode mode, + enum non_prefixed_form non_prefix_format); extern bool prefixed_load_p (rtx_insn *); extern bool prefixed_store_p (rtx_insn *); extern bool prefixed_paddi_p (rtx_insn *); diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c index a2e6821..cc75ca5 100644 --- a/gcc/config/rs6000/rs6000-string.c +++ b/gcc/config/rs6000/rs6000-string.c @@ -1,6 +1,6 @@ /* Subroutines used to expand string and block move, clear, compare and other operations for PowerPC. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 8ae2b60..3f9ea9be 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from rs6000-cpus.def. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f26fc13..ec068c5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM RS/6000. - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -2512,6 +2512,9 @@ rs6000_debug_reg_global (void) if (rs6000_altivec_abi) fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true"); + if (rs6000_aix_extabi) + fprintf (stderr, DEBUG_FMT_S, "AIX vec-extabi", "true"); + if (rs6000_darwin64_abi) fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true"); @@ -4430,6 +4433,16 @@ rs6000_option_override_internal (bool global_init_p) if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_MMA) == 0) rs6000_isa_flags |= OPTION_MASK_MMA; + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION; + + if (TARGET_POWER10 && + (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LD_CMPI) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LD_CMPI; + + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL; + /* Turn off vector pair/mma options on non-power10 systems. */ else if (!TARGET_POWER10 && TARGET_MMA) { @@ -6806,17 +6819,9 @@ rs6000_expand_vector_init (rtx target, rtx vals) /* Force the values into word_mode registers. */ for (i = 0; i < n_elts; i++) { - rtx tmp = force_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, i)); - if (TARGET_POWERPC64) - { - op[i] = gen_reg_rtx (DImode); - emit_insn (gen_zero_extendqidi2 (op[i], tmp)); - } - else - { - op[i] = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendqisi2 (op[i], tmp)); - } + rtx tmp = force_reg (inner_mode, XVECEXP (vals, 0, i)); + machine_mode tmode = TARGET_POWERPC64 ? DImode : SImode; + op[i] = simplify_gen_subreg (tmode, tmp, inner_mode, 0); } /* Take unsigned char big endianness on 64bit as example for below @@ -6985,6 +6990,152 @@ rs6000_expand_vector_init (rtx target, rtx vals) emit_move_insn (target, mem); } +/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX + is variable and also counts by vector element size for p9 and above. */ + +static void +rs6000_expand_vector_set_var_p9 (rtx target, rtx val, rtx idx) +{ + machine_mode mode = GET_MODE (target); + + gcc_assert (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (idx)); + + gcc_assert (GET_MODE (idx) == E_SImode); + + machine_mode inner_mode = GET_MODE (val); + + rtx tmp = gen_reg_rtx (GET_MODE (idx)); + int width = GET_MODE_SIZE (inner_mode); + + gcc_assert (width >= 1 && width <= 8); + + int shift = exact_log2 (width); + /* Generate the IDX for permute shift, width is the vector element size. + idx = idx * width. */ + emit_insn (gen_ashlsi3 (tmp, idx, GEN_INT (shift))); + + tmp = convert_modes (DImode, SImode, tmp, 1); + + /* lvsr v1,0,idx. */ + rtx pcvr = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsr_reg (pcvr, tmp)); + + /* lvsl v2,0,idx. */ + rtx pcvl = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_reg (pcvl, tmp)); + + rtx sub_target = simplify_gen_subreg (V16QImode, target, mode, 0); + + rtx permr + = gen_altivec_vperm_v8hiv16qi (sub_target, sub_target, sub_target, pcvr); + emit_insn (permr); + + rs6000_expand_vector_set (target, val, const0_rtx); + + rtx perml + = gen_altivec_vperm_v8hiv16qi (sub_target, sub_target, sub_target, pcvl); + emit_insn (perml); +} + +/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX + is variable and also counts by vector element size for p8. */ + +static void +rs6000_expand_vector_set_var_p8 (rtx target, rtx val, rtx idx) +{ + machine_mode mode = GET_MODE (target); + + gcc_assert (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (idx)); + + gcc_assert (GET_MODE (idx) == E_SImode); + + machine_mode inner_mode = GET_MODE (val); + HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); + + rtx tmp = gen_reg_rtx (GET_MODE (idx)); + int width = GET_MODE_SIZE (inner_mode); + + gcc_assert (width >= 1 && width <= 4); + + if (!BYTES_BIG_ENDIAN) + { + /* idx = idx * width. */ + emit_insn (gen_mulsi3 (tmp, idx, GEN_INT (width))); + /* idx = idx + 8. */ + emit_insn (gen_addsi3 (tmp, tmp, GEN_INT (8))); + } + else + { + emit_insn (gen_mulsi3 (tmp, idx, GEN_INT (width))); + emit_insn (gen_subsi3 (tmp, GEN_INT (24 - width), tmp)); + } + + /* lxv vs33, mask. + DImode: 0xffffffffffffffff0000000000000000 + SImode: 0x00000000ffffffff0000000000000000 + HImode: 0x000000000000ffff0000000000000000. + QImode: 0x00000000000000ff0000000000000000. */ + rtx mask = gen_reg_rtx (V16QImode); + rtx mask_v2di = gen_reg_rtx (V2DImode); + rtvec v = rtvec_alloc (2); + if (!BYTES_BIG_ENDIAN) + { + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (DImode, 0); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (DImode, mode_mask); + } + else + { + RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (DImode, mode_mask); + RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (DImode, 0); + } + emit_insn (gen_vec_initv2didi (mask_v2di, gen_rtx_PARALLEL (V2DImode, v))); + rtx sub_mask = simplify_gen_subreg (V16QImode, mask_v2di, V2DImode, 0); + emit_insn (gen_rtx_SET (mask, sub_mask)); + + /* mtvsrd[wz] f0,tmp_val. */ + rtx tmp_val = gen_reg_rtx (SImode); + if (inner_mode == E_SFmode) + emit_insn (gen_movsi_from_sf (tmp_val, val)); + else + tmp_val = force_reg (SImode, val); + + rtx val_v16qi = gen_reg_rtx (V16QImode); + rtx val_v2di = gen_reg_rtx (V2DImode); + rtvec vec_val = rtvec_alloc (2); + if (!BYTES_BIG_ENDIAN) + { + RTVEC_ELT (vec_val, 0) = gen_rtx_CONST_INT (DImode, 0); + RTVEC_ELT (vec_val, 1) = tmp_val; + } + else + { + RTVEC_ELT (vec_val, 0) = tmp_val; + RTVEC_ELT (vec_val, 1) = gen_rtx_CONST_INT (DImode, 0); + } + emit_insn ( + gen_vec_initv2didi (val_v2di, gen_rtx_PARALLEL (V2DImode, vec_val))); + rtx sub_val = simplify_gen_subreg (V16QImode, val_v2di, V2DImode, 0); + emit_insn (gen_rtx_SET (val_v16qi, sub_val)); + + /* lvsl 13,0,idx. */ + tmp = convert_modes (DImode, SImode, tmp, 1); + rtx pcv = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_lvsl_reg (pcv, tmp)); + + /* vperm 1,1,1,13. */ + /* vperm 0,0,0,13. */ + rtx val_perm = gen_reg_rtx (V16QImode); + rtx mask_perm = gen_reg_rtx (V16QImode); + emit_insn (gen_altivec_vperm_v8hiv16qi (val_perm, val_v16qi, val_v16qi, pcv)); + emit_insn (gen_altivec_vperm_v8hiv16qi (mask_perm, mask, mask, pcv)); + + rtx target_v16qi = simplify_gen_subreg (V16QImode, target, mode, 0); + + /* xxsel 34,34,32,33. */ + emit_insn ( + gen_vector_select_v16qi (target_v16qi, target_v16qi, val_perm, mask_perm)); +} + /* Set field ELT_RTX of TARGET to VAL. */ void @@ -7001,6 +7152,22 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx) if (VECTOR_MEM_VSX_P (mode)) { + if (!CONST_INT_P (elt_rtx)) + { + /* For V2DI/V2DF, could leverage the P9 version to generate xxpermdi + when elt_rtx is variable. */ + if ((TARGET_P9_VECTOR && TARGET_POWERPC64) || width == 8) + { + rs6000_expand_vector_set_var_p9 (target, val, elt_rtx); + return; + } + else if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT) + { + rs6000_expand_vector_set_var_p8 (target, val, elt_rtx); + return; + } + } + rtx insn = NULL_RTX; if (mode == V2DFmode) @@ -9654,7 +9821,7 @@ rs6000_conditional_register_usage (void) call_used_regs[i] = 1; /* AIX reserves VR20:31 in non-extended ABI mode. */ - if (TARGET_XCOFF) + if (TARGET_XCOFF && !rs6000_aix_extabi) for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i) fixed_regs[i] = call_used_regs[i] = 1; } @@ -9940,10 +10107,8 @@ rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode) void rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode) { - /* This should never be called during or after LRA, because it does - not re-permute the source register. It is intended only for use - during expand. */ - gcc_assert (!lra_in_progress && !reload_completed); + /* This should never be called after LRA. */ + gcc_assert (can_create_pseudo_p ()); /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode, V1TImode). */ @@ -9954,7 +10119,7 @@ rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode) source = gen_lowpart (V2DImode, source); } - rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source; + rtx tmp = gen_reg_rtx_and_attrs (source); rs6000_emit_le_vsx_permute (tmp, source, mode); rs6000_emit_le_vsx_permute (dest, tmp, mode); } @@ -22954,6 +23119,16 @@ rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, if (TARGET_ALTIVEC && testing_p) return true; + if (op0) + { + rtx nop0 = force_reg (vmode, op0); + if (op0 == op1) + op1 = nop0; + op0 = nop0; + } + if (op1) + op1 = force_reg (vmode, op1); + /* Check for ps_merge* or xxpermdi insns. */ if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode)) { @@ -23621,6 +23796,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true }, { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, + { "power10-fusion", OPTION_MASK_P10_FUSION, false, true }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, { "prefixed", OPTION_MASK_PREFIXED, false, true }, @@ -25712,6 +25888,50 @@ address_to_insn_form (rtx addr, return INSN_FORM_BAD; } +/* Given address rtx ADDR for a load of MODE, is this legitimate for a + non-prefixed D-form or X-form instruction? NON_PREFIXED_FORMAT is + given NON_PREFIXED_D or NON_PREFIXED_DS to indicate whether we want + a D-form or DS-form instruction. X-form and base_reg are always + allowed. */ +bool +address_is_non_pfx_d_or_x (rtx addr, machine_mode mode, + enum non_prefixed_form non_prefixed_format) +{ + enum insn_form result_form; + + result_form = address_to_insn_form (addr, mode, non_prefixed_format); + + switch (non_prefixed_format) + { + case NON_PREFIXED_D: + switch (result_form) + { + case INSN_FORM_X: + case INSN_FORM_D: + case INSN_FORM_DS: + case INSN_FORM_BASE_REG: + return true; + default: + return false; + } + break; + case NON_PREFIXED_DS: + switch (result_form) + { + case INSN_FORM_X: + case INSN_FORM_DS: + case INSN_FORM_BASE_REG: + return true; + default: + return false; + } + break; + default: + break; + } + return false; +} + /* Helper function to see if we're potentially looking at lfs/stfs. - PARALLEL containing a SET and a CLOBBER - stfs: @@ -27124,57 +27344,128 @@ rs6000_globalize_decl_name (FILE * stream, tree decl) library before you can switch the real*16 type at compile time. We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We - only do this if the default is that long double is IBM extended double, and - the user asked for IEEE 128-bit. */ + only do this transformation if the __float128 type is enabled. This + prevents us from doing the transformation on older 32-bit ports that might + have enabled using IEEE 128-bit floating point as the default long double + type. */ static tree rs6000_mangle_decl_assembler_name (tree decl, tree id) { - if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 + if (TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && TREE_CODE (decl) == FUNCTION_DECL - && DECL_IS_UNDECLARED_BUILTIN (decl)) + && DECL_IS_UNDECLARED_BUILTIN (decl) + && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) { size_t len = IDENTIFIER_LENGTH (id); const char *name = IDENTIFIER_POINTER (id); + char *newname = NULL; - if (name[len - 1] == 'l') + /* See if it is one of the built-in functions with an unusual name. */ + switch (DECL_FUNCTION_CODE (decl)) { - bool uses_ieee128_p = false; - tree type = TREE_TYPE (decl); - machine_mode ret_mode = TYPE_MODE (type); + case BUILT_IN_DREML: + newname = xstrdup ("__remainderieee128"); + break; - /* See if the function returns a IEEE 128-bit floating point type or - complex type. */ - if (ret_mode == TFmode || ret_mode == TCmode) - uses_ieee128_p = true; - else - { - function_args_iterator args_iter; - tree arg; + case BUILT_IN_GAMMAL: + newname = xstrdup ("__lgammaieee128"); + break; + + case BUILT_IN_GAMMAL_R: + case BUILT_IN_LGAMMAL_R: + newname = xstrdup ("__lgammaieee128_r"); + break; + + case BUILT_IN_NEXTTOWARD: + newname = xstrdup ("__nexttoward_to_ieee128"); + break; - /* See if the function passes a IEEE 128-bit floating point type - or complex type. */ - FOREACH_FUNCTION_ARGS (type, arg, args_iter) + case BUILT_IN_NEXTTOWARDF: + newname = xstrdup ("__nexttowardf_to_ieee128"); + break; + + case BUILT_IN_NEXTTOWARDL: + newname = xstrdup ("__nexttowardieee128"); + break; + + case BUILT_IN_POW10L: + newname = xstrdup ("__exp10ieee128"); + break; + + case BUILT_IN_SCALBL: + newname = xstrdup ("__scalbieee128"); + break; + + case BUILT_IN_SIGNIFICANDL: + newname = xstrdup ("__significandieee128"); + break; + + case BUILT_IN_SINCOSL: + newname = xstrdup ("__sincosieee128"); + break; + + default: + break; + } + + /* Update the __builtin_*printf and __builtin_*scanf functions. */ + if (!newname) + { + size_t printf_len = strlen ("printf"); + size_t scanf_len = strlen ("scanf"); + + if (len >= printf_len + && strcmp (name + len - printf_len, "printf") == 0) + newname = xasprintf ("__%sieee128", name); + + else if (len >= scanf_len + && strcmp (name + len - scanf_len, "scanf") == 0) + newname = xasprintf ("__isoc99_%sieee128", name); + + else if (name[len - 1] == 'l') + { + bool uses_ieee128_p = false; + tree type = TREE_TYPE (decl); + machine_mode ret_mode = TYPE_MODE (type); + + /* See if the function returns a IEEE 128-bit floating point type or + complex type. */ + if (ret_mode == TFmode || ret_mode == TCmode) + uses_ieee128_p = true; + else { - machine_mode arg_mode = TYPE_MODE (arg); - if (arg_mode == TFmode || arg_mode == TCmode) + function_args_iterator args_iter; + tree arg; + + /* See if the function passes a IEEE 128-bit floating point type + or complex type. */ + FOREACH_FUNCTION_ARGS (type, arg, args_iter) { - uses_ieee128_p = true; - break; + machine_mode arg_mode = TYPE_MODE (arg); + if (arg_mode == TFmode || arg_mode == TCmode) + { + uses_ieee128_p = true; + break; + } } } - } - /* If we passed or returned an IEEE 128-bit floating point type, - change the name. */ - if (uses_ieee128_p) - { - char *name2 = (char *) alloca (len + 4); - memcpy (name2, name, len - 1); - strcpy (name2 + len - 1, "f128"); - id = get_identifier (name2); + /* If we passed or returned an IEEE 128-bit floating point type, + change the name. Use __<name>ieee128, instead of <name>l. */ + if (uses_ieee128_p) + newname = xasprintf ("__%.*sieee128", (int)(len - 1), name); } } + + if (newname) + { + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "Map %s => %s\n", name, newname); + + id = get_identifier (newname); + free (newname); + } } return id; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 5bf9c83..233a92b 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -539,6 +539,7 @@ extern int rs6000_vector_align[]; #define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX #define MASK_POWER10 OPTION_MASK_POWER10 +#define MASK_P10_FUSION OPTION_MASK_P10_FUSION #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b89990f..a131552 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1,5 +1,5 @@ ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler -;; Copyright (C) 1990-2020 Free Software Foundation, Inc. +;; Copyright (C) 1990-2021 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; This file is part of GCC. @@ -668,9 +668,10 @@ (V4SI "du") (V2DI "d")]) -;; How many bits in this mode? +;; How many bits (per element) in this mode? (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64") - (SF "32") (DF "64")]) + (SF "32") (DF "64") + (V4SI "32") (V2DI "64")]) ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) @@ -14926,3 +14927,4 @@ (include "dfp.md") (include "crypto.md") (include "htm.md") +(include "fusion.md") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 2888172..ae9e91e 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -1,6 +1,6 @@ ; Options for the rs6000 port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. @@ -117,31 +117,31 @@ mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) Var(rs6000_isa_flags) +Target Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set. mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) +Target Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions. mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) +Target Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions. mmfcrf -Target Report Mask(MFCRF) Var(rs6000_isa_flags) +Target Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction. mpopcntb -Target Report Mask(POPCNTB) Var(rs6000_isa_flags) +Target Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction. mfprnd -Target Report Mask(FPRND) Var(rs6000_isa_flags) +Target Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions. mcmpb -Target Report Mask(CMPB) Var(rs6000_isa_flags) +Target Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction. ;; This option existed in the past, but now is always off. @@ -152,27 +152,27 @@ mmfpgpr Target RejectNegative Undocumented WarnRemoved maltivec -Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) +Target Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions. mfold-gimple -Target Report Var(rs6000_fold_gimple) Init(1) +Target Var(rs6000_fold_gimple) Init(1) Enable early gimple folding of builtins. mhard-dfp -Target Report Mask(DFP) Var(rs6000_isa_flags) +Target Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions. mmulhw -Target Report Mask(MULHW) Var(rs6000_isa_flags) +Target Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions. mdlmzb -Target Report Mask(DLMZB) Var(rs6000_isa_flags) +Target Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction. mmultiple -Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) +Target Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions. ;; This option existed in the past, but now is always off. @@ -183,19 +183,19 @@ mstring Target RejectNegative Undocumented WarnRemoved msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) +Target RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point. mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) +Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point. mpopcntd -Target Report Mask(POPCNTD) Var(rs6000_isa_flags) +Target Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction. mfriz -Target Report Var(TARGET_FRIZ) Init(-1) Save +Target Var(TARGET_FRIZ) Init(-1) Save Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. mveclibabi= @@ -203,11 +203,11 @@ Target RejectNegative Joined Var(rs6000_veclibabi_name) Vector library ABI to use. mvsx -Target Report Mask(VSX) Var(rs6000_isa_flags) +Target Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions. mvsx-align-128 -Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save +Target Undocumented Var(TARGET_VSX_ALIGN_128) Save ; If -mvsx, set alignment to 128 bits instead of 32/64 mallow-movmisalign @@ -215,74 +215,74 @@ Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save ; Allow the movmisalign in DF/DI vectors mefficient-unaligned-vsx -Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) +Target Undocumented Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) ; Consider unaligned VSX vector and fp accesses to be efficient msched-groups -Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save +Target Undocumented Var(TARGET_SCHED_GROUPS) Init(-1) Save ; Explicitly set rs6000_sched_groups malways-hint -Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save +Target Undocumented Var(TARGET_ALWAYS_HINT) Init(-1) Save ; Explicitly set rs6000_always_hint malign-branch-targets -Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save +Target Undocumented Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save ; Explicitly set rs6000_align_branch_targets mno-update -Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) +Target RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions. mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) +Target RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions. msingle-pic-base -Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) +Target Var(TARGET_SINGLE_PIC_BASE) Init(0) Do not load the PIC register in function prologues. mavoid-indexed-addresses -Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save +Target Var(TARGET_AVOID_XFORM) Init(-1) Save Avoid generation of indexed load/store instructions when possible. msched-epilog Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save msched-prolog -Target Report Var(TARGET_SCHED_PROLOG) Save +Target Var(TARGET_SCHED_PROLOG) Save Schedule the start and end of the procedure. maix-struct-return -Target Report RejectNegative Var(aix_struct_return) Save +Target RejectNegative Var(aix_struct_return) Save Return all structures in memory (AIX default). msvr4-struct-return -Target Report RejectNegative Var(aix_struct_return,0) Save +Target RejectNegative Var(aix_struct_return,0) Save Return small structures in registers (SVR4 default). mxl-compat -Target Report Var(TARGET_XL_COMPAT) Save +Target Var(TARGET_XL_COMPAT) Save Conform more closely to IBM XLC semantics. mrecip -Target Report +Target Generate software reciprocal divide and square root for better throughput. mrecip= -Target Report RejectNegative Joined Var(rs6000_recip_name) +Target RejectNegative Joined Var(rs6000_recip_name) Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) +Target Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save +Target RejectNegative Var(TARGET_NO_FP_IN_TOC) Save Do not place floating point constants in TOC. mfp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save +Target RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save Place floating point constants in TOC. mno-sum-in-toc @@ -301,15 +301,15 @@ Place symbol+offset constants in TOC. ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) +Target Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure. mfull-toc -Target Report +Target Put everything in the regular TOC. mvrsave -Target Report Var(TARGET_ALTIVEC_VRSAVE) Save +Target Var(TARGET_ALTIVEC_VRSAVE) Save Generate VRSAVE instructions when generating AltiVec code. mvrsave=no @@ -321,11 +321,11 @@ Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %< Deprecated option. Use -mvrsave instead. mblock-move-inline-limit= -Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save +Target Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save Max number of bytes to move inline. mblock-ops-unaligned-vsx -Target Report Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags) +Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags) Generate unaligned VSX load/store for inline expansion of memcpy/memmove. mblock-ops-vector-pair @@ -333,25 +333,26 @@ Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags) Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove. mblock-compare-inline-limit= -Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save +Target Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save Max number of bytes to compare without loops. mblock-compare-inline-loop-limit= -Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save +Target Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save Max number of bytes to compare with loops. mstring-compare-inline-limit= -Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save +Target Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save Max number of bytes to compare. misel -Target Report Mask(ISEL) Var(rs6000_isa_flags) +Target Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions. mdebug= Target RejectNegative Joined -mdebug= Enable debug output. +; Altivec ABI mabi=altivec Target RejectNegative Var(rs6000_altivec_abi) Save Use the AltiVec ABI extensions. @@ -360,6 +361,16 @@ mabi=no-altivec Target RejectNegative Var(rs6000_altivec_abi, 0) Do not use the AltiVec ABI extensions. +; AIX Extended vector ABI +mabi=vec-extabi +Target RejectNegative Var(rs6000_aix_extabi, 1) Save +Use the AIX Vector Extended ABI. + +mabi=vec-default +Target RejectNegative Var(rs6000_aix_extabi, 0) +Do not use the AIX Vector Extended ABI. + +; PPC64 Linux ELF ABI mabi=elfv1 Target RejectNegative Var(rs6000_elf_abi, 1) Save Use the ELFv1 ABI. @@ -409,7 +420,7 @@ EnumValue Enum(rs6000_traceback_type) String(no) Value(traceback_none) mlongcall -Target Report Var(rs6000_default_long_calls) Save +Target Var(rs6000_default_long_calls) Save Avoid all range limits on call instructions. ; This option existed in the past, but now is always on. @@ -456,11 +467,11 @@ Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority Specify scheduling priority for dispatch slot restricted insns. mpointers-to-nested-functions -Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save +Target Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save Use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect -Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) +Target Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) Save the TOC in the prologue for indirect calls rather than inline. ; This option existed in the past, but now is always the same as -mvsx. @@ -468,7 +479,7 @@ mvsx-timode Target RejectNegative Undocumented Ignore mpower8-fusion -Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) +Target Mask(P8_FUSION) Var(rs6000_isa_flags) Fuse certain integer operations together for better performance on power8. mpower8-fusion-sign @@ -476,30 +487,42 @@ Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) Allow sign extension in fusion operations. mpower8-vector -Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) +Target Mask(P8_VECTOR) Var(rs6000_isa_flags) Use vector and scalar instructions added in ISA 2.07. +mpower10-fusion +Target Mask(P10_FUSION) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power10. + +mpower10-fusion-ld-cmpi +Target Undocumented Mask(P10_FUSION_LD_CMPI) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power10. + +mpower10-fusion-2logical +Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power10. + mcrypto -Target Report Mask(CRYPTO) Var(rs6000_isa_flags) +Target Mask(CRYPTO) Var(rs6000_isa_flags) Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. mdirect-move Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved mhtm -Target Report Mask(HTM) Var(rs6000_isa_flags) +Target Mask(HTM) Var(rs6000_isa_flags) Use ISA 2.07 transactional memory (HTM) instructions. mquad-memory -Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) +Target Mask(QUAD_MEMORY) Var(rs6000_isa_flags) Generate the quad word memory instructions (lq/stq). mquad-memory-atomic -Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) +Target Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) Generate the quad word memory atomic instructions (lqarx/stqcx). mcompat-align-parm -Target Report Var(rs6000_compat_align_parm) Init(0) Save +Target Var(rs6000_compat_align_parm) Init(0) Save Generate aggregate parameter passing code with at most 64-bit alignment. moptimize-swaps @@ -511,11 +534,11 @@ Target Undocumented Var(unroll_only_small_loops) Init(0) Save ; Use conservative small loop unrolling. mpower9-misc -Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) +Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags) Use certain scalar instructions added in ISA 3.0. mpower9-vector -Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) +Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags) Use vector instructions added in ISA 3.0. mpower9-minmax @@ -527,15 +550,15 @@ Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) Fuse medium/large code model toc references with the memory instruction. mmodulo -Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) +Target Undocumented Mask(MODULO) Var(rs6000_isa_flags) Generate the integer modulo instructions. mfloat128 -Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) +Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) Enable IEEE 128-bit floating point via the __float128 keyword. mfloat128-hardware -Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) +Target Mask(FLOAT128_HW) Var(rs6000_isa_flags) Enable using IEEE 128-bit floating point instructions. mfloat128-convert @@ -579,15 +602,15 @@ mpower10 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved mprefixed -Target Report Mask(PREFIXED) Var(rs6000_isa_flags) +Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. mpcrel -Target Report Mask(PCREL) Var(rs6000_isa_flags) +Target Mask(PCREL) Var(rs6000_isa_flags) Generate (do not generate) pc-relative memory addressing. mmma -Target Report Mask(MMA) Var(rs6000_isa_flags) +Target Mask(MMA) Var(rs6000_isa_flags) Generate (do not generate) MMA instructions. mrelative-jumptables diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index bbbecbe..56f21ab 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM RS64 processors. -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/rtems.h b/gcc/config/rs6000/rtems.h index 40db660..872cc28 100644 --- a/gcc/config/rs6000/rtems.h +++ b/gcc/config/rs6000/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a PowerPC using elf. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h index 7a66546..c3c65a7 100644 --- a/gcc/config/rs6000/secureplt.h +++ b/gcc/config/rs6000/secureplt.h @@ -1,5 +1,5 @@ /* Default to -msecure-plt. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/si2vmx.h b/gcc/config/rs6000/si2vmx.h index c5fd0e0..8471ff5 100644 --- a/gcc/config/rs6000/si2vmx.h +++ b/gcc/config/rs6000/si2vmx.h @@ -1,5 +1,5 @@ /* Cell BEA specific SPU intrinsics to PPU/VMX intrinsics - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/smmintrin.h b/gcc/config/rs6000/smmintrin.h index 4c0fc86..bdf6eb3 100644 --- a/gcc/config/rs6000/smmintrin.h +++ b/gcc/config/rs6000/smmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2018-2020 Free Software Foundation, Inc. +/* Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/spu2vmx.h b/gcc/config/rs6000/spu2vmx.h index 91d4d3a..65a7ba8 100644 --- a/gcc/config/rs6000/spu2vmx.h +++ b/gcc/config/rs6000/spu2vmx.h @@ -1,5 +1,5 @@ /* Cell SPU 2 VMX intrinsics header - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 5ad8880..11e4c03 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -1,5 +1,5 @@ ;; Machine description for PowerPC synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Geoffrey Keating. ;; This file is part of GCC. diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 9ade721..510abe1 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for PowerPC running System V.4 - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index b49ba26..7ab55c4 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -1,6 +1,6 @@ ; SYSV4 options for PPC port. ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. @@ -28,7 +28,7 @@ Target RejectNegative Joined Var(rs6000_sdata_name) -msdata=[none,data,sysv,eabi] Select method for sdata handling. mreadonly-in-sdata -Target Report Var(rs6000_readonly_in_sdata) Init(1) Save +Target Var(rs6000_readonly_in_sdata) Init(1) Save Allow readonly data in sdata. mtls-size= @@ -48,16 +48,16 @@ EnumValue Enum(rs6000_tls_size) String(64) Value(64) mbit-align -Target Report Var(TARGET_NO_BITFIELD_TYPE) Save +Target Var(TARGET_NO_BITFIELD_TYPE) Save Align to the base type of the bit-field. mstrict-align -Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) +Target Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field. Don't assume that unaligned accesses are handled by the system. mrelocatable -Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) +Target Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime. mrelocatable-lib @@ -65,19 +65,19 @@ Target Produce code relocatable at runtime. mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) +Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code. mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) +Target RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code. mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) +Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code. mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) +Target RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code. ;; FIXME: This does nothing. What should be done? @@ -99,11 +99,11 @@ Target RejectNegative No description yet. meabi -Target Report Mask(EABI) Var(rs6000_isa_flags) +Target Mask(EABI) Var(rs6000_isa_flags) Use EABI. mbit-word -Target Report Var(TARGET_NO_BITFIELD_WORD) Save +Target Var(TARGET_NO_BITFIELD_WORD) Save Allow bit-fields to cross word boundaries. mregnames @@ -141,11 +141,11 @@ Target RejectNegative No description yet. m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code. m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code. mnewlib @@ -153,17 +153,17 @@ Target RejectNegative No description yet. msecure-plt -Target Report RejectNegative Var(secure_plt, 1) Save +Target RejectNegative Var(secure_plt, 1) Save Generate code to use a non-exec PLT and GOT. mbss-plt -Target Report RejectNegative Var(secure_plt, 0) Save +Target RejectNegative Var(secure_plt, 0) Save Generate code for old exec BSS PLT. mpltseq -Target Report Var(rs6000_pltseq) Init(1) Save +Target Var(rs6000_pltseq) Init(1) Save Use inline plt sequences to implement long calls and -fno-plt. mgnu-attribute -Target Report Var(rs6000_gnu_attr) Init(1) Save +Target Var(rs6000_gnu_attr) Init(1) Save Emit .gnu_attribute tags. diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h index 3406f30..a9f4d65 100644 --- a/gcc/config/rs6000/sysv4le.h +++ b/gcc/config/rs6000/sysv4le.h @@ -1,6 +1,6 @@ /* Target definitions for GCC for a little endian PowerPC running System V.4 - Copyright (C) 1995-2020 Free Software Foundation, Inc. + Copyright (C) 1995-2021 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/t-aix52 b/gcc/config/rs6000/t-aix52 index 1a0413a..485ba50 100644 --- a/gcc/config/rs6000/t-aix52 +++ b/gcc/config/rs6000/t-aix52 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-aix64 b/gcc/config/rs6000/t-aix64 index 8134e19..1c180c2 100644 --- a/gcc/config/rs6000/t-aix64 +++ b/gcc/config/rs6000/t-aix64 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-fprules b/gcc/config/rs6000/t-fprules index df8da61..508ecbf 100644 --- a/gcc/config/rs6000/t-fprules +++ b/gcc/config/rs6000/t-fprules @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-freebsd64 b/gcc/config/rs6000/t-freebsd64 index 47a42d8..fce347c 100644 --- a/gcc/config/rs6000/t-freebsd64 +++ b/gcc/config/rs6000/t-freebsd64 @@ -1,6 +1,6 @@ #rs6000/t-freebsd64 -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-linux64 b/gcc/config/rs6000/t-linux64 index 264a7e2..e11a118 100644 --- a/gcc/config/rs6000/t-linux64 +++ b/gcc/config/rs6000/t-linux64 @@ -1,6 +1,6 @@ #rs6000/t-linux64 -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-lynx b/gcc/config/rs6000/t-lynx index 500ee61..136f9de 100644 --- a/gcc/config/rs6000/t-lynx +++ b/gcc/config/rs6000/t-lynx @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-netbsd b/gcc/config/rs6000/t-netbsd index cbe0d8f..3b4365a 100644 --- a/gcc/config/rs6000/t-netbsd +++ b/gcc/config/rs6000/t-netbsd @@ -1,6 +1,6 @@ # Support for NetBSD PowerPC ELF targets (SVR4 ABI). # -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppccomm b/gcc/config/rs6000/t-ppccomm index d33c1e9..5201eab 100644 --- a/gcc/config/rs6000/t-ppccomm +++ b/gcc/config/rs6000/t-ppccomm @@ -1,6 +1,6 @@ # Common support for PowerPC ELF targets (both EABI and SVR4). # -# Copyright (C) 1996-2020 Free Software Foundation, Inc. +# Copyright (C) 1996-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppcendian b/gcc/config/rs6000/t-ppcendian index e475602..38516c0 100644 --- a/gcc/config/rs6000/t-ppcendian +++ b/gcc/config/rs6000/t-ppcendian @@ -1,6 +1,6 @@ # Multilibs for powerpc embedded ELF targets with altivec. # -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppcgas b/gcc/config/rs6000/t-ppcgas index 53e3c18..7432d35 100644 --- a/gcc/config/rs6000/t-ppcgas +++ b/gcc/config/rs6000/t-ppcgas @@ -1,6 +1,6 @@ # Multilibs for powerpc embedded ELF targets. # -# Copyright (C) 1995-2020 Free Software Foundation, Inc. +# Copyright (C) 1995-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 1ddb572..e3a58bf 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -1,6 +1,6 @@ # General rules that all rs6000/ targets must have. # -# Copyright (C) 1995-2020 Free Software Foundation, Inc. +# Copyright (C) 1995-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -47,6 +47,9 @@ rs6000-call.o: $(srcdir)/config/rs6000/rs6000-call.c $(COMPILE) $< $(POSTCOMPILE) +$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl + $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md + $(srcdir)/config/rs6000/rs6000-tables.opt: $(srcdir)/config/rs6000/genopt.sh \ $(srcdir)/config/rs6000/rs6000-cpus.def $(SHELL) $(srcdir)/config/rs6000/genopt.sh $(srcdir)/config/rs6000 > \ @@ -86,4 +89,5 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/mma.md \ $(srcdir)/config/rs6000/crypto.md \ $(srcdir)/config/rs6000/htm.md \ - $(srcdir)/config/rs6000/dfp.md + $(srcdir)/config/rs6000/dfp.md \ + $(srcdir)/config/rs6000/fusion.md diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems index 8065a09..1ca3f0b 100644 --- a/gcc/config/rs6000/t-rtems +++ b/gcc/config/rs6000/t-rtems @@ -1,6 +1,6 @@ # Multilibs for powerpc RTEMS targets. # -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-vxworks b/gcc/config/rs6000/t-vxworks index a0120b1..68b2415 100644 --- a/gcc/config/rs6000/t-vxworks +++ b/gcc/config/rs6000/t-vxworks @@ -1,6 +1,6 @@ # Multilibs for VxWorks. # -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index b14311e..df6c1a3 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -1,5 +1,5 @@ ;; Pipeline description for the AppliedMicro Titan core. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Theobroma Systems Design und Consulting GmbH ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/tmmintrin.h b/gcc/config/rs6000/tmmintrin.h index 9763a32..9715112 100644 --- a/gcc/config/rs6000/tmmintrin.h +++ b/gcc/config/rs6000/tmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/vec_types.h b/gcc/config/rs6000/vec_types.h index a4e45e6..0f78cac 100644 --- a/gcc/config/rs6000/vec_types.h +++ b/gcc/config/rs6000/vec_types.h @@ -1,5 +1,5 @@ /* Cell single token vector types - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 7aab188..e5191bd 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -3,7 +3,7 @@ ;; expander, and the actual vector instructions will be in altivec.md and ;; vsx.md -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> ;; This file is part of GCC. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 947631d..3e05186 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1,5 +1,5 @@ ;; VSX patterns. -;; Copyright (C) 2009-2020 Free Software Foundation, Inc. +;; Copyright (C) 2009-2021 Free Software Foundation, Inc. ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> ;; This file is part of GCC. @@ -267,6 +267,10 @@ (define_mode_iterator VSX_MM [V16QI V8HI V4SI V2DI V1TI]) (define_mode_iterator VSX_MM4 [V16QI V8HI V4SI V2DI]) +;; Longer vec int modes for rotate/mask ops +;; and Vector Integer Multiply/Divide/Modulo Instructions +(define_mode_iterator VIlong [V2DI V4SI]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -363,6 +367,8 @@ UNSPEC_INSERTR UNSPEC_REPLACE_ELT UNSPEC_REPLACE_UN + UNSPEC_VDIVES + UNSPEC_VDIVEU ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -1623,28 +1629,35 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op3 = gen_reg_rtx (DImode); - rtx op4 = gen_reg_rtx (DImode); - rtx op5 = gen_reg_rtx (DImode); - emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); - emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); - if (TARGET_POWERPC64) - emit_insn (gen_muldi3 (op5, op3, op4)); - else - { - rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); - emit_move_insn (op5, ret); - } - emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); - emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); - if (TARGET_POWERPC64) - emit_insn (gen_muldi3 (op3, op3, op4)); + + if (TARGET_POWER10) + emit_insn (gen_mulv2di3 (op0, op1, op2) ); + else { - rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); - emit_move_insn (op3, ret); + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + if (TARGET_POWERPC64) + emit_insn (gen_muldi3 (op5, op3, op4)); + else + { + rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); + emit_move_insn (op5, ret); + } + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + if (TARGET_POWERPC64) + emit_insn (gen_muldi3 (op3, op3, op4)); + else + { + rtx ret = expand_mult (DImode, op3, op4, NULL, 0, false); + emit_move_insn (op3, ret); + } + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); } - emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); DONE; } [(set_attr "type" "mul")]) @@ -1718,37 +1731,46 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op3 = gen_reg_rtx (DImode); - rtx op4 = gen_reg_rtx (DImode); - rtx op5 = gen_reg_rtx (DImode); - emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); - emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); - if (TARGET_POWERPC64) - emit_insn (gen_udivdi3 (op5, op3, op4)); - else - { - rtx libfunc = optab_libfunc (udiv_optab, DImode); - rtx target = emit_library_call_value (libfunc, - op5, LCT_NORMAL, DImode, - op3, DImode, - op4, DImode); - emit_move_insn (op5, target); - } - emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); - emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); - if (TARGET_POWERPC64) - emit_insn (gen_udivdi3 (op3, op3, op4)); - else - { - rtx libfunc = optab_libfunc (udiv_optab, DImode); - rtx target = emit_library_call_value (libfunc, - op3, LCT_NORMAL, DImode, - op3, DImode, - op4, DImode); - emit_move_insn (op3, target); - } - emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); - DONE; + + if (TARGET_POWER10) + emit_insn (gen_udivv2di3 (op0, op1, op2) ); + else + { + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + + if (TARGET_POWERPC64) + emit_insn (gen_udivdi3 (op5, op3, op4)); + else + { + rtx libfunc = optab_libfunc (udiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op5, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op5, target); + } + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + + if (TARGET_POWERPC64) + emit_insn (gen_udivdi3 (op3, op3, op4)); + else + { + rtx libfunc = optab_libfunc (udiv_optab, DImode); + rtx target = emit_library_call_value (libfunc, + op3, LCT_NORMAL, DImode, + op3, DImode, + op4, DImode); + emit_move_insn (op3, target); + } + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); + } + DONE; } [(set_attr "type" "div")]) @@ -6104,3 +6126,92 @@ "TARGET_POWER10" "vexpand<wd>m %0,%1" [(set_attr "type" "vecsimple")]) + +(define_insn "dives_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")] + UNSPEC_VDIVES))] + "TARGET_POWER10" + "vdives<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "diveu_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")] + UNSPEC_VDIVEU))] + "TARGET_POWER10" + "vdiveu<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "div<mode>3" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (div:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")))] + "TARGET_POWER10" + "vdivs<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "udiv<mode>3" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (udiv:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")))] + "TARGET_POWER10" + "vdivu<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "mods_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")))] + "TARGET_POWER10" + "vmods<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "modu_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") + (match_operand:VIlong 2 "vsx_register_operand" "v")))] + "TARGET_POWER10" + "vmodu<wd> %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "<bits>")]) + +(define_insn "mulhs_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (mult:VIlong (ashiftrt + (match_operand:VIlong 1 "vsx_register_operand" "v") + (const_int 32)) + (ashiftrt + (match_operand:VIlong 2 "vsx_register_operand" "v") + (const_int 32))))] + "TARGET_POWER10" + "vmulhs<wd> %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "mulhu_<mode>" + [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") + (us_mult:VIlong (ashiftrt + (match_operand:VIlong 1 "vsx_register_operand" "v") + (const_int 32)) + (ashiftrt + (match_operand:VIlong 2 "vsx_register_operand" "v") + (const_int 32))))] + "TARGET_POWER10" + "vmulhu<wd> %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +;; Vector multiply low double word +(define_insn "mulv2di3" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v") + (mult:V2DI (match_operand:V2DI 1 "vsx_register_operand" "v") + (match_operand:V2DI 2 "vsx_register_operand" "v")))] + "TARGET_POWER10" + "vmulld %0,%1,%2" + [(set_attr "type" "veccomplex")]) diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 51a3250..5facbbb 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Vxworks PowerPC version. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/rs6000/vxworksae.h b/gcc/config/rs6000/vxworksae.h index 001c2cc..51c7f47 100644 --- a/gcc/config/rs6000/vxworksae.h +++ b/gcc/config/rs6000/vxworksae.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. PowerPC VxworksAE version. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/rs6000/vxworksmils.h b/gcc/config/rs6000/vxworksmils.h index 8fb54a7..6d68e7c 100644 --- a/gcc/config/rs6000/vxworksmils.h +++ b/gcc/config/rs6000/vxworksmils.h @@ -1,7 +1,7 @@ /* PowerPC VxWorks MILS target definitions for GNU compiler. Overrides on top of the canonical VxWorks definitions. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/x86intrin.h b/gcc/config/rs6000/x86intrin.h index 406e4eb..6ad2bfc 100644 --- a/gcc/config/rs6000/x86intrin.h +++ b/gcc/config/rs6000/x86intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2020 Free Software Foundation, Inc. +/* Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h index fe6221a..c016678 100644 --- a/gcc/config/rs6000/xcoff.h +++ b/gcc/config/rs6000/xcoff.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for some generic XCOFF file format - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/xmmintrin.h b/gcc/config/rs6000/xmmintrin.h index 5a99680..ae1a33e 100644 --- a/gcc/config/rs6000/xmmintrin.h +++ b/gcc/config/rs6000/xmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2020 Free Software Foundation, Inc. +/* Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rtems.h b/gcc/config/rtems.h index 30ad625..313988d 100644 --- a/gcc/config/rtems.h +++ b/gcc/config/rtems.h @@ -1,5 +1,5 @@ /* Configuration common to all targets running RTEMS. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -36,11 +36,11 @@ */ #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{!qrtems:crt0%O%s} " \ -"%{qrtems:%{!nostdlib:%{!nostartfiles:" RTEMS_STARTFILE_SPEC "}}}" +"%{qrtems:" RTEMS_STARTFILE_SPEC "}" #undef ENDFILE_SPEC #define ENDFILE_SPEC \ -"%{qrtems:%{!nostdlib:%{!nostartfiles:" RTEMS_ENDFILE_SPEC "}}}" +"%{qrtems:" RTEMS_ENDFILE_SPEC " %{!qnolinkcmds:-T linkcmds%s}}" /* * Some targets do not set up LIB_SPECS, override it, here. @@ -49,9 +49,7 @@ #undef LIB_SPEC #define LIB_SPEC "%{!qrtems:" STD_LIB_SPEC "} " \ -"%{qrtems:%{!nostdlib:%{!nodefaultlibs:" \ -"--start-group -lrtemsbsp -lrtemscpu -latomic -lc -lgcc --end-group} " \ -"%{!qnolinkcmds:-T linkcmds%s}}}" +"%{qrtems:--start-group -lrtemsbsp -lrtemscpu -latomic -lc -lgcc --end-group}" #define TARGET_POSIX_IO diff --git a/gcc/config/rtems.opt b/gcc/config/rtems.opt index 7beeb31..e05b848 100644 --- a/gcc/config/rtems.opt +++ b/gcc/config/rtems.opt @@ -1,6 +1,6 @@ ; RTEMS options. -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rx/constraints.md b/gcc/config/rx/constraints.md index 30d716f..84b9d8d 100644 --- a/gcc/config/rx/constraints.md +++ b/gcc/config/rx/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas RX. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/rx/elf.opt b/gcc/config/rx/elf.opt index f130e79..86800dd 100644 --- a/gcc/config/rx/elf.opt +++ b/gcc/config/rx/elf.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RX port of GCC. -; Copyright (C) 2008-2020 Free Software Foundation, Inc. +; Copyright (C) 2008-2021 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. @@ -28,7 +28,7 @@ Use the simulator runtime. ;--------------------------------------------------- mas100-syntax -Target Mask(AS100_SYNTAX) Report +Target Mask(AS100_SYNTAX) Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax. ;--------------------------------------------------- diff --git a/gcc/config/rx/predicates.md b/gcc/config/rx/predicates.md index e9a8e0d..f6684ef 100644 --- a/gcc/config/rx/predicates.md +++ b/gcc/config/rx/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas RX. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/rx/rx-modes.def b/gcc/config/rx/rx-modes.def index 3be9080..5b68e6a 100644 --- a/gcc/config/rx/rx-modes.def +++ b/gcc/config/rx/rx-modes.def @@ -1,5 +1,5 @@ /* Definitions of target specific machine modes for the RX. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx-opts.h b/gcc/config/rx/rx-opts.h index 4b84307..88af3ef 100644 --- a/gcc/config/rx/rx-opts.h +++ b/gcc/config/rx/rx-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the Renesas RX processor. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h index 6927b91..c517072 100644 --- a/gcc/config/rx/rx-protos.h +++ b/gcc/config/rx/rx-protos.h @@ -1,5 +1,5 @@ /* Exported function prototypes from the Renesas RX backend. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index dfb4bd4..af54ccc 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Renesas RX processors. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index 2f3d97a..8e23e31 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the Renesas RX processor. - Copyright (C) 2008-2020 Free Software Foundation, Inc. + Copyright (C) 2008-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 6e5c546..b76fce9 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RX processors -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt index d6426f4..d476f19 100644 --- a/gcc/config/rx/rx.opt +++ b/gcc/config/rx/rx.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RX port of GCC. -; Copyright (C) 2008-2020 Free Software Foundation, Inc. +; Copyright (C) 2008-2021 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. @@ -25,11 +25,11 @@ config/rx/rx-opts.h ; The default is -fpu -m32bit-doubles. m64bit-doubles -Target RejectNegative Mask(64BIT_DOUBLES) Report +Target RejectNegative Mask(64BIT_DOUBLES) Store doubles in 64 bits. m32bit-doubles -Target RejectNegative InverseMask(64BIT_DOUBLES) Report +Target RejectNegative InverseMask(64BIT_DOUBLES) Stores doubles in 32 bits. This is the default. nofpu @@ -37,16 +37,16 @@ Target RejectNegative Alias(mnofpu) Disable the use of RX FPU instructions. mnofpu -Target RejectNegative Mask(NO_USE_FPU) Report Undocumented +Target RejectNegative Mask(NO_USE_FPU) Undocumented fpu -Target RejectNegative InverseMask(NO_USE_FPU) Report +Target RejectNegative InverseMask(NO_USE_FPU) Enable the use of RX FPU instructions. This is the default. ;--------------------------------------------------- mcpu= -Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600) +Target RejectNegative Joined Var(rx_cpu_type) ToLower Enum(rx_cpu_types) Init(RX600) Specify the target RX cpu type. Enum @@ -67,11 +67,11 @@ Enum(rx_cpu_types) String(rx100) Value(RX100) ;--------------------------------------------------- mbig-endian-data -Target RejectNegative Mask(BIG_ENDIAN_DATA) Report +Target RejectNegative Mask(BIG_ENDIAN_DATA) Data is stored in big-endian format. mlittle-endian-data -Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report +Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Data is stored in little-endian format. (Default). ;--------------------------------------------------- @@ -113,33 +113,33 @@ Enables Position-Independent-Data (PID) mode. ;--------------------------------------------------- mwarn-multiple-fast-interrupts -Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning +Target Var(rx_warn_multiple_fast_interrupts) Init(1) Warning Warn when multiple, different, fast interrupt handlers are in the compilation unit. ;--------------------------------------------------- mgcc-abi -Target RejectNegative Report Mask(GCC_ABI) +Target RejectNegative Mask(GCC_ABI) Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits. mrx-abi -Target RejectNegative Report InverseMask(GCC_ABI) +Target RejectNegative InverseMask(GCC_ABI) Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default. ;--------------------------------------------------- mlra -Target Report Mask(ENABLE_LRA) +Target Mask(ENABLE_LRA) Enable the use of the LRA register allocator. ;--------------------------------------------------- mallow-string-insns -Target Report Var(rx_allow_string_insns) Init(1) +Target Var(rx_allow_string_insns) Init(1) Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default. ;--------------------------------------------------- mjsr -Target Report Mask(JSR) +Target Mask(JSR) Always use JSR, never BSR, for calls. diff --git a/gcc/config/rx/t-rx b/gcc/config/rx/t-rx index 5890a95..3e61d76 100644 --- a/gcc/config/rx/t-rx +++ b/gcc/config/rx/t-rx @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the Renesas RX target. -# Copyright (C) 2008-2020 Free Software Foundation, Inc. +# Copyright (C) 2008-2021 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/s390/2064.md b/gcc/config/s390/2064.md index 6fd96bd4..5da2da4 100644 --- a/gcc/config/s390/2064.md +++ b/gcc/config/s390/2064.md @@ -1,5 +1,5 @@ ;; Scheduling description for z900 (cpu 2064). -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/2084.md b/gcc/config/s390/2084.md index 375d384..7d51968 100644 --- a/gcc/config/s390/2084.md +++ b/gcc/config/s390/2084.md @@ -1,5 +1,5 @@ ;; Scheduling description for z990 (cpu 2084). -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md index 08d7638..a33961e 100644 --- a/gcc/config/s390/2097.md +++ b/gcc/config/s390/2097.md @@ -1,5 +1,5 @@ ;; Scheduling description for z10 (cpu 2097). -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com). diff --git a/gcc/config/s390/2817.md b/gcc/config/s390/2817.md index 11cc4b8..855a1c2 100644 --- a/gcc/config/s390/2817.md +++ b/gcc/config/s390/2817.md @@ -1,5 +1,5 @@ ;; Scheduling description for z196 (cpu 2817). -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; Contributed by Christian Borntraeger (Christian.Borntraeger@de.ibm.com) ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md index 705992a..fe31ba8 100644 --- a/gcc/config/s390/2827.md +++ b/gcc/config/s390/2827.md @@ -1,5 +1,5 @@ ;; Scheduling description for zEC12 (cpu 2827). -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/2964.md b/gcc/config/s390/2964.md index 80c0b92..af8b8b1 100644 --- a/gcc/config/s390/2964.md +++ b/gcc/config/s390/2964.md @@ -1,5 +1,5 @@ ;; Scheduling description for z13. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/3906.md b/gcc/config/s390/3906.md index 83dc160..71a6dc2 100644 --- a/gcc/config/s390/3906.md +++ b/gcc/config/s390/3906.md @@ -1,5 +1,5 @@ ;; Scheduling description for z14. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; Contributed by Robin Dapp (rdapp@linux.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/8561.md b/gcc/config/s390/8561.md index 38d6c42..9321a8e 100644 --- a/gcc/config/s390/8561.md +++ b/gcc/config/s390/8561.md @@ -1,5 +1,5 @@ ;; Scheduling description for z15. -;; Copyright (C) 2019-2020 Free Software Foundation, Inc. +;; Copyright (C) 2019-2021 Free Software Foundation, Inc. ;; Contributed by Robin Dapp (rdapp@linux.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md index 0b05c5c..6db084b 100644 --- a/gcc/config/s390/constraints.md +++ b/gcc/config/s390/constraints.md @@ -1,5 +1,5 @@ ;; Constraints definitions belonging to the gcc backend for IBM S/390. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; Written by Wolfgang Gellerich, using code and information found in ;; files s390.md, s390.h, and s390.c. ;; diff --git a/gcc/config/s390/driver-native.c b/gcc/config/s390/driver-native.c index 06bef40..4a065a5 100644 --- a/gcc/config/s390/driver-native.c +++ b/gcc/config/s390/driver-native.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/s390/htmintrin.h b/gcc/config/s390/htmintrin.h index dce293e..f796e92 100644 --- a/gcc/config/s390/htmintrin.h +++ b/gcc/config/s390/htmintrin.h @@ -1,5 +1,5 @@ /* GNU compiler hardware transactional execution intrinsics - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/htmxlintrin.h b/gcc/config/s390/htmxlintrin.h index 6acb64d..b4868fb 100644 --- a/gcc/config/s390/htmxlintrin.h +++ b/gcc/config/s390/htmxlintrin.h @@ -1,5 +1,5 @@ /* XL compiler hardware transactional execution intrinsics - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h index 6919b46..daa48fd 100644 --- a/gcc/config/s390/linux.h +++ b/gcc/config/s390/linux.h @@ -1,5 +1,5 @@ /* Definitions for Linux for S/390. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index 8b8043d..15093cb 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for S/390 and zSeries. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). ;; diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def index 76ae8fe..a2b7d4a 100644 --- a/gcc/config/s390/s390-builtin-types.def +++ b/gcc/config/s390/s390-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin type definitions for IBM S/390 and zSeries - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index c69573d..deb205b 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -1,5 +1,5 @@ /* Builtin definitions for IBM S/390 and zSeries - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-builtins.h b/gcc/config/s390/s390-builtins.h index 18e5208..69fc736 100644 --- a/gcc/config/s390/s390-builtins.h +++ b/gcc/config/s390/s390-builtins.h @@ -1,5 +1,5 @@ /* Common data structures used for builtin handling on S/390. - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-c.c b/gcc/config/s390/s390-c.c index 8e5f2c9..a5f5f56 100644 --- a/gcc/config/s390/s390-c.c +++ b/gcc/config/s390/s390-c.c @@ -1,6 +1,6 @@ /* Language specific subroutines used for code generation on IBM S/390 and zSeries - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). @@ -294,9 +294,9 @@ s390_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) /* Helper function that defines or undefines macros. If SET is true, the macro MACRO_DEF is defined. If SET is false, the macro MACRO_UNDEF is undefined. Nothing is done if SET and WAS_SET have the same value. */ +template <typename F> static void -s390_def_or_undef_macro (cpp_reader *pfile, - unsigned int mask, +s390_def_or_undef_macro (cpp_reader *pfile, F is_set, const struct cl_target_option *old_opts, const struct cl_target_option *new_opts, const char *macro_def, const char *macro_undef) @@ -304,8 +304,8 @@ s390_def_or_undef_macro (cpp_reader *pfile, bool was_set; bool set; - was_set = (!old_opts) ? false : old_opts->x_target_flags & mask; - set = new_opts->x_target_flags & mask; + was_set = (!old_opts) ? false : is_set (old_opts); + set = is_set (new_opts); if (was_set == set) return; if (set) @@ -314,6 +314,19 @@ s390_def_or_undef_macro (cpp_reader *pfile, cpp_undef (pfile, macro_undef); } +struct target_flag_set_p +{ + target_flag_set_p (unsigned int mask) : m_mask (mask) {} + + bool + operator() (const struct cl_target_option *opts) const + { + return opts->x_target_flags & m_mask; + } + + unsigned int m_mask; +}; + /* Internal function to either define or undef the appropriate system macros. */ static void @@ -321,18 +334,18 @@ s390_cpu_cpp_builtins_internal (cpp_reader *pfile, struct cl_target_option *opts, const struct cl_target_option *old_opts) { - s390_def_or_undef_macro (pfile, MASK_OPT_HTM, old_opts, opts, - "__HTM__", "__HTM__"); - s390_def_or_undef_macro (pfile, MASK_OPT_VX, old_opts, opts, - "__VX__", "__VX__"); - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "__VEC__=10303", "__VEC__"); - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "__vector=__attribute__((vector_size(16)))", + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_OPT_HTM), old_opts, + opts, "__HTM__", "__HTM__"); + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_OPT_VX), old_opts, + opts, "__VX__", "__VX__"); + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), old_opts, + opts, "__VEC__=10303", "__VEC__"); + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), old_opts, + opts, "__vector=__attribute__((vector_size(16)))", "__vector__"); - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "__bool=__attribute__((s390_vector_bool)) unsigned", - "__bool"); + s390_def_or_undef_macro ( + pfile, target_flag_set_p (MASK_ZVECTOR), old_opts, opts, + "__bool=__attribute__((s390_vector_bool)) unsigned", "__bool"); { char macro_def[64]; gcc_assert (s390_arch != PROCESSOR_NATIVE); @@ -340,16 +353,20 @@ s390_cpu_cpp_builtins_internal (cpp_reader *pfile, cpp_undef (pfile, "__ARCH__"); cpp_define (pfile, macro_def); } + s390_def_or_undef_macro ( + pfile, + [] (const struct cl_target_option *opts) { return TARGET_VXE_P (opts); }, + old_opts, opts, "__LONG_DOUBLE_VX__", "__LONG_DOUBLE_VX__"); if (!flag_iso) { - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "__VECTOR_KEYWORD_SUPPORTED__", + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), + old_opts, opts, "__VECTOR_KEYWORD_SUPPORTED__", "__VECTOR_KEYWORD_SUPPORTED__"); - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "vector=vector", "vector"); - s390_def_or_undef_macro (pfile, MASK_ZVECTOR, old_opts, opts, - "bool=bool", "bool"); + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), + old_opts, opts, "vector=vector", "vector"); + s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), + old_opts, opts, "bool=bool", "bool"); if (TARGET_ZVECTOR_P (opts->x_target_flags) && __vector_keyword == NULL) { __vector_keyword = get_identifier ("__vector"); diff --git a/gcc/config/s390/s390-d.c b/gcc/config/s390/s390-d.c index 5a70e06..155144c 100644 --- a/gcc/config/s390/s390-d.c +++ b/gcc/config/s390/s390-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the IBM S/390 and zSeries architectures. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def index 316ca5c..6d814fc 100644 --- a/gcc/config/s390/s390-modes.def +++ b/gcc/config/s390/s390-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390 - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/s390-opts.h b/gcc/config/s390/s390-opts.h index f3907d6..d575180 100644 --- a/gcc/config/s390/s390-opts.h +++ b/gcc/config/s390/s390-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IBM S/390. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/s390/s390-passes.def b/gcc/config/s390/s390-passes.def index b5d51c9..86c77e1 100644 --- a/gcc/config/s390/s390-passes.def +++ b/gcc/config/s390/s390-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for S/390. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h index eb10c3f..acbdf66 100644 --- a/gcc/config/s390/s390-protos.h +++ b/gcc/config/s390/s390-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 2f83988..9d2cee9 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM S/390 and zSeries - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com) and Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index bc579a3..2da768d 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390 - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). Andreas Krebbel (Andreas.Krebbel@de.ibm.com) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index d6d8965..3f96f5f 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. -;; Copyright (C) 1999-2020 Free Software Foundation, Inc. +;; Copyright (C) 1999-2021 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com) and ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt index 0afcea3..de7207e 100644 --- a/gcc/config/s390/s390.opt +++ b/gcc/config/s390/s390.opt @@ -1,6 +1,6 @@ ; Options for the S/390 / zSeries port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -44,11 +44,11 @@ Variable long s390_cost_pointer m31 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) 31 bit ABI. m64 -Target Report RejectNegative Negative(m31) Mask(64BIT) +Target RejectNegative Negative(m31) Mask(64BIT) 64 bit ABI. march= @@ -119,27 +119,27 @@ EnumValue Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly mbackchain -Target Report Mask(BACKCHAIN) Save +Target Mask(BACKCHAIN) Save Maintain backchain pointer. mdebug -Target Report Mask(DEBUG_ARG) Save +Target Mask(DEBUG_ARG) Save Additional debug prints. mesa -Target Report RejectNegative Negative(mzarch) InverseMask(ZARCH) +Target RejectNegative Negative(mzarch) InverseMask(ZARCH) ESA/390 architecture. mhard-dfp -Target Report Mask(HARD_DFP) Save +Target Mask(HARD_DFP) Save Enable decimal floating point hardware support. mhard-float -Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save +Target RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Save Enable hardware floating point. mhotpatch= -Target RejectNegative Report Joined Var(s390_deferred_options) Defer +Target RejectNegative Joined Var(s390_deferred_options) Defer Takes two non-negative integer numbers separated by a comma. Prepend the function label with the number of two-byte Nop instructions indicated by the first. Append Nop instructions @@ -149,31 +149,31 @@ label. Nop instructions of the largest possible size are used size. Using 0 for both values disables hotpatching. mlong-double-128 -Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128) +Target RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128) Use 128-bit long double. mlong-double-64 -Target Report RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128) +Target RejectNegative Negative(mlong-double-128) InverseMask(LONG_DOUBLE_128) Use 64-bit long double. mhtm -Target Report Mask(OPT_HTM) Save +Target Mask(OPT_HTM) Save Use hardware transactional execution instructions. mvx -Target Report Mask(OPT_VX) Save +Target Mask(OPT_VX) Save Use hardware vector facility instructions and enable the vector ABI. mpacked-stack -Target Report Mask(PACKED_STACK) Save +Target Mask(PACKED_STACK) Save Use packed stack layout. msmall-exec -Target Report Mask(SMALL_EXEC) Save +Target Mask(SMALL_EXEC) Save Use bras for executable < 64k. msoft-float -Target Report RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save +Target RejectNegative Negative(mhard-float) Mask(SOFT_FLOAT) Save Disable hardware floating point. mstack-guard= @@ -197,11 +197,11 @@ Target RejectNegative Joined Enum(processor_type) Var(s390_tune) Init(PROCESSOR_ Schedule code for given CPU. mmvcle -Target Report Mask(MVCLE) Save +Target Mask(MVCLE) Save Use the mvcle instruction for block moves. mzvector -Target Report Mask(ZVECTOR) Save +Target Mask(ZVECTOR) Save Enable the z vector language extension providing the context-sensitive vector macro and enable the Altivec-style builtins in vecintrin.h. @@ -214,31 +214,31 @@ Target RejectNegative Joined UInteger Var(s390_warn_framesize) Save Warn if a single function's framesize exceeds the given framesize. mzarch -Target Report RejectNegative Negative(mesa) Mask(ZARCH) +Target RejectNegative Negative(mesa) Mask(ZARCH) z/Architecture. mbranch-cost= -Target Report Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save +Target Joined RejectNegative UInteger Var(s390_branch_cost) Init(1) Save Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 1. mlra -Target Report Var(s390_lra_flag) Init(1) Save +Target Var(s390_lra_flag) Init(1) Save Use LRA instead of reload. mpic-data-is-text-relative -Target Report Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) +Target Var(s390_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) Assume data segments are relative to text segment. mindirect-branch= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch) Init(indirect_branch_keep) Wrap all indirect branches into execute in order to disable branch prediction. mindirect-branch-jump= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_jump) Init(indirect_branch_keep) Wrap indirect table jumps and computed gotos into execute in order to disable branch prediction. Using thunk or thunk-extern with this option requires the thunks to be considered signal handlers to order to @@ -246,22 +246,22 @@ generate correct CFI. For environments where unwinding (e.g. for exceptions) is required please use thunk-inline instead. mindirect-branch-call= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_indirect_branch_call) Init(indirect_branch_keep) Wrap all indirect calls into execute in order to disable branch prediction. mfunction-return= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return) Init(indirect_branch_keep) Wrap all indirect return branches into execute in order to disable branch prediction. mfunction-return-mem= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_mem) Init(indirect_branch_keep) Wrap indirect return branches into execute in order to disable branch prediction. This affects only branches where the return address is going to be restored from memory. mfunction-return-reg= -Target Report RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep) +Target RejectNegative Joined Enum(indirect_branch) Var(s390_function_return_reg) Init(indirect_branch_keep) Wrap indirect return branches into execute in order to disable branch prediction. This affects only branches where the return address doesn't need to be restored from memory. @@ -283,7 +283,7 @@ EnumValue Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) mindirect-branch-table -Target Report Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE) +Target Var(s390_indirect_branch_table) Init(TARGET_DEFAULT_INDIRECT_BRANCH_TABLE) Generate sections .s390_indirect_jump, .s390_indirect_call, .s390_return_reg, and .s390_return_mem to contain the indirect branch locations which have been patched as part of using one of the @@ -292,21 +292,21 @@ consist of an array of 32 bit elements. Each entry holds the offset from the entry to the patched location. mfentry -Target Report Var(flag_fentry) +Target Var(flag_fentry) Emit profiling counter call at function entry before prologue. The compiled code will require a 64-bit CPU and glibc 2.29 or newer to run. mrecord-mcount -Target Report Var(flag_record_mcount) +Target Var(flag_record_mcount) Generate __mcount_loc section with all _mcount and __fentry__ calls. mnop-mcount -Target Report Var(flag_nop_mcount) +Target Var(flag_nop_mcount) Generate mcount/__fentry__ calls as nops. To activate they need to be patched in. mvx-long-double-fma -Target Report Undocumented Var(flag_vx_long_double_fma) +Target Undocumented Var(flag_vx_long_double_fma) Emit fused multiply-add instructions for long doubles in vector registers (wfmaxb, wfmsxb, wfnmaxb, wfnmsxb). Reassociation pass does not handle fused multiply-adds, therefore code generated by the middle-end is prone to diff --git a/gcc/config/s390/s390intrin.h b/gcc/config/s390/s390intrin.h index 7c33aa5..e108bd1 100644 --- a/gcc/config/s390/s390intrin.h +++ b/gcc/config/s390/s390intrin.h @@ -1,5 +1,5 @@ /* S/390 System z specific intrinsics - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/s390x.h b/gcc/config/s390/s390x.h index 7cb59d7..f6efc57 100644 --- a/gcc/config/s390/s390x.h +++ b/gcc/config/s390/s390x.h @@ -1,5 +1,5 @@ /* Definitions of target machine for IBM zSeries 64-bit - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md index 29339a0..384af11 100644 --- a/gcc/config/s390/subst.md +++ b/gcc/config/s390/subst.md @@ -1,6 +1,6 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. ;; Subst patterns. -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/t-s390 b/gcc/config/s390/t-s390 index 979eace..781484d 100644 --- a/gcc/config/s390/t-s390 +++ b/gcc/config/s390/t-s390 @@ -1,4 +1,4 @@ -# Copyright (C) 2015-2020 Free Software Foundation, Inc. +# Copyright (C) 2015-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/s390/tpf.h b/gcc/config/s390/tpf.h index 22adf27..7696810 100644 --- a/gcc/config/s390/tpf.h +++ b/gcc/config/s390/tpf.h @@ -1,5 +1,5 @@ /* Definitions for target OS TPF for GNU compiler, for IBM S/390 hardware - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. Contributed by P.J. Darcy (darcypj@us.ibm.com), Hartmut Penner (hpenner@de.ibm.com), and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/tpf.md b/gcc/config/s390/tpf.md index 19c53a1..297e9d1 100644 --- a/gcc/config/s390/tpf.md +++ b/gcc/config/s390/tpf.md @@ -1,5 +1,5 @@ ;; S390 TPF-OS specific machine patterns -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/s390/tpf.opt b/gcc/config/s390/tpf.opt index 9876a55..f13558b 100644 --- a/gcc/config/s390/tpf.opt +++ b/gcc/config/s390/tpf.opt @@ -1,6 +1,6 @@ ; Options for the TPF-OS port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,29 +19,29 @@ ; <http://www.gnu.org/licenses/>. mtpf-trace -Target Report Mask(TPF_PROFILING) +Target Mask(TPF_PROFILING) Enable TPF-OS tracing code. mtpf-trace-hook-prologue-check= -Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK) +Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_check) Init(TPF_TRACE_PROLOGUE_CHECK) Set the trace check address for prologue tpf hook mtpf-trace-hook-prologue-target= -Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET) +Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_prologue_target) Init(TPF_TRACE_PROLOGUE_TARGET) Set the trace jump address for prologue tpf hook mtpf-trace-hook-epilogue-check= -Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK) +Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_check) Init(TPF_TRACE_EPILOGUE_CHECK) Set the trace check address for epilogue tpf hook mtpf-trace-hook-epilogue-target= -Target RejectNegative Report Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET) +Target RejectNegative Joined UInteger Var(s390_tpf_trace_hook_epilogue_target) Init(TPF_TRACE_EPILOGUE_TARGET) Set the trace jump address for epilogue tpf hook mtpf-trace-skip -Target Report Var(s390_tpf_trace_skip) Init(0) +Target Var(s390_tpf_trace_skip) Init(0) Set the prologue and epilogue hook addresses to TPF_TRACE_PROLOGUE_SKIP_TARGET and TPF_TRACE_EPILOGUE_SKIP_TARGET. Equivalent to using -mtpf-trace-hook-prologue-target=TPF_TRACE_PROLOGUE_SKIP_TARGET and -mtpf-trace-hook-epilogue-target=TPF_TRACE_EPILOGUE_SKIP_TARGET mmain -Target Report +Target Specify main object for TPF-OS. diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h index 8ef4f44..cbc8f4d 100644 --- a/gcc/config/s390/vecintrin.h +++ b/gcc/config/s390/vecintrin.h @@ -1,5 +1,5 @@ /* GNU compiler vector extension intrinsics - Copyright (C) 2015-2020 Free Software Foundation, Inc. + Copyright (C) 2015-2021 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 029ee08..0e3c31f 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1,5 +1,5 @@ ;;- Instruction patterns for the System z vector facility -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. @@ -737,16 +737,16 @@ "vperm\t%v0,%v1,%v2,%v3" [(set_attr "op_type" "VRR")]) -(define_insn "*mov_tf_to_fprx2_0" - [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0) +(define_insn "*tf_to_fprx2_0" + [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "+f") 0) (subreg:DF (match_operand:TF 1 "general_operand" "v") 0))] "TARGET_VXE" ; M4 == 1 corresponds to %v0[0] = %v1[0]; %v0[1] = %v0[1]; "vpdi\t%v0,%v1,%v0,1" [(set_attr "op_type" "VRR")]) -(define_insn "*mov_tf_to_fprx2_1" - [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 8) +(define_insn "*tf_to_fprx2_1" + [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "+f") 8) (subreg:DF (match_operand:TF 1 "general_operand" "v") 8))] "TARGET_VXE" ; M4 == 5 corresponds to %V0[0] = %v1[1]; %V0[1] = %V0[1]; diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 2bbed19..816786f 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -1,5 +1,5 @@ ;;- Instruction patterns for the System z vector facility builtins. -;; Copyright (C) 2015-2020 Free Software Foundation, Inc. +;; Copyright (C) 2015-2021 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index b58d08b..8bf3381 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas / SuperH SH. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/divcost-analysis b/gcc/config/sh/divcost-analysis index e6f2c16..ffcaf05 100644 --- a/gcc/config/sh/divcost-analysis +++ b/gcc/config/sh/divcost-analysis @@ -81,7 +81,7 @@ jmp @r0 ; 2 cycles worse than SFUNC_STATIC -Copyright (C) 2006-2020 Free Software Foundation, Inc. +Copyright (C) 2006-2021 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/sh/divtab-sh4-300.c b/gcc/config/sh/divtab-sh4-300.c index ff4581a..d64e768 100644 --- a/gcc/config/sh/divtab-sh4-300.c +++ b/gcc/config/sh/divtab-sh4-300.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/divtab-sh4.c b/gcc/config/sh/divtab-sh4.c index 3b9b51f..9b39f8c 100644 --- a/gcc/config/sh/divtab-sh4.c +++ b/gcc/config/sh/divtab-sh4.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2020 Free Software Foundation, Inc. +/* Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/divtab.c b/gcc/config/sh/divtab.c index d7db7d1..d99ad6a 100644 --- a/gcc/config/sh/divtab.c +++ b/gcc/config/sh/divtab.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2020 Free Software Foundation, Inc. +/* Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h index 450c0b0..a967989 100644 --- a/gcc/config/sh/elf.h +++ b/gcc/config/sh/elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Renesas / SuperH SH using ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Ian Lance Taylor <ian@cygnus.com>. This file is part of GCC. diff --git a/gcc/config/sh/embed-elf.h b/gcc/config/sh/embed-elf.h index 056b0f5..c2e7e49 100644 --- a/gcc/config/sh/embed-elf.h +++ b/gcc/config/sh/embed-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH non-Linux embedded targets. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by J"orn Rennecke <joern.rennecke@superh.com> This file is part of GCC. diff --git a/gcc/config/sh/iterators.md b/gcc/config/sh/iterators.md index 7f21b56..66b7522 100644 --- a/gcc/config/sh/iterators.md +++ b/gcc/config/sh/iterators.md @@ -1,5 +1,5 @@ ;; Iterator definitions for GCC SH machine description files. -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h index c1d0441..7558d2f 100644 --- a/gcc/config/sh/linux.h +++ b/gcc/config/sh/linux.h @@ -1,5 +1,5 @@ /* Definitions for SH running Linux-based GNU systems using ELF - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Kazumoto Kojima <kkojima@rr.iij4u.or.jp> This file is part of GCC. diff --git a/gcc/config/sh/little.h b/gcc/config/sh/little.h index 77c8c52..5c03734 100644 --- a/gcc/config/sh/little.h +++ b/gcc/config/sh/little.h @@ -1,6 +1,6 @@ /* Definition of little endian SH machine for GNU compiler. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/netbsd-elf.h b/gcc/config/sh/netbsd-elf.h index 02bf1be..f0b7541 100644 --- a/gcc/config/sh/netbsd-elf.h +++ b/gcc/config/sh/netbsd-elf.h @@ -1,5 +1,5 @@ /* Definitions for SH running NetBSD using ELF - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/sh/newlib.h b/gcc/config/sh/newlib.h index 3d32033..c837b84 100644 --- a/gcc/config/sh/newlib.h +++ b/gcc/config/sh/newlib.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Super-H using sh-superh-elf. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index 4ba5475..ecb7262 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas / SuperH SH. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/rtems.h b/gcc/config/sh/rtems.h index 7161817..3120445 100644 --- a/gcc/config/sh/rtems.h +++ b/gcc/config/sh/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SH using COFF. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sh/rtemself.h b/gcc/config/sh/rtemself.h index a1aaa46..a747deb 100644 --- a/gcc/config/sh/rtemself.h +++ b/gcc/config/sh/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SH using elf. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c index 218c7c0..d0f3b96 100644 --- a/gcc/config/sh/sh-c.c +++ b/gcc/config/sh/sh-c.c @@ -1,5 +1,5 @@ /* Pragma handling for GCC for Renesas / SuperH SH. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Joern Rennecke <joern.rennecke@st.com>. This file is part of GCC. diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc index f1a7fe8..39aaf74 100644 --- a/gcc/config/sh/sh-mem.cc +++ b/gcc/config/sh/sh-mem.cc @@ -1,5 +1,5 @@ /* Helper routines for memory move and comparison insns. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh-modes.def b/gcc/config/sh/sh-modes.def index 4a07ddf..2fd42d7 100644 --- a/gcc/config/sh/sh-modes.def +++ b/gcc/config/sh/sh-modes.def @@ -1,5 +1,5 @@ /* SH extra machine modes. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index 554bbbb..19ac1c8 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 84c0ea0..1564109 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -1,5 +1,5 @@ /* Output routines for GCC for Renesas / SuperH SH. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 8ab5455..d2280e2 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. - Copyright (C) 1993-2020 Free Software Foundation, Inc. + Copyright (C) 1993-2021 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index fc80278..e3af9ae 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -1,5 +1,5 @@ ;;- Machine description for Renesas / SuperH SH. -;; Copyright (C) 1993-2020 Free Software Foundation, Inc. +;; Copyright (C) 1993-2021 Free Software Foundation, Inc. ;; Contributed by Steve Chamberlain (sac@cygnus.com). ;; Improved by Jim Wilson (wilson@cygnus.com). @@ -6067,8 +6067,7 @@ && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode) || arith_reg_operand (operands[1], SFmode) - || fpul_operand (operands[1], SFmode) - || arith_reg_operand (operands[2], SImode))" + || fpul_operand (operands[1], SFmode))" "@ fmov %1,%0 mov %1,%0 diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 908603b..b4755a8 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -1,6 +1,6 @@ ; Options for the SH port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -175,19 +175,19 @@ Target RejectNegative Condition(SUPPORT_SH4AL) Generate SH4al-dsp code. maccumulate-outgoing-args -Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) +Target Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) Reserve space for outgoing arguments in the function prologue. mb -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target RejectNegative InverseMask(LITTLE_ENDIAN) Generate code in big endian mode. mbigtable -Target Report RejectNegative Mask(BIGTABLE) +Target RejectNegative Mask(BIGTABLE) Generate 32-bit offsets in switch tables. mbitops -Target Report RejectNegative Mask(BITOPS) +Target RejectNegative Mask(BITOPS) Generate bit instructions. mbranch-cost= @@ -195,15 +195,15 @@ Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) Cost to assume for a branch insn. mzdcbranch -Target Report Var(TARGET_ZDCBRANCH) +Target Var(TARGET_ZDCBRANCH) Assume that zero displacement conditional branches are fast. mcbranch-force-delay-slot -Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) +Target RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) Force the usage of delay slots for conditional branches. mdalign -Target Report RejectNegative Mask(ALIGN_DOUBLE) +Target RejectNegative Mask(ALIGN_DOUBLE) Align doubles at 64-bit boundaries. mdiv= @@ -215,7 +215,7 @@ Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") Specify name for 32 bit signed division function. mfdpic -Target Report Var(TARGET_FDPIC) Init(0) +Target Var(TARGET_FDPIC) Init(0) Generate ELF FDPIC code. mfmovd @@ -227,7 +227,7 @@ Target RejectNegative Joined Var(sh_fixed_range_str) Specify range of registers to make fixed. mhitachi -Target Report RejectNegative Mask(HITACHI) +Target RejectNegative Mask(HITACHI) Follow Renesas (formerly Hitachi) / SuperH calling conventions. mieee @@ -235,33 +235,33 @@ Target Var(TARGET_IEEE) Increase the IEEE compliance for floating-point comparisons. minline-ic_invalidate -Target Report Var(TARGET_INLINE_IC_INVALIDATE) +Target Var(TARGET_INLINE_IC_INVALIDATE) Inline code to invalidate instruction cache entries after setting up nested function trampolines. misize -Target Report RejectNegative Mask(DUMPISIZE) +Target RejectNegative Mask(DUMPISIZE) Annotate assembler instructions with estimated addresses. ml -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target RejectNegative Mask(LITTLE_ENDIAN) Generate code in little endian mode. mnomacsave -Target Report RejectNegative Mask(NOMACSAVE) +Target RejectNegative Mask(NOMACSAVE) Mark MAC register as call-clobbered. ;; ??? This option is not useful, but is retained in case there are people ;; who are still relying on it. It may be deleted in the future. mpadstruct -Target Report RejectNegative Mask(PADSTRUCT) +Target RejectNegative Mask(PADSTRUCT) Make structs a multiple of 4 bytes (warning: ABI altered). mprefergot -Target Report RejectNegative Mask(PREFERGOT) +Target RejectNegative Mask(PREFERGOT) Emit function-calls using global offset table when generating PIC. mrelax -Target Report RejectNegative Mask(RELAX) +Target RejectNegative Mask(RELAX) Shorten address references during linking. mrenesas @@ -269,11 +269,11 @@ Target Mask(HITACHI) Follow Renesas (formerly Hitachi) / SuperH calling conventions. matomic-model= -Target Report RejectNegative Joined Var(sh_atomic_model_str) +Target RejectNegative Joined Var(sh_atomic_model_str) Specify the model for atomic operations. mtas -Target Report RejectNegative Var(TARGET_ENABLE_TAS) +Target RejectNegative Var(TARGET_ENABLE_TAS) Use tas.b instruction for __atomic_test_and_set. multcost= @@ -299,5 +299,5 @@ Target Var(TARGET_FSRRA) Enable the use of the fsrra instruction. mlra -Target Report Var(sh_lra_flag) Init(0) Save +Target Var(sh_lra_flag) Init(0) Save Use LRA instead of reload (transitional). diff --git a/gcc/config/sh/sh1.md b/gcc/config/sh/sh1.md index 4d8f9ea..daa86dc 100644 --- a/gcc/config/sh/sh1.md +++ b/gcc/config/sh/sh1.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for Renesas / SuperH SH. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4-300.md b/gcc/config/sh/sh4-300.md index 9ec4a8f..d6c084b 100644 --- a/gcc/config/sh/sh4-300.md +++ b/gcc/config/sh/sh4-300.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for ST40-300. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4.md b/gcc/config/sh/sh4.md index 73150e5..473f7a3 100644 --- a/gcc/config/sh/sh4.md +++ b/gcc/config/sh/sh4.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for SH4. -;; Copyright (C) 2004-2020 Free Software Foundation, Inc. +;; Copyright (C) 2004-2021 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4a.md b/gcc/config/sh/sh4a.md index 85cf6a6..5c3a3dd 100644 --- a/gcc/config/sh/sh4a.md +++ b/gcc/config/sh/sh4a.md @@ -1,5 +1,5 @@ ;; Scheduling description for Renesas SH4a -;; Copyright (C) 2003-2020 Free Software Foundation, Inc. +;; Copyright (C) 2003-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/sh_optimize_sett_clrt.cc b/gcc/config/sh/sh_optimize_sett_clrt.cc index 3db9d28..34b87aa 100644 --- a/gcc/config/sh/sh_optimize_sett_clrt.cc +++ b/gcc/config/sh/sh_optimize_sett_clrt.cc @@ -1,5 +1,5 @@ /* An SH specific RTL pass that tries to optimize clrt and sett insns. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc index ed9dcb0..fb10931 100644 --- a/gcc/config/sh/sh_treg_combine.cc +++ b/gcc/config/sh/sh_treg_combine.cc @@ -1,6 +1,6 @@ /* An SH specific RTL pass that tries to combine comparisons and redundant condition code register stores across multiple basic blocks. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/superh.h b/gcc/config/sh/superh.h index a65f28e..78dc8ad 100644 --- a/gcc/config/sh/superh.h +++ b/gcc/config/sh/superh.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Super-H using sh-superh-elf. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index 25f3b69..2b43f8e 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SH synchronization instructions. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh index a402359..888f8ff 100644 --- a/gcc/config/sh/t-sh +++ b/gcc/config/sh/t-sh @@ -1,4 +1,4 @@ -# Copyright (C) 1993-2020 Free Software Foundation, Inc. +# Copyright (C) 1993-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sh/vxworks.h b/gcc/config/sh/vxworks.h index f3342c7..6af9c84 100644 --- a/gcc/config/sh/vxworks.h +++ b/gcc/config/sh/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for SuperH with targeting the VXWorks run time environment. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2-c.c b/gcc/config/sol2-c.c index 9eaf43c..cd5cce6 100644 --- a/gcc/config/sol2-c.c +++ b/gcc/config/sol2-c.c @@ -1,5 +1,5 @@ /* Solaris support needed only by C/C++ frontends. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2-cxx.c b/gcc/config/sol2-cxx.c index 3074eb5..e942f5e 100644 --- a/gcc/config/sol2-cxx.c +++ b/gcc/config/sol2-cxx.c @@ -1,5 +1,5 @@ /* C++ specific Solaris system support. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2-d.c b/gcc/config/sol2-d.c index 27068f8..529d365 100644 --- a/gcc/config/sol2-d.c +++ b/gcc/config/sol2-d.c @@ -1,5 +1,5 @@ /* Solaris support needed only by D front-end. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/sol2-protos.h b/gcc/config/sol2-protos.h index 399f4a4..77c45e4 100644 --- a/gcc/config/sol2-protos.h +++ b/gcc/config/sol2-protos.h @@ -1,6 +1,6 @@ /* Operating system specific prototypes to be used when targeting GCC for any Solaris 2 system. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2-stubs.c b/gcc/config/sol2-stubs.c index 11d3d90..a73e2a3 100644 --- a/gcc/config/sol2-stubs.c +++ b/gcc/config/sol2-stubs.c @@ -1,5 +1,5 @@ /* Stubs for C++ specific Solaris system support. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2.c b/gcc/config/sol2.c index cf9d9f1..1fbdbf5 100644 --- a/gcc/config/sol2.c +++ b/gcc/config/sol2.c @@ -1,5 +1,5 @@ /* General Solaris system support. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h index 7a21f22..ac2c3cd 100644 --- a/gcc/config/sol2.h +++ b/gcc/config/sol2.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for any Solaris 2 system. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2.opt b/gcc/config/sol2.opt index a432ab5..d6515e2 100644 --- a/gcc/config/sol2.opt +++ b/gcc/config/sol2.opt @@ -1,6 +1,6 @@ ; Options for the Solaris 2 port of the compiler ; -; Copyright (C) 2010-2020 Free Software Foundation, Inc. +; Copyright (C) 2010-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -28,11 +28,11 @@ Ym, Driver Joined mclear-hwcap -Target Report +Target Clear hardware capabilities when linking. mimpure-text -Target Report +Target Pass -z text to linker. pthread diff --git a/gcc/config/sparc/biarch64.h b/gcc/config/sparc/biarch64.h index 3c9f243..e36ac68 100644 --- a/gcc/config/sparc/biarch64.h +++ b/gcc/config/sparc/biarch64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org>. This file is part of GCC. diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md index eb7b2f1..82bbba9 100644 --- a/gcc/config/sparc/constraints.md +++ b/gcc/config/sparc/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for SPARC. -;; Copyright (C) 2008-2020 Free Software Foundation, Inc. +;; Copyright (C) 2008-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/cypress.md b/gcc/config/sparc/cypress.md index 236e7d8..4564ecf 100644 --- a/gcc/config/sparc/cypress.md +++ b/gcc/config/sparc/cypress.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARC Cypress. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/default64.h b/gcc/config/sparc/default64.h index 619e456..9210e38 100644 --- a/gcc/config/sparc/default64.h +++ b/gcc/config/sparc/default64.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GCC, for bi-arch SPARC, defaulting to 64-bit code generation. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index ebb397d..f70c53f 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h index 2e1e9a9..3f9396c 100644 --- a/gcc/config/sparc/freebsd.h +++ b/gcc/config/sparc/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Sun SPARC64 running FreeBSD using the ELF format - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/sparc/hypersparc.md b/gcc/config/sparc/hypersparc.md index ae5c1b1..c2eda4f 100644 --- a/gcc/config/sparc/hypersparc.md +++ b/gcc/config/sparc/hypersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for HyperSPARC. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md index 39dc8ab..5408c78 100644 --- a/gcc/config/sparc/leon.md +++ b/gcc/config/sparc/leon.md @@ -1,5 +1,5 @@ ;; Scheduling description for LEON. -;; Copyright (C) 2010-2020 Free Software Foundation, Inc. +;; Copyright (C) 2010-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index 63853e6..2550d7e 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -1,5 +1,5 @@ /* Definitions for SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Eddie C. Dost (ecd@skynet.be) This file is part of GCC. diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index 19ce84d..95af8af 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by David S. Miller (davem@caip.rutgers.edu) This file is part of GCC. diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt index 8139ae6..66468e5 100644 --- a/gcc/config/sparc/long-double-switch.opt +++ b/gcc/config/sparc/long-double-switch.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,9 +19,9 @@ ; <http://www.gnu.org/licenses/>. mlong-double-128 -Target Report RejectNegative Mask(LONG_DOUBLE_128) +Target RejectNegative Mask(LONG_DOUBLE_128) Use 128-bit long double. mlong-double-64 -Target Report RejectNegative InverseMask(LONG_DOUBLE_128) +Target RejectNegative InverseMask(LONG_DOUBLE_128) Use 64-bit long double. diff --git a/gcc/config/sparc/m8.md b/gcc/config/sparc/m8.md index b7a21f7..e369046 100644 --- a/gcc/config/sparc/m8.md +++ b/gcc/config/sparc/m8.md @@ -1,5 +1,5 @@ ;; Scheduling description for the SPARC M8. -;; Copyright (C) 2017-2020 Free Software Foundation, Inc. +;; Copyright (C) 2017-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h index e37ece5..8a367e3 100644 --- a/gcc/config/sparc/netbsd-elf.h +++ b/gcc/config/sparc/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ELF on NetBSD/sparc and NetBSD/sparc64. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Matthew Green (mrg@eterna.com.au). This file is part of GCC. diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index 7e59213..6e81ed3 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index e69993d..81a758b 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-2 and Niagara-3. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md index 074f3f0..ae2646d 100644 --- a/gcc/config/sparc/niagara4.md +++ b/gcc/config/sparc/niagara4.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-4 -;; Copyright (C) 2012-2020 Free Software Foundation, Inc. +;; Copyright (C) 2012-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara7.md b/gcc/config/sparc/niagara7.md index e1e69db..03139a6 100644 --- a/gcc/config/sparc/niagara7.md +++ b/gcc/config/sparc/niagara7.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-7 -;; Copyright (C) 2016-2020 Free Software Foundation, Inc. +;; Copyright (C) 2016-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/openbsd1-64.h b/gcc/config/sparc/openbsd1-64.h index 0b93bf0..60d7bee 100644 --- a/gcc/config/sparc/openbsd1-64.h +++ b/gcc/config/sparc/openbsd1-64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/openbsd64.h b/gcc/config/sparc/openbsd64.h index f700ecd..e287b20 100644 --- a/gcc/config/sparc/openbsd64.h +++ b/gcc/config/sparc/openbsd64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 42316ad..1851642 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for SPARC. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index 6570590..fa972af 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SPARC using ELF. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. @@ -33,6 +33,8 @@ builtin_assert ("system=rtems"); \ if (sparc_fix_b2bst) \ builtin_define ("__FIX_LEON3FT_B2BST"); \ + if (sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_ut699) \ + builtin_define ("__FIX_LEON3FT_TN0018"); \ } \ while (0) diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 94b668e..1b4aa28 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC running Solaris 2 - Copyright (C) 1992-2020 Free Software Foundation, Inc. + Copyright (C) 1992-2021 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@netcom.com). Additional changes by David V. Henkel-Wallace (gumby@cygnus.com). diff --git a/gcc/config/sparc/sp-elf.h b/gcc/config/sparc/sp-elf.h index 292d050..9bc3d46 100644 --- a/gcc/config/sparc/sp-elf.h +++ b/gcc/config/sparc/sp-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for SPARC running in an embedded environment using the ELF file format. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h index b940aff..d7ac3b2 100644 --- a/gcc/config/sparc/sp64-elf.h +++ b/gcc/config/sparc/sp64-elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC64, ELF. - Copyright (C) 1994-2020 Free Software Foundation, Inc. + Copyright (C) 1994-2021 Free Software Foundation, Inc. Contributed by Doug Evans, dje@cygnus.com. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c index 108e8fa..d9583d9 100644 --- a/gcc/config/sparc/sparc-c.c +++ b/gcc/config/sparc/sparc-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on SPARC. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-d.c b/gcc/config/sparc/sparc-d.c index 53163c6..186e965 100644 --- a/gcc/config/sparc/sparc-d.c +++ b/gcc/config/sparc/sparc-d.c @@ -1,5 +1,5 @@ /* Subroutines for the D front end on the SPARC architecture. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def index 69fe32b..5cc4743 100644 --- a/gcc/config/sparc/sparc-modes.def +++ b/gcc/config/sparc/sparc-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index 5bda749..1af556e 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for SPARC. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-passes.def b/gcc/config/sparc/sparc-passes.def index 31226e3..d24855d 100644 --- a/gcc/config/sparc/sparc-passes.def +++ b/gcc/config/sparc/sparc-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for SPARC. - Copyright (C) 2016-2020 Free Software Foundation, Inc. + Copyright (C) 2016-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 5f9999a..ef94d4f 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for SPARC. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index ec0921b..f355793 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for SPARC. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -12942,6 +12942,12 @@ sparc_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, if (vmode != V8QImode) return false; + rtx nop0 = force_reg (vmode, op0); + if (op0 == op1) + op1 = nop0; + op0 = nop0; + op1 = force_reg (vmode, op1); + unsigned int i, mask; for (i = mask = 0; i < 8; ++i) mask |= (sel[i] & 0xf) << (28 - i*4); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index c5f098e..cec2f5a 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Sun SPARC. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 6e9ccb4..02b7c8d 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1,5 +1,5 @@ ;; Machine description for SPARC. -;; Copyright (C) 1987-2020 Free Software Foundation, Inc. +;; Copyright (C) 1987-2021 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@cygnus.com) ;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, ;; at Cygnus Support. diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index b3d688b..fb79267 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -26,7 +26,7 @@ TargetVariable unsigned int sparc_debug mfpu -Target Report Mask(FPU) +Target Mask(FPU) Use hardware FP. mhard-float @@ -38,95 +38,95 @@ Target RejectNegative InverseMask(FPU) Do not use hardware FP. mflat -Target Report Mask(FLAT) +Target Mask(FLAT) Use flat register window model. munaligned-doubles -Target Report Mask(UNALIGNED_DOUBLES) +Target Mask(UNALIGNED_DOUBLES) Assume possible double misalignment. mapp-regs -Target Report Mask(APP_REGS) +Target Mask(APP_REGS) Use ABI reserved registers. mhard-quad-float -Target Report RejectNegative Mask(HARD_QUAD) +Target RejectNegative Mask(HARD_QUAD) Use hardware quad FP instructions. msoft-quad-float -Target Report RejectNegative InverseMask(HARD_QUAD) +Target RejectNegative InverseMask(HARD_QUAD) Do not use hardware quad fp instructions. mlra -Target Report Mask(LRA) +Target Mask(LRA) Enable Local Register Allocation. mv8plus -Target Report Mask(V8PLUS) +Target Mask(V8PLUS) Compile for V8+ ABI. mvis -Target Report Mask(VIS) +Target Mask(VIS) Use UltraSPARC Visual Instruction Set version 1.0 extensions. mvis2 -Target Report Mask(VIS2) +Target Mask(VIS2) Use UltraSPARC Visual Instruction Set version 2.0 extensions. mvis3 -Target Report Mask(VIS3) +Target Mask(VIS3) Use UltraSPARC Visual Instruction Set version 3.0 extensions. mvis4 -Target Report Mask(VIS4) +Target Mask(VIS4) Use UltraSPARC Visual Instruction Set version 4.0 extensions. mvis4b -Target Report Mask(VIS4B) +Target Mask(VIS4B) Use additional VIS instructions introduced in OSA2017. mcbcond -Target Report Mask(CBCOND) +Target Mask(CBCOND) Use UltraSPARC Compare-and-Branch extensions. mfmaf -Target Report Mask(FMAF) +Target Mask(FMAF) Use UltraSPARC Fused Multiply-Add extensions. mfsmuld -Target Report Mask(FSMULD) +Target Mask(FSMULD) Use Floating-point Multiply Single to Double (FsMULd) instruction. mpopc -Target Report Mask(POPC) +Target Mask(POPC) Use UltraSPARC Population-Count instruction. msubxc -Target Report Mask(SUBXC) +Target Mask(SUBXC) Use UltraSPARC Subtract-Extended-with-Carry instruction. mptr64 -Target Report RejectNegative Mask(PTR64) +Target RejectNegative Mask(PTR64) Pointers are 64-bit. mptr32 -Target Report RejectNegative InverseMask(PTR64) +Target RejectNegative InverseMask(PTR64) Pointers are 32-bit. m64 -Target Report RejectNegative Mask(64BIT) +Target RejectNegative Mask(64BIT) Use 64-bit ABI. m32 -Target Report RejectNegative InverseMask(64BIT) +Target RejectNegative InverseMask(64BIT) Use 32-bit ABI. mstack-bias -Target Report Mask(STACK_BIAS) +Target Mask(STACK_BIAS) Use stack bias. mfaster-structs -Target Report Mask(FASTER_STRUCTS) +Target Mask(FASTER_STRUCTS) Use structs on stronger alignment for double-word copies. mrelax @@ -134,7 +134,7 @@ Target Optimize tail call instructions in assembler and linker. muser-mode -Target Report InverseMask(SV_MODE) +Target InverseMask(SV_MODE) Do not generate code that can only run in supervisor mode (default). mcpu= @@ -247,24 +247,24 @@ Target RejectNegative Joined Undocumented Var(sparc_debug_string) Enable debug output. mstd-struct-return -Target Report Var(sparc_std_struct_return) +Target Var(sparc_std_struct_return) Enable strict 32-bit psABI struct return checking. mfix-at697f -Target Report RejectNegative Var(sparc_fix_at697f) +Target RejectNegative Var(sparc_fix_at697f) Enable workaround for single erratum of AT697F processor (corresponding to erratum #13 of AT697E processor). mfix-ut699 -Target Report RejectNegative Var(sparc_fix_ut699) +Target RejectNegative Var(sparc_fix_ut699) Enable workarounds for the errata of the UT699 processor. mfix-ut700 -Target Report RejectNegative Var(sparc_fix_ut700) +Target RejectNegative Var(sparc_fix_ut700) Enable workarounds for the errata of the UT699E/UT700 processor. mfix-gr712rc -Target Report RejectNegative Var(sparc_fix_gr712rc) +Target RejectNegative Var(sparc_fix_gr712rc) Enable workarounds for the errata of the GR712RC processor. ;; Enable workaround for back-to-back store errata diff --git a/gcc/config/sparc/sparclet.md b/gcc/config/sparc/sparclet.md index 52aa473..7980fc5 100644 --- a/gcc/config/sparc/sparclet.md +++ b/gcc/config/sparc/sparclet.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARClet. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/supersparc.md b/gcc/config/sparc/supersparc.md index 3960061..134858d 100644 --- a/gcc/config/sparc/supersparc.md +++ b/gcc/config/sparc/supersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for SuperSPARC. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index 096372c..c578e95 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SPARC synchronization instructions. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h index 8783198..beb1417 100644 --- a/gcc/config/sparc/sysv4.h +++ b/gcc/config/sparc/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for SPARC running System V.4 - Copyright (C) 1991-2020 Free Software Foundation, Inc. + Copyright (C) 1991-2021 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@monkeys.com). This file is part of GCC. diff --git a/gcc/config/sparc/t-elf b/gcc/config/sparc/t-elf index f037acc..ec69e6d 100644 --- a/gcc/config/sparc/t-elf +++ b/gcc/config/sparc/t-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2020 Free Software Foundation, Inc. +# Copyright (C) 1997-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon b/gcc/config/sparc/t-leon index 410ce0f..1c66053 100644 --- a/gcc/config/sparc/t-leon +++ b/gcc/config/sparc/t-leon @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon3 b/gcc/config/sparc/t-leon3 index 0936126..6a2a5f2 100644 --- a/gcc/config/sparc/t-leon3 +++ b/gcc/config/sparc/t-leon3 @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-linux64 b/gcc/config/sparc/t-linux64 index 887fbef..ff0bd95 100644 --- a/gcc/config/sparc/t-linux64 +++ b/gcc/config/sparc/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2020 Free Software Foundation, Inc. +# Copyright (C) 1998-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index 7d11ab8..c6f90ae 100644 --- a/gcc/config/sparc/t-rtems +++ b/gcc/config/sparc/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-rtems-64 b/gcc/config/sparc/t-rtems-64 index beb29c2..ca85e4b 100644 --- a/gcc/config/sparc/t-rtems-64 +++ b/gcc/config/sparc/t-rtems-64 @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-sparc b/gcc/config/sparc/t-sparc index a09bb26..de99ce7 100644 --- a/gcc/config/sparc/t-sparc +++ b/gcc/config/sparc/t-sparc @@ -1,6 +1,6 @@ # General rules that all sparc/ targets must have. # -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/tso.h b/gcc/config/sparc/tso.h index bf49bd4..ec67abd 100644 --- a/gcc/config/sparc/tso.h +++ b/gcc/config/sparc/tso.h @@ -1,5 +1,5 @@ /* Include fragment for Sparc TSO operating systems. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index b42d740..4d1adf9 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-I/II. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index b735e22..d67c091 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-III. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h index 479ce55..9723cc3 100644 --- a/gcc/config/sparc/visintrin.h +++ b/gcc/config/sparc/visintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2020 Free Software Foundation, Inc. +/* Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/vxworks.h b/gcc/config/sparc/vxworks.h index 23c56b8..49de0c9 100644 --- a/gcc/config/sparc/vxworks.h +++ b/gcc/config/sparc/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for SPARC targeting the VxWorks run time environment. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/constraints.md b/gcc/config/stormy16/constraints.md index 3a3baad..32c2918 100644 --- a/gcc/config/stormy16/constraints.md +++ b/gcc/config/stormy16/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for XSTORMY16. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md index cc9a967..eff5273 100644 --- a/gcc/config/stormy16/predicates.md +++ b/gcc/config/stormy16/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for XSTORMY16. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/stormy16/stormy-abi b/gcc/config/stormy16/stormy-abi index cf066db..e9fc9a7 100644 --- a/gcc/config/stormy16/stormy-abi +++ b/gcc/config/stormy16/stormy-abi @@ -167,7 +167,7 @@ means that overflow is reported for either signed or unsigned overflow. -Copyright (C) 2001-2020 Free Software Foundation, Inc. +Copyright (C) 2001-2021 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/stormy16/stormy16-protos.h b/gcc/config/stormy16/stormy16-protos.h index 8c4d2bb..c81ea8c 100644 --- a/gcc/config/stormy16/stormy16-protos.h +++ b/gcc/config/stormy16/stormy16-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in xstormy16.c - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c index 2141531..fb7670f 100644 --- a/gcc/config/stormy16/stormy16.c +++ b/gcc/config/stormy16/stormy16.c @@ -1,5 +1,5 @@ /* Xstormy16 target functions. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index bd74de6..d275516 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -1,5 +1,5 @@ /* Xstormy16 cpu description. - Copyright (C) 1997-2020 Free Software Foundation, Inc. + Copyright (C) 1997-2021 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.md b/gcc/config/stormy16/stormy16.md index 8a86940..c634db5 100644 --- a/gcc/config/stormy16/stormy16.md +++ b/gcc/config/stormy16/stormy16.md @@ -1,5 +1,5 @@ ;; XSTORMY16 Machine description template -;; Copyright (C) 1997-2020 Free Software Foundation, Inc. +;; Copyright (C) 1997-2021 Free Software Foundation, Inc. ;; Contributed by Red Hat, Inc. ;; This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.opt b/gcc/config/stormy16/stormy16.opt index 7fab405..6456766 100644 --- a/gcc/config/stormy16/stormy16.opt +++ b/gcc/config/stormy16/stormy16.opt @@ -1,6 +1,6 @@ ; Options for the XSTORMY16 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/t-darwin b/gcc/config/t-darwin index 355389c..d9d4c73 100644 --- a/gcc/config/t-darwin +++ b/gcc/config/t-darwin @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-dragonfly b/gcc/config/t-dragonfly index 764ced9..bc7ddb4 100644 --- a/gcc/config/t-dragonfly +++ b/gcc/config/t-dragonfly @@ -1,4 +1,4 @@ -# Copyright (C) 2020 Free Software Foundation, Inc. +# Copyright (C) 2020-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-freebsd b/gcc/config/t-freebsd index ca0cb2e..1a5c80a 100644 --- a/gcc/config/t-freebsd +++ b/gcc/config/t-freebsd @@ -1,4 +1,4 @@ -# Copyright (C) 2020 Free Software Foundation, Inc. +# Copyright (C) 2020-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-glibc b/gcc/config/t-glibc index 0c27973..cb6d097 100644 --- a/gcc/config/t-glibc +++ b/gcc/config/t-glibc @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-libunwind b/gcc/config/t-libunwind index c66b77f..28020a7 100644 --- a/gcc/config/t-libunwind +++ b/gcc/config/t-libunwind @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-linux b/gcc/config/t-linux index ce05b37..f74f7d0 100644 --- a/gcc/config/t-linux +++ b/gcc/config/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-lynx b/gcc/config/t-lynx index ab8428d..7798d4d 100644 --- a/gcc/config/t-lynx +++ b/gcc/config/t-lynx @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-netbsd b/gcc/config/t-netbsd index ab1581d..bd98b89 100644 --- a/gcc/config/t-netbsd +++ b/gcc/config/t-netbsd @@ -1,4 +1,4 @@ -# Copyright (C) 2017-2020 Free Software Foundation, Inc. +# Copyright (C) 2017-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-pnt16-warn b/gcc/config/t-pnt16-warn index d11489e..8e80390 100644 --- a/gcc/config/t-pnt16-warn +++ b/gcc/config/t-pnt16-warn @@ -1,5 +1,5 @@ # -Werror overrides for targets with 16 bit pointers -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-sol2 b/gcc/config/t-sol2 index 8b953d9..794cc9e 100644 --- a/gcc/config/t-sol2 +++ b/gcc/config/t-sol2 @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2020 Free Software Foundation, Inc. +# Copyright (C) 2004-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-vxworks b/gcc/config/t-vxworks index 221f53c..5a06ebe 100644 --- a/gcc/config/t-vxworks +++ b/gcc/config/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -43,29 +43,16 @@ $(INSTALL_HEADERS_DIR): install-stdint.h LIMITS_H_TEST = true STMP_FIXINC = stmp-fixinc -# VxWorks system environments have been GCC based for a long time and we need -# to make sure that our files and the system ones use distinct macro names to -# protect against recursive inclusions. We achieve this by temporarily -# substituting the headers used by stmp-int-headers with alternative versions -# where we add some version indication in the inclusion-protection macro +# VxWorks system environments have been GCC based for a long time and +# we need to make sure that our files and the system ones use distinct +# macro names to protect against recursive inclusions. We achieve +# this by modifying the GLIMITS_H fragment that goes into limits.h +# with some version indication in the inclusion-protection macro # names. -# Before the standard stmp-int-headers operations take place, arrange to -# copy the current version of the relevant header files locally, generate -# the alternate version and replace the original version with ours: +T_GLIMITS_H = vxw-glimits.h -stmp-int-hdrs: subst-glimits.h - -subst-%.h: - cp -p $(srcdir)/$*.h orig-$*.h - ID=$$(echo $(BASEVER_c) | sed -e 's/\./_/g'); \ - sed -e "s/_LIMITS_H__/_LIMITS_H__$${ID}_/" < $(srcdir)/$*.h > $@ - cp $@ $(srcdir)/$*.h - -# Then arrange to restore the original versions after the standard -# operations have taken place: - -INSTALL_HEADERS += restore-glimits.h - -restore-glimits.h: stmp-int-hdrs - cp -p orig-glimits.h $(srcdir)/glimits.h +vxw-glimits.h: $(srcdir)/glimits.h + ID=`echo $(BASEVER_c) | sed -e 's/\./_/g'` && \ + sed -e "s/_LIMITS_H__/_LIMITS_H__$${ID}_/" < $(srcdir)/glimits.h > $@T + mv $@T $@ diff --git a/gcc/config/t-winnt b/gcc/config/t-winnt index b9bf20f..9587f66 100644 --- a/gcc/config/t-winnt +++ b/gcc/config/t-winnt @@ -1,4 +1,4 @@ -# Copyright (C) 2013-2020 Free Software Foundation, Inc. +# Copyright (C) 2013-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/tilegx/constraints.md b/gcc/config/tilegx/constraints.md index eb370aa..c504366 100644 --- a/gcc/config/tilegx/constraints.md +++ b/gcc/config/tilegx/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Tilera TILE-Gx. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/linux.h b/gcc/config/tilegx/linux.h index f9d129a..6886d45 100644 --- a/gcc/config/tilegx/linux.h +++ b/gcc/config/tilegx/linux.h @@ -1,5 +1,5 @@ /* Definitions for TILE-Gx running Linux-based GNU systems with ELF. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/mul-tables.c b/gcc/config/tilegx/mul-tables.c index df88fbe..ec49228 100644 --- a/gcc/config/tilegx/mul-tables.c +++ b/gcc/config/tilegx/mul-tables.c @@ -1,5 +1,5 @@ /* Constant multiply table for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/predicates.md b/gcc/config/tilegx/predicates.md index 9c468ea..a62e7f1 100644 --- a/gcc/config/tilegx/predicates.md +++ b/gcc/config/tilegx/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Tilera TILE-Gx. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/sync.md b/gcc/config/tilegx/sync.md index cf96b8d..02cf008 100644 --- a/gcc/config/tilegx/sync.md +++ b/gcc/config/tilegx/sync.md @@ -1,6 +1,6 @@ ;; GCC machine description for Tilera TILE-Gx synchronization ;; instructions. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-builtins.h b/gcc/config/tilegx/tilegx-builtins.h index 3e99d32..5193ab1 100644 --- a/gcc/config/tilegx/tilegx-builtins.h +++ b/gcc/config/tilegx/tilegx-builtins.h @@ -1,5 +1,5 @@ /* Enum for builtin intrinsics for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-c.c b/gcc/config/tilegx/tilegx-c.c index 2c6e03a..2181cd3 100644 --- a/gcc/config/tilegx/tilegx-c.c +++ b/gcc/config/tilegx/tilegx-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-generic.md b/gcc/config/tilegx/tilegx-generic.md index 4e6df9e..ef714b2 100644 --- a/gcc/config/tilegx/tilegx-generic.md +++ b/gcc/config/tilegx/tilegx-generic.md @@ -1,5 +1,5 @@ ;; Scheduling description for Tilera TILE-Gx chip. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-modes.def b/gcc/config/tilegx/tilegx-modes.def index 18842f2..c8dcf9c 100644 --- a/gcc/config/tilegx/tilegx-modes.def +++ b/gcc/config/tilegx/tilegx-modes.def @@ -1,5 +1,5 @@ /* TILE-Gx extra machine modes. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-multiply.h b/gcc/config/tilegx/tilegx-multiply.h index 87b160e..a06e4b8 100644 --- a/gcc/config/tilegx/tilegx-multiply.h +++ b/gcc/config/tilegx/tilegx-multiply.h @@ -1,5 +1,5 @@ /* Header for constant multiple table for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-opts.h b/gcc/config/tilegx/tilegx-opts.h index 59fdd83..4b51261 100644 --- a/gcc/config/tilegx/tilegx-opts.h +++ b/gcc/config/tilegx/tilegx-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for TILE-Gx. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-protos.h b/gcc/config/tilegx/tilegx-protos.h index a4f313c..dba4683 100644 --- a/gcc/config/tilegx/tilegx-protos.h +++ b/gcc/config/tilegx/tilegx-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index 142e342..64e28f6 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Tilera TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h index 15ab6f4..b0dcccf 100644 --- a/gcc/config/tilegx/tilegx.h +++ b/gcc/config/tilegx/tilegx.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for TILE-Gx. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 94be6b5..eae5555 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1,5 +1,5 @@ ;; Machine description for Tilera TILE-Gx chip for GCC. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.opt b/gcc/config/tilegx/tilegx.opt index bcbadb9..943449a 100644 --- a/gcc/config/tilegx/tilegx.opt +++ b/gcc/config/tilegx/tilegx.opt @@ -1,5 +1,5 @@ ; Options for the TILE-Gx port of the compiler. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; Contributed by Walter Lee (walt@tilera.com) ; ; This file is part of GCC. @@ -33,19 +33,19 @@ EnumValue Enum(tilegx_cpu) String(tilegx) Value(0) m32 -Target Report RejectNegative Negative(m64) Mask(32BIT) +Target RejectNegative Negative(m64) Mask(32BIT) Compile with 32 bit longs and pointers. m64 -Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT) +Target RejectNegative Negative(m32) InverseMask(32BIT, 64BIT) Compile with 64 bit longs and pointers. mbig-endian -Target Report RejectNegative Mask(BIG_ENDIAN) +Target RejectNegative Mask(BIG_ENDIAN) Use big-endian byte order. mlittle-endian -Target Report RejectNegative InverseMask(BIG_ENDIAN) +Target RejectNegative InverseMask(BIG_ENDIAN) Use little-endian byte order. mcmodel= diff --git a/gcc/config/tilepro/constraints.md b/gcc/config/tilepro/constraints.md index 4861941..8f677e3 100644 --- a/gcc/config/tilepro/constraints.md +++ b/gcc/config/tilepro/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Tilera TILEPro chip. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/gen-mul-tables.cc b/gcc/config/tilepro/gen-mul-tables.cc index 7f9fb65..03c0cfd 100644 --- a/gcc/config/tilepro/gen-mul-tables.cc +++ b/gcc/config/tilepro/gen-mul-tables.cc @@ -1,5 +1,5 @@ /* Multiply table generator for tile. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. @@ -1230,7 +1230,7 @@ main () #else printf ("/* Constant multiply table for TILE-Gx.\n"); #endif - printf (" Copyright (C) 2011-2020 Free Software Foundation, Inc.\n"); + printf (" Copyright (C) 2011-2021 Free Software Foundation, Inc.\n"); printf (" Contributed by Walter Lee (walt@tilera.com)\n"); printf ("\n"); printf (" This file is part of GCC.\n"); diff --git a/gcc/config/tilepro/linux.h b/gcc/config/tilepro/linux.h index 25292b0..f0b0687 100644 --- a/gcc/config/tilepro/linux.h +++ b/gcc/config/tilepro/linux.h @@ -1,5 +1,5 @@ /* Definitions for TILEPro running Linux-based GNU systems with ELF. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/mul-tables.c b/gcc/config/tilepro/mul-tables.c index ab4a533..3fff354 100644 --- a/gcc/config/tilepro/mul-tables.c +++ b/gcc/config/tilepro/mul-tables.c @@ -1,5 +1,5 @@ /* Constant multiply table for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/predicates.md b/gcc/config/tilepro/predicates.md index c782034..56e7a42 100644 --- a/gcc/config/tilepro/predicates.md +++ b/gcc/config/tilepro/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Tilera TILEPro chip. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-builtins.h b/gcc/config/tilepro/tilepro-builtins.h index a3fb44e..90f97db0 100644 --- a/gcc/config/tilepro/tilepro-builtins.h +++ b/gcc/config/tilepro/tilepro-builtins.h @@ -1,5 +1,5 @@ /* Enum for builtin intrinsics for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-c.c b/gcc/config/tilepro/tilepro-c.c index 6f938f0..453f7ff 100644 --- a/gcc/config/tilepro/tilepro-c.c +++ b/gcc/config/tilepro/tilepro-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-generic.md b/gcc/config/tilepro/tilepro-generic.md index e4fa6db..f5842bf 100644 --- a/gcc/config/tilepro/tilepro-generic.md +++ b/gcc/config/tilepro/tilepro-generic.md @@ -1,5 +1,5 @@ ;; Scheduling description for Tilera TILEPro chip. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-modes.def b/gcc/config/tilepro/tilepro-modes.def index 6335adb..e6ea647 100644 --- a/gcc/config/tilepro/tilepro-modes.def +++ b/gcc/config/tilepro/tilepro-modes.def @@ -1,5 +1,5 @@ /* TILEPro extra machine modes. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-multiply.h b/gcc/config/tilepro/tilepro-multiply.h index 2b0eb07..1e459e6f 100644 --- a/gcc/config/tilepro/tilepro-multiply.h +++ b/gcc/config/tilepro/tilepro-multiply.h @@ -1,5 +1,5 @@ /* Header for constant multiple table for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-protos.h b/gcc/config/tilepro/tilepro-protos.h index 6467200..6849421 100644 --- a/gcc/config/tilepro/tilepro-protos.h +++ b/gcc/config/tilepro/tilepro-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index 3990194..f2525d5 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Tilera TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h index a23c77f..1986f80 100644 --- a/gcc/config/tilepro/tilepro.h +++ b/gcc/config/tilepro/tilepro.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for TILEPro. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md index 7aa6d4d..c6ab941 100644 --- a/gcc/config/tilepro/tilepro.md +++ b/gcc/config/tilepro/tilepro.md @@ -1,5 +1,5 @@ ;; Machine description for Tilera TILEPro chip for GCC. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.opt b/gcc/config/tilepro/tilepro.opt index d97eb04..c34f9c0 100644 --- a/gcc/config/tilepro/tilepro.opt +++ b/gcc/config/tilepro/tilepro.opt @@ -1,5 +1,5 @@ ; Options for the TILEPro port of the compiler. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; Contributed by Walter Lee (walt@tilera.com) ; ; This file is part of GCC. @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. m32 -Target Report RejectNegative +Target RejectNegative Compile with 32 bit longs and pointers, which is the only supported behavior and thus the flag is ignored. diff --git a/gcc/config/usegas.h b/gcc/config/usegas.h index feb6023..2eca83c 100644 --- a/gcc/config/usegas.h +++ b/gcc/config/usegas.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2001-2020 Free Software Foundation, Inc. +/* Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/constraints.md b/gcc/config/v850/constraints.md index c26d546..a3cfbef 100644 --- a/gcc/config/v850/constraints.md +++ b/gcc/config/v850/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for V850. -;; Copyright (C) 2011-2020 Free Software Foundation, Inc. +;; Copyright (C) 2011-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md index a8b264e..91f4332 100644 --- a/gcc/config/v850/predicates.md +++ b/gcc/config/v850/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for NEC V850. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/v850/rtems.h b/gcc/config/v850/rtems.h index e261ea3..17da919 100644 --- a/gcc/config/v850/rtems.h +++ b/gcc/config/v850/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a v850 using ELF. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/t-v850 b/gcc/config/v850/t-v850 index 36fdc1d..373455f 100644 --- a/gcc/config/v850/t-v850 +++ b/gcc/config/v850/t-v850 @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2020 Free Software Foundation, Inc. +# Copyright (C) 1997-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/v850/v850-c.c b/gcc/config/v850/v850-c.c index fca9b61..b08e57a 100644 --- a/gcc/config/v850/v850-c.c +++ b/gcc/config/v850/v850-c.c @@ -1,5 +1,5 @@ /* v850 specific, C compiler specific functions. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850-modes.def b/gcc/config/v850/v850-modes.def index c3c8f80..9d74322 100644 --- a/gcc/config/v850/v850-modes.def +++ b/gcc/config/v850/v850-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. NEC V850 series - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by NEC EL This file is part of GCC. diff --git a/gcc/config/v850/v850-opts.h b/gcc/config/v850/v850-opts.h index d1324d9..8222283 100644 --- a/gcc/config/v850/v850-opts.h +++ b/gcc/config/v850/v850-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for NEC V850 series. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/v850-protos.h b/gcc/config/v850/v850-protos.h index 2efe513..42fece6 100644 --- a/gcc/config/v850/v850-protos.h +++ b/gcc/config/v850/v850-protos.h @@ -1,5 +1,5 @@ /* Prototypes for v850.c functions used in the md file & elsewhere. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index 4b0e28c..249cb40 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for NEC V850 series - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index 7ae583c..23dfdf6 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. NEC V850 series - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index a580b00..872f179 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -1,5 +1,5 @@ ;; GCC machine description for NEC V850 -;; Copyright (C) 1996-2020 Free Software Foundation, Inc. +;; Copyright (C) 1996-2021 Free Software Foundation, Inc. ;; Contributed by Jeff Law (law@cygnus.com). ;; This file is part of GCC. diff --git a/gcc/config/v850/v850.opt b/gcc/config/v850/v850.opt index 723b5a3..d3792bf0 100644 --- a/gcc/config/v850/v850.opt +++ b/gcc/config/v850/v850.opt @@ -1,6 +1,6 @@ ; Options for the NEC V850 port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -25,34 +25,34 @@ Variable int small_memory_max[(int)SMALL_MEMORY_max] = { 0, 0, 0 } mapp-regs -Target Report Mask(APP_REGS) +Target Mask(APP_REGS) Use registers r2 and r5. mbig-switch -Target Report Mask(BIG_SWITCH) +Target Mask(BIG_SWITCH) Use 4 byte entries in switch tables. mdebug -Target Report Mask(DEBUG) +Target Mask(DEBUG) Enable backend debugging. mdisable-callt -Target Report Mask(DISABLE_CALLT) +Target Mask(DISABLE_CALLT) Do not use the callt instruction (default). mep -Target Report Mask(EP) +Target Mask(EP) Reuse r30 on a per function basis. mghs Target RejectNegative InverseMask(GCC_ABI) MaskExists mlong-calls -Target Report Mask(LONG_CALLS) +Target Mask(LONG_CALLS) Prohibit PC relative function calls. mprolog-function -Target Report Mask(PROLOG_FUNCTION) +Target Mask(PROLOG_FUNCTION) Use stubs for function prologues. msda= @@ -63,7 +63,7 @@ msda- Target RejectNegative Joined Undocumented Alias(msda=) msmall-sld -Target Report Mask(SMALL_SLD) +Target Mask(SMALL_SLD) Enable the use of the short load instructions. mspace @@ -78,22 +78,22 @@ mtda- Target RejectNegative Joined Undocumented Alias(mtda=) mno-strict-align -Target Report Mask(NO_STRICT_ALIGN) +Target Mask(NO_STRICT_ALIGN) Do not enforce strict alignment. mjump-tables-in-data-section -Target Report Mask(JUMP_TABLES_IN_DATA_SECTION) +Target Mask(JUMP_TABLES_IN_DATA_SECTION) Put jump tables for switch statements into the .data section rather than the .code section. mUS-bit-set -Target Report Mask(US_BIT_SET) +Target Mask(US_BIT_SET) mv850 -Target Report RejectNegative Mask(V850) +Target RejectNegative Mask(V850) Compile for the v850 processor. mv850e -Target Report RejectNegative Mask(V850E) +Target RejectNegative Mask(V850E) Compile for the v850e processor. mv850e1 @@ -105,22 +105,22 @@ Target RejectNegative Mask(V850E1) Compile for the v850es variant of the v850e1. mv850e2 -Target Report RejectNegative Mask(V850E2) +Target RejectNegative Mask(V850E2) Compile for the v850e2 processor. mv850e2v3 -Target Report RejectNegative Mask(V850E2V3) +Target RejectNegative Mask(V850E2V3) Compile for the v850e2v3 processor. mv850e3v5 -Target Report RejectNegative Mask(V850E3V5) +Target RejectNegative Mask(V850E3V5) Compile for the v850e3v5 processor. mv850e2v4 Target RejectNegative Mask(V850E3V5) MaskExists mloop -Target Report Mask(LOOP) +Target Mask(LOOP) Enable v850e3v5 loop instructions. mzda= @@ -131,29 +131,29 @@ mzda- Target RejectNegative Joined Undocumented Alias(mzda=) mrelax -Target Report Mask(RELAX) +Target Mask(RELAX) Enable relaxing in the assembler. mlong-jumps -Target Report Mask(BIG_SWITCH) MaskExists +Target Mask(BIG_SWITCH) MaskExists Prohibit PC relative jumps. msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target RejectNegative Mask(SOFT_FLOAT) Inhibit the use of hardware floating point instructions. mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT) MaskExists +Target RejectNegative InverseMask(SOFT_FLOAT) MaskExists Allow the use of hardware floating point instructions for V850E2V3 and up. mrh850-abi -Target RejectNegative Report InverseMask(GCC_ABI) MaskExists +Target RejectNegative InverseMask(GCC_ABI) MaskExists Enable support for the RH850 ABI. This is the default. mgcc-abi -Target RejectNegative Report Mask(GCC_ABI) +Target RejectNegative Mask(GCC_ABI) Enable support for the old GCC ABI. m8byte-align -Target Report Mask(8BYTE_ALIGN) +Target Mask(8BYTE_ALIGN) Support alignments of up to 64-bits. diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index 846d1f3..3d1cbcd 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -1,5 +1,5 @@ ;; builtin definitions for DEC VAX. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/constraints.md b/gcc/config/vax/constraints.md index d4eddb8..843fca5 100644 --- a/gcc/config/vax/constraints.md +++ b/gcc/config/vax/constraints.md @@ -1,5 +1,5 @@ ;; Constraints for the DEC VAX port. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/elf.h b/gcc/config/vax/elf.h index f6485eca..823701d 100644 --- a/gcc/config/vax/elf.h +++ b/gcc/config/vax/elf.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for VAX using ELF - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by Matt Thomas <matt@3am-software.com> This file is part of GCC. diff --git a/gcc/config/vax/elf.opt b/gcc/config/vax/elf.opt index 10589d7..fd2c509 100644 --- a/gcc/config/vax/elf.opt +++ b/gcc/config/vax/elf.opt @@ -1,6 +1,6 @@ ; VAX ELF options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/vax/linux.h b/gcc/config/vax/linux.h index 2addf7d..5dbb40a 100644 --- a/gcc/config/vax/linux.h +++ b/gcc/config/vax/linux.h @@ -1,5 +1,5 @@ /* Definitions for VAX running Linux-based GNU systems with ELF format. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/netbsd-elf.h b/gcc/config/vax/netbsd-elf.h index 9a01fdd..21f5bc6 100644 --- a/gcc/config/vax/netbsd-elf.h +++ b/gcc/config/vax/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for NetBSD/vax ELF systems. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/openbsd.h b/gcc/config/vax/openbsd.h index b733e8c..95bea8d 100644 --- a/gcc/config/vax/openbsd.h +++ b/gcc/config/vax/openbsd.h @@ -1,5 +1,5 @@ /* Configuration fragment for a VAX OpenBSD target. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/openbsd1.h b/gcc/config/vax/openbsd1.h index bde77e7..28d7b25 100644 --- a/gcc/config/vax/openbsd1.h +++ b/gcc/config/vax/openbsd1.h @@ -1,5 +1,5 @@ /* Configuration fragment for a VAX OpenBSD target. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/predicates.md b/gcc/config/vax/predicates.md index 92caf83..edec4f7 100644 --- a/gcc/config/vax/predicates.md +++ b/gcc/config/vax/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for DEC VAX. -;; Copyright (C) 2007-2020 Free Software Foundation, Inc. +;; Copyright (C) 2007-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/vax-modes.def b/gcc/config/vax/vax-modes.def index 2a7438e..29af798 100644 --- a/gcc/config/vax/vax-modes.def +++ b/gcc/config/vax/vax-modes.def @@ -1,5 +1,5 @@ /* VAX extra machine modes. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax-protos.h b/gcc/config/vax/vax-protos.h index aa949c5..89fddec 100644 --- a/gcc/config/vax/vax-protos.h +++ b/gcc/config/vax/vax-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. VAX version. - Copyright (C) 2000-2020 Free Software Foundation, Inc. + Copyright (C) 2000-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index 54d83dc..fe4c14e 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for VAX. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. @@ -1235,6 +1235,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands, { rtx hi[3], lo[3]; const char *pattern_hi, *pattern_lo; + bool push_p; switch (mode) { @@ -1345,19 +1346,13 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands, return "movq %1,%0"; case E_SImode: + push_p = push_operand (operands[0], SImode); + if (symbolic_operand (operands[1], SImode)) - { - if (push_operand (operands[0], SImode)) - return "pushab %a1"; - return "movab %a1,%0"; - } + return push_p ? "pushab %a1" : "movab %a1,%0"; if (operands[1] == const0_rtx) - { - if (push_operand (operands[1], SImode)) - return "pushl %1"; - return "clrl %0"; - } + return push_p ? "pushl %1" : "clrl %0"; if (CONST_INT_P (operands[1]) && (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64) @@ -1383,9 +1378,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands, if (i >= -0x8000 && i < 0) return "cvtwl %1,%0"; } - if (push_operand (operands[0], SImode)) - return "pushl %1"; - return "movl %1,%0"; + return push_p ? "pushl %1" : "movl %1,%0"; case E_HImode: if (CONST_INT_P (operands[1])) @@ -2042,12 +2035,14 @@ vax_expand_addsub_di_operands (rtx * operands, enum rtx_code code) } else { - /* If are adding the same value together, that's really a multiply by 2, - and that's just a left shift of 1. */ + /* If we are adding a value to itself, that's really a multiply by 2, + and that's just a left shift by 1. If subtracting, it's just 0. */ if (rtx_equal_p (operands[1], operands[2])) { - gcc_assert (code != MINUS); - emit_insn (gen_ashldi3 (operands[0], operands[1], const1_rtx)); + if (code == PLUS) + emit_insn (gen_ashldi3 (operands[0], operands[1], const1_rtx)); + else + emit_move_insn (operands[0], const0_rtx); return; } @@ -2066,6 +2061,19 @@ vax_expand_addsub_di_operands (rtx * operands, enum rtx_code code) else operands[2] = fixup_mathdi_operand (operands[2], DImode); + /* If we are adding or subtracting 0, then this is a move. */ + if (code == PLUS && operands[1] == const0_rtx) + { + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; + } + if (operands[2] == const0_rtx) + { + emit_move_insn (operands[0], operands[1]); + return; + } + /* If we are subtracting not from ourselves [d = a - b], and because the carry ops are two operand only, we would need to do a move prior to the subtract. And if d == b, we would need a temp otherwise @@ -2082,7 +2090,6 @@ vax_expand_addsub_di_operands (rtx * operands, enum rtx_code code) { if (code == MINUS && CONSTANT_P (operands[1])) { - temp = gen_reg_rtx (DImode); emit_insn (gen_sbcdi3 (operands[0], const0_rtx, operands[2])); code = PLUS; gen_insn = gen_adcdi3; diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 8b2b2d1..b67d668 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. VAX version. - Copyright (C) 1987-2020 Free Software Foundation, Inc. + Copyright (C) 1987-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index b8cf4ee..0a2c86c 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -1,5 +1,5 @@ ;; Machine description for GNU compiler, VAX Version -;; Copyright (C) 1987-2020 Free Software Foundation, Inc. +;; Copyright (C) 1987-2021 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -58,7 +58,6 @@ (define_mode_iterator VAXcc [CC CCN CCNZ CCZ]) (define_mode_iterator VAXccnz [CCN CCNZ CCZ]) -(define_mode_attr cc [(CC "cc") (CCN "ccn") (CCNZ "ccnz") (CCZ "ccz")]) (define_code_iterator any_extract [sign_extract zero_extract]) @@ -67,7 +66,7 @@ (include "predicates.md") ;; Make instructions that set the N, N+Z, and Z condition codes respectively. -(define_subst "subst_<cc>" +(define_subst "subst_<mode>" [(set (match_operand 0 "") (match_operand 1 "")) (clobber (reg:CC VAX_PSL_REGNUM))] @@ -78,14 +77,14 @@ (set (match_dup 0) (match_dup 1))]) -(define_subst "subst_f<cc>" - [(set (match_operand 0 "") - (match_operand 1 "")) +(define_subst "subst_f<VAXccnz:mode>" + [(set (match_operand:VAXfp 0 "") + (match_operand:VAXfp 1 "")) (clobber (reg:CC VAX_PSL_REGNUM))] "" [(set (reg:VAXccnz VAX_PSL_REGNUM) (compare:VAXccnz (match_dup 1) - (const_double_zero))) + (const_double_zero:VAXfp))) (set (match_dup 0) (match_dup 1))]) @@ -2174,7 +2173,7 @@ (define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>" [(set (pc) (if_then_else - (match_operator 0 "vax_<cc>_comparison_operator" + (match_operator 0 "vax_<VAXcc:mode>_comparison_operator" [(match_operand:VAXint 1 "general_operand" "nrmT") (match_operand:VAXint 2 "general_operand" "nrmT")]) (label_ref (match_operand 3 "" "")) @@ -2206,7 +2205,7 @@ (define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>" [(set (pc) (if_then_else - (match_operator 0 "vax_<cc>_comparison_operator" + (match_operator 0 "vax_<VAXccnz:mode>_comparison_operator" [(match_operand:VAXfp 1 "general_operand" "gF") (match_operand:VAXfp 2 "general_operand" "gF")]) (label_ref (match_operand 3 "" "")) @@ -2226,7 +2225,7 @@ (define_insn "*branch_<mode>" [(set (pc) - (if_then_else (match_operator 0 "vax_<cc>_comparison_operator" + (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" [(reg:VAXcc VAX_PSL_REGNUM) (const_int 0)]) (label_ref (match_operand 1 "" "")) @@ -2237,7 +2236,7 @@ ;; Recognize reversed jumps. (define_insn "*branch_<mode>_reversed" [(set (pc) - (if_then_else (match_operator 0 "vax_<cc>_comparison_operator" + (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" [(reg:VAXcc VAX_PSL_REGNUM) (const_int 0)]) (pc) @@ -2816,7 +2815,7 @@ rtx index = gen_reg_rtx (SImode); emit_insn (gen_addsi3 (index, operands[0], - GEN_INT (-INTVAL (operands[1])))); + gen_int_mode (-INTVAL (operands[1]), SImode))); operands[0] = index; } diff --git a/gcc/config/vax/vax.opt b/gcc/config/vax/vax.opt index 86f3065..470e8b1 100644 --- a/gcc/config/vax/vax.opt +++ b/gcc/config/vax/vax.opt @@ -1,6 +1,6 @@ ; Options for the VAX port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/visium/constraints.md b/gcc/config/visium/constraints.md index f2f98a7..bcb9a4a 100644 --- a/gcc/config/visium/constraints.md +++ b/gcc/config/visium/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Visium. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/elf.h b/gcc/config/visium/elf.h index e3b0878..3720150 100644 --- a/gcc/config/visium/elf.h +++ b/gcc/config/visium/elf.h @@ -1,5 +1,5 @@ /* ELF-specific defines for Visium. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/gr5.md b/gcc/config/visium/gr5.md index 219ad06..81c0322 100644 --- a/gcc/config/visium/gr5.md +++ b/gcc/config/visium/gr5.md @@ -1,5 +1,5 @@ ;; Scheduling description for GR5. -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/gr6.md b/gcc/config/visium/gr6.md index 88c3431..4d7b25c 100644 --- a/gcc/config/visium/gr6.md +++ b/gcc/config/visium/gr6.md @@ -1,5 +1,5 @@ ;; Scheduling description for GR6. -;; Copyright (C) 2013-2020 Free Software Foundation, Inc. +;; Copyright (C) 2013-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md index d79e0c5..f8e97bc 100644 --- a/gcc/config/visium/predicates.md +++ b/gcc/config/visium/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Visium. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/t-visium b/gcc/config/visium/t-visium index 6edc985..17e4c60 100644 --- a/gcc/config/visium/t-visium +++ b/gcc/config/visium/t-visium @@ -1,6 +1,6 @@ # General rules that all visium/ targets must have. -# Copyright (C) 2012-2020 Free Software Foundation, Inc. +# Copyright (C) 2012-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/visium/visium-modes.def b/gcc/config/visium/visium-modes.def index 6d5989b..b837653 100644 --- a/gcc/config/visium/visium-modes.def +++ b/gcc/config/visium/visium-modes.def @@ -1,5 +1,5 @@ /* Machine description for Visium. - Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2014-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/visium-opts.h b/gcc/config/visium/visium-opts.h index 4bcaad8..52dc7cf 100644 --- a/gcc/config/visium/visium-opts.h +++ b/gcc/config/visium/visium-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Visium. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/visium-passes.def b/gcc/config/visium/visium-passes.def index 813b12a..6a4e299 100644 --- a/gcc/config/visium/visium-passes.def +++ b/gcc/config/visium/visium-passes.def @@ -1,5 +1,5 @@ /* Description of target passes for Visium. - Copyright (C) 2018-2020 Free Software Foundation, Inc. + Copyright (C) 2018-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/visium-protos.h b/gcc/config/visium/visium-protos.h index 948d5fb..f6569b5 100644 --- a/gcc/config/visium/visium-protos.h +++ b/gcc/config/visium/visium-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for Visium. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by C.Nettleton,J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 843a9a5..e0b88be 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -1,5 +1,5 @@ /* Output routines for Visium. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by C.Nettleton, J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.h b/gcc/config/visium/visium.h index 5cb940f..66e3dec 100644 --- a/gcc/config/visium/visium.h +++ b/gcc/config/visium/visium.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Visium. - Copyright (C) 2002-2020 Free Software Foundation, Inc. + Copyright (C) 2002-2021 Free Software Foundation, Inc. Contributed by C.Nettleton, J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md index 07f2ea8..83ccf08 100644 --- a/gcc/config/visium/visium.md +++ b/gcc/config/visium/visium.md @@ -1,5 +1,5 @@ ;; Machine description for Visium. -;; Copyright (C) 2002-2020 Free Software Foundation, Inc. +;; Copyright (C) 2002-2021 Free Software Foundation, Inc. ;; Contributed by C.Nettleton, J.P.Parkes and P.Garbett. ;; This file is part of GCC. diff --git a/gcc/config/visium/visium.opt b/gcc/config/visium/visium.opt index 9c2bf6d..da3f9bc 100644 --- a/gcc/config/visium/visium.opt +++ b/gcc/config/visium/visium.opt @@ -1,5 +1,5 @@ ; Options for Visium. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -29,7 +29,7 @@ Target RejectNegative Link with libc.a and libsim.a. mfpu -Target Report Mask(FPU) +Target Mask(FPU) Use hardware FP (default). mhard-float @@ -61,11 +61,11 @@ EnumValue Enum(visium_processor_type) String(gr6) Value(PROCESSOR_GR6) msv-mode -Target RejectNegative Report Mask(SV_MODE) +Target RejectNegative Mask(SV_MODE) Generate code for the supervisor mode (default). muser-mode -Target RejectNegative Report InverseMask(SV_MODE) +Target RejectNegative InverseMask(SV_MODE) Generate code for the user mode. menable-trampolines diff --git a/gcc/config/vms/make-crtlmap.awk b/gcc/config/vms/make-crtlmap.awk index fce5c7d..6f6b8b5 100644 --- a/gcc/config/vms/make-crtlmap.awk +++ b/gcc/config/vms/make-crtlmap.awk @@ -1,5 +1,5 @@ # Generate the VMS crtl map -# Copyright (C) 2011-2020 Free Software Foundation, Inc. +# Copyright (C) 2011-2021 Free Software Foundation, Inc. BEGIN { is_first = 1; diff --git a/gcc/config/vms/t-vms b/gcc/config/vms/t-vms index e0aee46..74415b9 100644 --- a/gcc/config/vms/t-vms +++ b/gcc/config/vms/t-vms @@ -1,4 +1,4 @@ -# Copyright (C) 2009-2020 Free Software Foundation, Inc. +# Copyright (C) 2009-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/t-vmsnative b/gcc/config/vms/t-vmsnative index a66603c..875b705 100644 --- a/gcc/config/vms/t-vmsnative +++ b/gcc/config/vms/t-vmsnative @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2020 Free Software Foundation, Inc. +# Copyright (C) 2010-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/vms-ar.c b/gcc/config/vms/vms-ar.c index 9e22cfa..8c111b0 100644 --- a/gcc/config/vms/vms-ar.c +++ b/gcc/config/vms/vms-ar.c @@ -1,5 +1,5 @@ /* VMS archive wrapper. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by AdaCore. This file is part of GCC. diff --git a/gcc/config/vms/vms-c.c b/gcc/config/vms/vms-c.c index 0918efd..1de696b 100644 --- a/gcc/config/vms/vms-c.c +++ b/gcc/config/vms/vms-c.c @@ -1,5 +1,5 @@ /* VMS specific, C compiler specific functions. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by Tristan Gingold (gingold@adacore.com). This file is part of GCC. diff --git a/gcc/config/vms/vms-f.c b/gcc/config/vms/vms-f.c index 4159876..bee489e 100644 --- a/gcc/config/vms/vms-f.c +++ b/gcc/config/vms/vms-f.c @@ -1,5 +1,5 @@ /* VMS support needed only by Fortran frontends. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-ld.c b/gcc/config/vms/vms-ld.c index 8bb6e28..451ad0d 100644 --- a/gcc/config/vms/vms-ld.c +++ b/gcc/config/vms/vms-ld.c @@ -1,5 +1,5 @@ /* VMS linker wrapper. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. Contributed by AdaCore This file is part of GCC. diff --git a/gcc/config/vms/vms-opts.h b/gcc/config/vms/vms-opts.h index a2aa936..be375f8 100644 --- a/gcc/config/vms/vms-opts.h +++ b/gcc/config/vms/vms-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for OpenVMS. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-protos.h b/gcc/config/vms/vms-protos.h index 696c6be..ec16f7f 100644 --- a/gcc/config/vms/vms-protos.h +++ b/gcc/config/vms/vms-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for VMS. - Copyright (C) 2011-2020 Free Software Foundation, Inc. + Copyright (C) 2011-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-stdint.h b/gcc/config/vms/vms-stdint.h index fdb7a71..f3f3ac3 100644 --- a/gcc/config/vms/vms-stdint.h +++ b/gcc/config/vms/vms-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on VMS systems. - Copyright (C) 2012-2020 Free Software Foundation, Inc. + Copyright (C) 2012-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms.c b/gcc/config/vms/vms.c index 6cde159..1ee1c86 100644 --- a/gcc/config/vms/vms.c +++ b/gcc/config/vms/vms.c @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. 32bit VMS version. - Copyright (C) 2009-2020 Free Software Foundation, Inc. + Copyright (C) 2009-2021 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/vms/vms.h b/gcc/config/vms/vms.h index f663f0f..6fa17f0 100644 --- a/gcc/config/vms/vms.h +++ b/gcc/config/vms/vms.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. VMS common version. - Copyright (C) 2003-2020 Free Software Foundation, Inc. + Copyright (C) 2003-2021 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/vms/vms.opt b/gcc/config/vms/vms.opt index 2dda12e..1292b59 100644 --- a/gcc/config/vms/vms.opt +++ b/gcc/config/vms/vms.opt @@ -1,4 +1,4 @@ -; Copyright (C) 2009-2020 Free Software Foundation, Inc. +; Copyright (C) 2009-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -23,7 +23,7 @@ map Target RejectNegative mmalloc64 -Target Report Var(flag_vms_malloc64) Init(1) +Target Var(flag_vms_malloc64) Init(1) Malloc data into P2 space. mdebug-main= @@ -31,11 +31,11 @@ Target RejectNegative Joined Var(vms_debug_main) Set name of main routine for the debugger. mvms-return-codes -Target Report Var(flag_vms_return_codes) +Target Var(flag_vms_return_codes) Use VMS exit codes instead of posix ones. mpointer-size= -Target Joined Report RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE) +Target Joined RejectNegative Enum(vms_pointer_size) Var(flag_vms_pointer_size) Init(VMS_POINTER_SIZE_NONE) -mpointer-size=[no,32,short,64,long] Set the default pointer size. Enum diff --git a/gcc/config/vms/x-vms b/gcc/config/vms/x-vms index 14c8f9f..21a698a 100644 --- a/gcc/config/vms/x-vms +++ b/gcc/config/vms/x-vms @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2020 Free Software Foundation, Inc. +# Copyright (C) 2001-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/xm-vms.h b/gcc/config/vms/xm-vms.h index e7f510c..3728e06 100644 --- a/gcc/config/vms/xm-vms.h +++ b/gcc/config/vms/xm-vms.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on VMS using a Unix style C library. - Copyright (C) 1996-2020 Free Software Foundation, Inc. + Copyright (C) 1996-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vx-common.h b/gcc/config/vx-common.h index 9cd7b3d..7dd4dee 100644 --- a/gcc/config/vx-common.h +++ b/gcc/config/vx-common.h @@ -1,5 +1,5 @@ /* Target-independent configuration for VxWorks and VxWorks AE. - Copyright (C) 2005-2020 Free Software Foundation, Inc. + Copyright (C) 2005-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/vxworks-c.c b/gcc/config/vxworks-c.c index 6fd82c3..318c3bb 100644 --- a/gcc/config/vxworks-c.c +++ b/gcc/config/vxworks-c.c @@ -1,5 +1,5 @@ /* C-family target hooks initializer for VxWorks targets. - Copyright (C) 2019-2020 Free Software Foundation, Inc. + Copyright (C) 2019-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks-dummy.h b/gcc/config/vxworks-dummy.h index 02b9b2e..49a9bac 100644 --- a/gcc/config/vxworks-dummy.h +++ b/gcc/config/vxworks-dummy.h @@ -1,5 +1,5 @@ /* Dummy definitions of VxWorks-related macros - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks-stdint.h b/gcc/config/vxworks-stdint.h index 648c8e1..3c9448c 100644 --- a/gcc/config/vxworks-stdint.h +++ b/gcc/config/vxworks-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using VxWorks. - Copyright (C) 2017-2020 Free Software Foundation, Inc. + Copyright (C) 2017-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks.c b/gcc/config/vxworks.c index b67d21d..51f4675 100644 --- a/gcc/config/vxworks.c +++ b/gcc/config/vxworks.c @@ -1,5 +1,5 @@ /* Common VxWorks target definitions for GNU compiler. - Copyright (C) 2007-2020 Free Software Foundation, Inc. + Copyright (C) 2007-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index cd43139..e41f16a 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -1,5 +1,5 @@ /* Common VxWorks target definitions for GNU compiler. - Copyright (C) 1999-2020 Free Software Foundation, Inc. + Copyright (C) 1999-2021 Free Software Foundation, Inc. Contributed by Wind River Systems. Rewritten by CodeSourcery, LLC. diff --git a/gcc/config/vxworks.opt b/gcc/config/vxworks.opt index 65295f1..9e3abef 100644 --- a/gcc/config/vxworks.opt +++ b/gcc/config/vxworks.opt @@ -1,6 +1,6 @@ ; Processor-independent options for VxWorks. ; -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; Contributed by CodeSourcery, LLC. ; ; This file is part of GCC. @@ -32,7 +32,7 @@ Xbind-now Driver Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) mrtp -Target Report RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) +Target RejectNegative Mask(VXWORKS_RTP) Condition(VXWORKS_KIND == VXWORKS_KIND_NORMAL) Assume the VxWorks RTP environment. ; VxWorks AE has two modes: kernel mode and vThreads mode. In diff --git a/gcc/config/vxworksae.h b/gcc/config/vxworksae.h index 7509931..0f9b553 100644 --- a/gcc/config/vxworksae.h +++ b/gcc/config/vxworksae.h @@ -1,5 +1,5 @@ /* Common VxWorks AE target definitions for GNU compiler. - Copyright (C) 2004-2020 Free Software Foundation, Inc. + Copyright (C) 2004-2021 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/winnt-c.c b/gcc/config/winnt-c.c index f4d412f..03da8fd 100644 --- a/gcc/config/winnt-c.c +++ b/gcc/config/winnt-c.c @@ -1,5 +1,5 @@ /* Default C-family target hooks initializer. - Copyright (C) 2013-2020 Free Software Foundation, Inc. + Copyright (C) 2013-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md index 90314d5..1db4b17 100644 --- a/gcc/config/xtensa/constraints.md +++ b/gcc/config/xtensa/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Xtensa. -;; Copyright (C) 2006-2020 Free Software Foundation, Inc. +;; Copyright (C) 2006-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/xtensa/elf.h b/gcc/config/xtensa/elf.h index 48e2590..5ec7e8c 100644 --- a/gcc/config/xtensa/elf.h +++ b/gcc/config/xtensa/elf.h @@ -1,6 +1,6 @@ /* Xtensa/Elf configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/elf.opt b/gcc/config/xtensa/elf.opt index 6544d1b..705023d 100644 --- a/gcc/config/xtensa/elf.opt +++ b/gcc/config/xtensa/elf.opt @@ -1,6 +1,6 @@ ; Xtensa ELF (bare metal) options. -; Copyright (C) 2011-2020 Free Software Foundation, Inc. +; Copyright (C) 2011-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/xtensa/linux.h b/gcc/config/xtensa/linux.h index bd20595..468a484 100644 --- a/gcc/config/xtensa/linux.h +++ b/gcc/config/xtensa/linux.h @@ -1,6 +1,6 @@ /* Xtensa Linux configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 1721640..f55b877 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Xtensa. -;; Copyright (C) 2005-2020 Free Software Foundation, Inc. +;; Copyright (C) 2005-2021 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -25,9 +25,8 @@ (define_predicate "addsubx_operand" (and (match_code "const_int") - (match_test "INTVAL (op) == 2 - || INTVAL (op) == 4 - || INTVAL (op) == 8"))) + (match_test "INTVAL (op) >= 1 + && INTVAL (op) <= 3"))) (define_predicate "arith_operand" (ior (and (match_code "const_int") diff --git a/gcc/config/xtensa/t-xtensa b/gcc/config/xtensa/t-xtensa index d46647b..973815c 100644 --- a/gcc/config/xtensa/t-xtensa +++ b/gcc/config/xtensa/t-xtensa @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2020 Free Software Foundation, Inc. +# Copyright (C) 2002-2021 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/xtensa/uclinux.h b/gcc/config/xtensa/uclinux.h index 374d2947..2c3831e 100644 --- a/gcc/config/xtensa/uclinux.h +++ b/gcc/config/xtensa/uclinux.h @@ -1,6 +1,6 @@ /* Xtensa uClinux configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/uclinux.opt b/gcc/config/xtensa/uclinux.opt index 53774fe..9a6b2f5 100644 --- a/gcc/config/xtensa/uclinux.opt +++ b/gcc/config/xtensa/uclinux.opt @@ -1,6 +1,6 @@ ; Xtensa uClinux options. -; Copyright (C) 2015-2020 Free Software Foundation, Inc. +; Copyright (C) 2015-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index 18d8035..20215f9 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for GNU compiler for Xtensa. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index be1eb21..9a661dd 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Tensilica's Xtensa architecture. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. @@ -1082,6 +1082,21 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode) if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) { + /* Try to emit MOVI + SLLI sequence, that is smaller + than L32R + literal. */ + if (optimize_size && mode == SImode && register_operand (dst, mode)) + { + HOST_WIDE_INT srcval = INTVAL (src); + int shift = ctz_hwi (srcval); + + if (xtensa_simm12b (srcval >> shift)) + { + emit_move_insn (dst, GEN_INT (srcval >> shift)); + emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift))); + return 1; + } + } + src = force_const_mem (SImode, src); operands[1] = src; } diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 33bfe45..b01f6af 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -1,5 +1,5 @@ /* Definitions of Tensilica's Xtensa target machine for GNU compiler. - Copyright (C) 2001-2020 Free Software Foundation, Inc. + Copyright (C) 2001-2021 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 749fe47..cdf22f1 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1,5 +1,5 @@ ;; GCC machine description for Tensilica's Xtensa architecture. -;; Copyright (C) 2001-2020 Free Software Foundation, Inc. +;; Copyright (C) 2001-2021 Free Software Foundation, Inc. ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. ;; This file is part of GCC. @@ -162,11 +162,14 @@ (define_insn "*addx" [(set (match_operand:SI 0 "register_operand" "=a") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 3 "addsubx_operand" "i")) + (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "addsubx_operand" "i")) (match_operand:SI 2 "register_operand" "r")))] "TARGET_ADDX" - "addx%3\t%0, %1, %2" +{ + operands[3] = GEN_INT (1 << INTVAL (operands[3])); + return "addx%3\t%0, %1, %2"; +} [(set_attr "type" "arith") (set_attr "mode" "SI") (set_attr "length" "3")]) @@ -196,11 +199,14 @@ (define_insn "*subx" [(set (match_operand:SI 0 "register_operand" "=a") - (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 3 "addsubx_operand" "i")) + (minus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "addsubx_operand" "i")) (match_operand:SI 2 "register_operand" "r")))] "TARGET_ADDX" - "subx%3\t%0, %1, %2" +{ + operands[3] = GEN_INT (1 << INTVAL (operands[3])); + return "subx%3\t%0, %1, %2"; +} [(set_attr "type" "arith") (set_attr "mode" "SI") (set_attr "length" "3")]) @@ -463,6 +469,27 @@ }) +;; Byte swap. + +(define_insn "bswapsi2" + [(set (match_operand:SI 0 "register_operand" "=&a") + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "!optimize_size" + "ssai\t8\;srli\t%0, %1, 16\;src\t%0, %0, %1\;src\t%0, %0, %0\;src\t%0, %1, %0" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "15")]) + +(define_insn "bswapdi2" + [(set (match_operand:DI 0 "register_operand" "=&a") + (bswap:DI (match_operand:DI 1 "register_operand" "r")))] + "!optimize_size" + "ssai\t8\;srli\t%0, %D1, 16\;src\t%0, %0, %D1\;src\t%0, %0, %0\;src\t%0, %D1, %0\;srli\t%D0, %1, 16\;src\t%D0, %D0, %1\;src\t%D0, %D0, %D0\;src\t%D0, %1, %D0" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "27")]) + + ;; Negation and one's complement. (define_insn "negsi2" @@ -721,8 +748,23 @@ (match_operand:DI 1 "general_operand" ""))] "" { - if (CONSTANT_P (operands[1]) && !TARGET_CONST16) - operands[1] = force_const_mem (DImode, operands[1]); + if (CONSTANT_P (operands[1])) + { + /* Split in halves if 64-bit Const-to-Reg moves + because of offering further optimization opportunities. */ + if (register_operand (operands[0], DImode)) + { + rtx first, second; + + split_double (operands[1], &first, &second); + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first)); + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second)); + DONE; + } + + if (!TARGET_CONST16) + operands[1] = force_const_mem (DImode, operands[1]); + } if (!register_operand (operands[0], DImode) && !register_operand (operands[1], DImode)) @@ -1050,6 +1092,16 @@ operands[1] = xtensa_copy_incoming_a7 (operands[1]); }) +(define_insn "*ashlsi3_1" + [(set (match_operand:SI 0 "register_operand" "=a") + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (const_int 1)))] + "TARGET_DENSITY" + "add.n\t%0, %1, %1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + (define_insn "ashlsi3_internal" [(set (match_operand:SI 0 "register_operand" "=a,a") (ashift:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1062,6 +1114,17 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) +(define_insn "*ashlsi3_3x" + [(set (match_operand:SI 0 "register_operand" "=a") + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))))] + "" + "ssa8b\t%2\;sll\t%0, %1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1074,6 +1137,17 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) +(define_insn "*ashrsi3_3x" + [(set (match_operand:SI 0 "register_operand" "=a") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))))] + "" + "ssa8l\t%2\;sra\t%0, %1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1093,6 +1167,17 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) +(define_insn "*lshrsi3_3x" + [(set (match_operand:SI 0 "register_operand" "=a") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))))] + "" + "ssa8l\t%2\;srl\t%0, %1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") (rotate:SI (match_operand:SI 1 "register_operand" "r,r") diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt index 0c4aa92..a1b4e92 100644 --- a/gcc/config/xtensa/xtensa.opt +++ b/gcc/config/xtensa/xtensa.opt @@ -1,6 +1,6 @@ ; Options for the Tensilica Xtensa port of the compiler. -; Copyright (C) 2005-2020 Free Software Foundation, Inc. +; Copyright (C) 2005-2021 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -19,11 +19,11 @@ ; <http://www.gnu.org/licenses/>. mconst16 -Target Report Mask(CONST16) +Target Mask(CONST16) Use CONST16 instruction to load constants. mforce-no-pic -Target Report Mask(FORCE_NO_PIC) +Target Mask(FORCE_NO_PIC) Disable position-independent code (PIC) for use in OS kernel code. mlongcalls @@ -39,20 +39,20 @@ Target Intersperse literal pools with code in the text section. mauto-litpools -Target Report Mask(AUTO_LITPOOLS) +Target Mask(AUTO_LITPOOLS) Relax literals in assembler and place them automatically in the text section. mserialize-volatile -Target Report Mask(SERIALIZE_VOLATILE) +Target Mask(SERIALIZE_VOLATILE) -mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions. TargetVariable int xtensa_windowed_abi = -1 mabi=call0 -Target Report RejectNegative Var(xtensa_windowed_abi, 0) +Target RejectNegative Var(xtensa_windowed_abi, 0) Use call0 ABI. mabi=windowed -Target Report RejectNegative Var(xtensa_windowed_abi, 1) +Target RejectNegative Var(xtensa_windowed_abi, 1) Use windowed registers ABI. |