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| author | Daniel Jacobowitz <dan@debian.org> | 2004-10-12 19:28:56 +0000 |
|---|---|---|
| committer | Daniel Jacobowitz <drow@gcc.gnu.org> | 2004-10-12 19:28:56 +0000 |
| commit | 888d2cd6b58f62d8492ec2a937de25c634966301 (patch) | |
| tree | 32fb1749887c1bb5a4613d1d87b18c9a8537c8f4 /gcc/config | |
| parent | 3d4818fd4dfa6fec3d7603ef2b7e13dd8d661680 (diff) | |
| download | gcc-888d2cd6b58f62d8492ec2a937de25c634966301.zip gcc-888d2cd6b58f62d8492ec2a937de25c634966301.tar.gz gcc-888d2cd6b58f62d8492ec2a937de25c634966301.tar.bz2 | |
* defaults.h (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P)
(MODE_BASE_REG_REG_CLASS, REGNO_MODE_OK_FOR_REG_BASE_P)
(REG_MODE_OK_FOR_REG_BASE_P): Provide default definitions.
* regclass.c (record_address_regs): Remove ifdef. Use
REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS.
* regrename.c (REG_MODE_OK_FOR_BASE_P): Remove unnecessary
definition.
(scan_rtx_address, replace_oldest_value_addr): Use
REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS.
* reload.c (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Remove
unnecessary definitions.
(find_reloads_address_1): Support REG_MODE_OK_FOR_REG_BASE_P
and MODE_BASE_REG_REG_CLASS.
* config/arm/arm.h (MODE_BASE_REG_CLASS): Don't check reload_completed.
(MODE_BASE_REG_REG_CLASS): Define.
(REGNO_MODE_OK_FOR_REG_BASE_P): Define.
(REG_MODE_OK_FOR_REG_BASE_P): Define.
* doc/tm.texi (Register Classes): Document MODE_BASE_REG_REG_CLASS,
REG_MODE_OK_FOR_REG_BASE_P, and REGNO_MODE_OK_FOR_REG_BASE_P.
From-SVN: r88948
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm.h | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index beecc29..446062f 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1218,12 +1218,14 @@ enum reg_class /* For the Thumb the high registers cannot be used as base registers when addressing quantities in QI or HI mode; if we don't know the - mode, then we must be conservative. After reload we must also be - conservative, since we can't support SP+reg addressing, and we - can't fix up any bad substitutions. */ + mode, then we must be conservative. */ #define MODE_BASE_REG_CLASS(MODE) \ (TARGET_ARM ? GENERAL_REGS : \ - (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) + (((MODE) == SImode) ? BASE_REGS : LO_REGS)) + +/* For Thumb we can not support SP+reg addressing, so we return LO_REGS + instead of BASE_REGS. */ +#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows registers explicitly used in the rtl to be used as spill registers @@ -1980,6 +1982,11 @@ typedef struct ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ : ARM_REGNO_OK_FOR_BASE_P (REGNO)) +/* Nonzero if X can be the base register in a reg+reg addressing mode. + For Thumb, we can not use SP + reg, so reject SP. */ +#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ + REGNO_OK_FOR_INDEX_P (X) + /* For ARM code, we don't care about the mode, but for Thumb, the index must be suitable for use in a QImode load. */ #define REGNO_OK_FOR_INDEX_P(REGNO) \ @@ -2123,6 +2130,10 @@ typedef struct ? THUMB_REG_OK_FOR_INDEX_P (X) \ : ARM_REG_OK_FOR_INDEX_P (X)) +/* Nonzero if X can be the base register in a reg+reg addressing mode. + For Thumb, we can not use SP + reg, so reject SP. */ +#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ + REG_OK_FOR_INDEX_P (X) /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. |