aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
diff options
context:
space:
mode:
authorRichard Henderson <rth@redhat.com>2011-11-30 08:10:24 -0800
committerRichard Henderson <rth@gcc.gnu.org>2011-11-30 08:10:24 -0800
commit2e65f38f1bf1f04c530bfeb6b543f084564eec3d (patch)
treef7ebc47322ba3389b5583ce189866e18f3530ba4 /gcc/config
parent99ee7887c639daad4ae2a9440eef9bab15da58c6 (diff)
downloadgcc-2e65f38f1bf1f04c530bfeb6b543f084564eec3d.zip
gcc-2e65f38f1bf1f04c530bfeb6b543f084564eec3d.tar.gz
gcc-2e65f38f1bf1f04c530bfeb6b543f084564eec3d.tar.bz2
sparc: Add -mmemory-model command-line option.
* config/sparc/sparc-opts.h (enum sparc_memory_model_type): New. * config/sparc/sparc.opt (mmemory-model=): New option. * doc/invoke.texi (Sparc Options): Document it. * config/sparc/sparc.c (sparc_option_override): Provide default for sparc_memory_model. (sparc_emit_membar_for_model): Omit barrier combinations that are implied by the memory model. From-SVN: r181853
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/sparc/sparc-opts.h10
-rw-r--r--gcc/config/sparc/sparc.c49
-rw-r--r--gcc/config/sparc/sparc.opt22
3 files changed, 80 insertions, 1 deletions
diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h
index 266cb14..7682eb9 100644
--- a/gcc/config/sparc/sparc-opts.h
+++ b/gcc/config/sparc/sparc-opts.h
@@ -47,4 +47,14 @@ enum processor_type {
PROCESSOR_NATIVE
};
+/* Sparc system memory model. See Appendix D in the Sparc V9 manual
+ for formal specification, and Appendix J for more discussion. */
+enum sparc_memory_model_type {
+ SMM_DEFAULT, /* Uninitialized. */
+ SMM_RMO, /* Relaxed Memory Order. */
+ SMM_PSO, /* Partial Store Order. */
+ SMM_TSO, /* Total Store Order. */
+ SMM_SC /* Sequential Consistency. */
+};
+
#endif
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 7db216a..713db26 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1160,6 +1160,17 @@ sparc_option_override (void)
gcc_unreachable ();
};
+ if (sparc_memory_model == SMM_DEFAULT)
+ {
+ /* Choose the most relaxed model for the processor. */
+ if (TARGET_V9)
+ sparc_memory_model = SMM_RMO;
+ else if (TARGET_V8)
+ sparc_memory_model = SMM_PSO;
+ else
+ sparc_memory_model = SMM_SC;
+ }
+
#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
target_flags |= MASK_LONG_DOUBLE_128;
@@ -10863,7 +10874,40 @@ sparc_emit_membar_for_model (enum memmodel model,
const int LoadStore = 4;
const int StoreStore = 8;
- int mm = 0;
+ int mm = 0, implied = 0;
+
+ switch (sparc_memory_model)
+ {
+ case SMM_SC:
+ /* Sequential Consistency. All memory transactions are immediately
+ visible in sequential execution order. No barriers needed. */
+ implied = LoadLoad | StoreLoad | LoadStore | StoreStore;
+ break;
+
+ case SMM_TSO:
+ /* Total Store Ordering: all memory transactions with store semantics
+ are followed by an implied StoreStore. */
+ implied |= StoreStore;
+ /* FALLTHRU */
+
+ case SMM_PSO:
+ /* Partial Store Ordering: all memory transactions with load semantics
+ are followed by an implied LoadLoad | LoadStore. */
+ implied |= LoadLoad | LoadStore;
+
+ /* If we're not looking for a raw barrer (before+after), then atomic
+ operations get the benefit of being both load and store. */
+ if (load_store == 3 && before_after == 2)
+ implied |= StoreLoad | StoreStore;
+ /* FALLTHRU */
+
+ case SMM_RMO:
+ /* Relaxed Memory Ordering: no implicit bits. */
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
if (before_after & 1)
{
@@ -10890,6 +10934,9 @@ sparc_emit_membar_for_model (enum memmodel model,
}
}
+ /* Remove the bits implied by the system memory model. */
+ mm &= ~implied;
+
/* For raw barriers (before+after), always emit a barrier.
This will become a compile-time barrier if needed. */
if (mm || before_after == 3)
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index cb807fd..01f3d43 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -215,3 +215,25 @@ Mask(V9)
Mask(DEPRECATED_V8_INSNS)
;; Generate code that uses the V8 instructions deprecated
;; in the V9 architecture.
+
+mmemory-model=
+Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
+Specify the memory model in effect for the program.
+
+Enum
+Name(sparc_memory_model) Type(enum sparc_memory_model_type)
+
+EnumValue
+Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
+
+EnumValue
+Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
+
+EnumValue
+Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
+
+EnumValue
+Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
+
+EnumValue
+Enum(sparc_memory_model) String(sc) Value(SMM_SC)