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| author | Uros Bizjak <uros@gcc.gnu.org> | 2016-12-28 16:16:26 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-12-28 16:16:26 +0100 |
| commit | 5c8617dce6534f9438d4a7d110b277b2fddf19c5 (patch) | |
| tree | 8dc69a56a38e95c09a4c283eaac811ff475b6736 /gcc/config | |
| parent | c05169aab6c52fb250ad4d113d2f3d965a9c6416 (diff) | |
| download | gcc-5c8617dce6534f9438d4a7d110b277b2fddf19c5.zip gcc-5c8617dce6534f9438d4a7d110b277b2fddf19c5.tar.gz gcc-5c8617dce6534f9438d4a7d110b277b2fddf19c5.tar.bz2 | |
re PR target/78904 (zero-extracts are not effective)
PR target/78904
* config/i386/constraints.md (Bn): New special memory constraint.
* config/i386/predicates.md (norex_memory_operand): New predicate.
* config/i386/i386.md (*extzvqi_mem_rex64): New insn pattern and
corresponding peephole2 pattern.
testsuite/ChangeLog:
PR target/78904
* gcc.target/i386/pr78904-4.c: New test.
* gcc.target/i386/pr78904-5.c: Ditto.
From-SVN: r243955
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/constraints.md | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 28 | ||||
| -rw-r--r-- | gcc/config/i386/predicates.md | 4 |
3 files changed, 36 insertions, 1 deletions
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 6aa2e4f..19edd25 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -169,6 +169,7 @@ ;; g GOT memory operand. ;; m Vector memory operand ;; c Constant memory operand +;; n Memory operand without REX prefix ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. @@ -191,6 +192,10 @@ (and (match_operand 0 "memory_operand") (match_test "constant_address_p (XEXP (op, 0))"))) +(define_special_memory_constraint "Bn" + "@internal Memory operand without REX prefix." + (match_operand 0 "norex_memory_operand")) + (define_constraint "Bs" "@internal Sibcall memory operand." (ior (and (not (match_test "TARGET_X32")) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 13769f9..cf9dc03 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2835,9 +2835,20 @@ [(set_attr "type" "imovx") (set_attr "mode" "SI")]) +(define_insn "*extzvqi_mem_rex64" + [(set (match_operand:QI 0 "norex_memory_operand" "=Bn") + (subreg:QI + (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") + (const_int 8) + (const_int 8)) 0))] + "TARGET_64BIT && reload_completed" + "mov{b}\t{%h1, %0|%0, %h1}" + [(set_attr "type" "imov") + (set_attr "mode" "QI")]) + (define_insn "*extzvqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m") - (subreg:QI + (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q") (const_int 8) (const_int 8)) 0))] @@ -2863,6 +2874,21 @@ (const_string "SI") (const_string "QI")))]) +(define_peephole2 + [(set (match_operand:QI 0 "register_operand") + (subreg:QI + (zero_extract:SI (match_operand 1 "ext_register_operand") + (const_int 8) + (const_int 8)) 0)) + (set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))] + "TARGET_64BIT + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 2) + (subreg:QI + (zero_extract:SI (match_dup 1) + (const_int 8) + (const_int 8)) 0))]) + (define_expand "insv<mode>" [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand") (match_operand:SI 1 "const_int_operand") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index b2d847e..a1ea34f 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1037,6 +1037,10 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "const0_operand"))) +(define_predicate "norex_memory_operand" + (and (match_operand 0 "memory_operand") + (not (match_test "x86_extended_reg_mentioned_p (op)")))) + ;; Return true for RTX codes that force SImode address. (define_predicate "SImode_address_operand" (match_code "subreg,zero_extend,and")) |