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| author | Kirill Yukhin <kirill.yukhin@intel.com> | 2013-12-05 07:54:43 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2013-12-05 07:54:43 +0000 |
| commit | 9eb8c09fdae1c41a03d30a1a386dafbf25cb1b82 (patch) | |
| tree | f2a3ad74f18acbd28a6bbdac16e49a625925e59c /gcc/config | |
| parent | c012dc48c02e9cfc761e09810a78e3eee2cc7579 (diff) | |
| download | gcc-9eb8c09fdae1c41a03d30a1a386dafbf25cb1b82.zip gcc-9eb8c09fdae1c41a03d30a1a386dafbf25cb1b82.tar.gz gcc-9eb8c09fdae1c41a03d30a1a386dafbf25cb1b82.tar.bz2 | |
ia64.md (prologue_allocate_stack): Block auto- generation of predicated version.
ChangeLog/
* config/ia64/ia64.md (prologue_allocate_stack): Block auto-
generation of predicated version.
(epilogue_deallocate_stack): Ditto.
(prologue_allocate_stack_pr): Add explicit predicated version.
(epilogue_deallocate_stack_pr): Ditto.
* config/ia64/ia64.c (ia64_single_set): Use explicit versions.
testsuite/ChangeLog/
* gcc.target/ia64/pr52731.c: New.
From-SVN: r205692
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/ia64/ia64.c | 2 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.md | 41 |
2 files changed, 41 insertions, 2 deletions
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index df4a4b0..8f305c1 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -7159,7 +7159,9 @@ ia64_single_set (rtx insn) switch (recog_memoized (insn)) { case CODE_FOR_prologue_allocate_stack: + case CODE_FOR_prologue_allocate_stack_pr: case CODE_FOR_epilogue_deallocate_stack: + case CODE_FOR_epilogue_deallocate_stack_pr: ret = XVECEXP (x, 0, 0); break; diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 4d9d4e0..bc4e8cb 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -4652,6 +4652,8 @@ ;; This prevents the scheduler from moving the SP decrement past FP-relative ;; stack accesses. This is the same as adddi3 plus the extra set. +;; Explicit predicated version of insn needed to check by CODE_FOR_ +;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. (define_insn "prologue_allocate_stack" [(set (match_operand:DI 0 "register_operand" "=r,r,r") @@ -4664,10 +4666,31 @@ add %0 = %1, %2 adds %0 = %2, %1 addl %0 = %2, %1" - [(set_attr "itanium_class" "ialu")]) + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) + +(define_insn "prologue_allocate_stack_pr" + [(cond_exec (match_operator 0 ("predicate_operator") + [(match_operand:BI 1 ("register_operand") ("c,c,c")) + (const_int 0)]) + (parallel + [(set (match_operand:DI 2 "register_operand" "=r,r,r") + (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a") + (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J"))) + (set (match_operand:DI 5 "register_operand" "+r,r,r") + (match_dup 5))]))] + "" + "@ + (%J0) add %2 = %3, %4 + (%J0) adds %2 = %3, %4 + (%J0) addl %2 = %3, %4" + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) ;; This prevents the scheduler from moving the SP restore past FP-relative ;; stack accesses. This is similar to movdi plus the extra set. +;; Explicit predicated version of insn needed to check by CODE_FOR_ +;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. (define_insn "epilogue_deallocate_stack" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4675,7 +4698,21 @@ (set (match_dup 1) (match_dup 1))] "" "mov %0 = %1" - [(set_attr "itanium_class" "ialu")]) + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) + +(define_insn "epilogue_deallocate_stack_pr" + [(cond_exec (match_operator 0 ("predicate_operator") + [(match_operand:BI 1 ("register_operand") ("c")) + (const_int 0)]) + (parallel + [(set (match_operand:DI 2 "register_operand" "=r") + (match_operand:DI 3 "register_operand" "+r")) + (set (match_dup 3) (match_dup 3))]))] + "" + "(%J0) mov %2 = %3" + [(set_attr "itanium_class" "ialu") + (set_attr "predicable" "no")]) ;; As USE insns aren't meaningful after reload, this is used instead ;; to prevent deleting instructions setting registers for EH handling |