Remove COPY_HARD_REG_SET

This patch replaces "COPY_HARD_REG_SET (x, y)" with "x = y".

2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* hard-reg-set.h (COPY_HARD_REG_SET): Delete.
	* caller-save.c (save_call_clobbered_regs): Use assignment instead
	of COPY_HARD_REG_SET.
	* config/epiphany/epiphany.c (epiphany_compute_frame_size): Likewise.
	(epiphany_conditional_register_usage): Likewise.
	* config/frv/frv.c (frv_ifcvt_modify_tests): Likewise.
	* config/gcn/gcn.c (gcn_md_reorg): Likewise.
	* config/ia64/ia64.c (ia64_compute_frame_size): Likewise.
	* config/m32c/m32c.c (m32c_register_move_cost): Likewise.
	* config/m68k/m68k.c (m68k_conditional_register_usage): Likewise.
	* config/mips/mips.c (mips_class_max_nregs): Likewise.
	* config/pdp11/pdp11.c (pdp11_conditional_register_usage): Likewise.
	* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
	* config/sh/sh.c (output_stack_adjust): Likewise.
	* final.c (collect_fn_hard_reg_usage): Likewise.
	(get_call_reg_set_usage): Likewise.
	* ira-build.c (ira_create_object, remove_low_level_allocnos)
	(ira_flattening): Likewise.
	* ira-color.c (add_allocno_hard_regs, add_allocno_hard_regs_to_forest)
	(setup_left_conflict_sizes_p, setup_profitable_hard_regs)
	(get_conflict_and_start_profitable_regs, allocno_reload_assign)
	(ira_reassign_pseudos): Likewise.
	* ira-conflicts.c (print_allocno_conflicts): Likewise.
	(ira_build_conflicts): Likewise.
	* ira-costs.c (restrict_cost_classes): Likewise.
	(setup_regno_cost_classes_by_aclass): Likewise.
	* ira.c (setup_class_hard_regs, setup_alloc_regs): Likewise.
	(setup_reg_subclasses, setup_class_subset_and_memory_move_costs)
	(setup_stack_reg_pressure_class, setup_pressure_classes)
	(setup_allocno_and_important_classes, setup_class_translate_array)
	(setup_reg_class_relations, setup_prohibited_class_mode_regs)
	(ira_setup_eliminable_regset): Likewise.
	* lra-assigns.c (find_hard_regno_for_1): Likewise.
	(setup_live_pseudos_and_spill_after_risky_transforms): Likewise.
	* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
	(process_alt_operands, inherit_in_ebb): Likewise.
	* lra-lives.c (process_bb_lives): Likewise.
	* lra-spills.c (assign_spill_hard_regs): Likewise.
	* lra.c (lra): Likewise.
	* mode-switching.c (new_seginfo): Likewise.
	* postreload.c (reload_combine): Likewise.
	* reg-stack.c (straighten_stack): Likewise.
	* reginfo.c (save_register_info, restore_register_info): Likewise.
	(init_reg_sets_1, record_subregs_of_mode): Likewise
	* regrename.c (create_new_chain, rename_chains): Likewise.
	* reload1.c (order_regs_for_reload, find_reg): Likewise.
	(find_reload_regs): Likewise.
	* resource.c (find_dead_or_set_registers): Likewise.
	(mark_target_live_regs): Likewise.
	* sel-sched.c (mark_unavailable_hard_regs): Likewise.

From-SVN: r275528

10 files changed, 17 insertions, 18 deletions

diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index cc51cfa..c2e3215 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1248,7 +1248,7 @@ epiphany_compute_frame_size (int size /* # of var. bytes allocated.  */)
   current_frame_info.var_size     = var_size;
   current_frame_info.args_size    = args_size;
   current_frame_info.reg_size	  = reg_size;
-  COPY_HARD_REG_SET (current_frame_info.gmask, gmask);
+  current_frame_info.gmask	  = gmask;
   current_frame_info.first_slot		= first_slot;
   current_frame_info.last_slot		= last_slot;
   current_frame_info.first_slot_offset	= first_slot_offset;
@@ -2240,8 +2240,7 @@ epiphany_conditional_register_usage (void)
     }
   if (!TARGET_PREFER_SHORT_INSN_REGS)
     CLEAR_HARD_REG_SET (reg_class_contents[SHORT_INSN_REGS]);
-  COPY_HARD_REG_SET (reg_class_contents[SIBCALL_REGS],
-		     reg_class_contents[GENERAL_REGS]);
+  reg_class_contents[SIBCALL_REGS] = reg_class_contents[GENERAL_REGS];
   /* It would be simpler and quicker if we could just use
      AND_COMPL_HARD_REG_SET, alas, call_used_reg_set is yet uninitialized;
      it is set up later by our caller.  */
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 6008e9a..7fc8068 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -5201,7 +5201,7 @@ frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false)
      not fixed.  However, allow the ICC/ICR temporary registers to be allocated
      if we did not need to use them in reloading other registers.  */
   memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
-  COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
+  tmp_reg->regs = call_used_reg_set;
   AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
   SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
   SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index cdb1c6e..548ab17 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -4553,7 +4553,7 @@ gcn_md_reorg (void)
 	      && gcn_vmem_insn_p (itype))
 	    {
 	      HARD_REG_SET regs;
-	      COPY_HARD_REG_SET (regs, prev_insn->writes);
+	      regs = prev_insn->writes;
 	      AND_HARD_REG_SET (regs, ireads);
 	      if (hard_reg_set_intersect_p
 		  (regs, reg_class_contents[(int) SGPR_REGS]))
@@ -4583,7 +4583,7 @@ gcn_md_reorg (void)
 	      && get_attr_laneselect (insn) == LANESELECT_YES)
 	    {
 	      HARD_REG_SET regs;
-	      COPY_HARD_REG_SET (regs, prev_insn->writes);
+	      regs = prev_insn->writes;
 	      AND_HARD_REG_SET (regs, ireads);
 	      if (hard_reg_set_intersect_p
 		  (regs, reg_class_contents[(int) SGPR_REGS])
@@ -4599,7 +4599,7 @@ gcn_md_reorg (void)
 	      && itype == TYPE_VOP_DPP)
 	    {
 	      HARD_REG_SET regs;
-	      COPY_HARD_REG_SET (regs, prev_insn->writes);
+	      regs = prev_insn->writes;
 	      AND_HARD_REG_SET (regs, ireads);
 	      if (hard_reg_set_intersect_p
 		  (regs, reg_class_contents[(int) VGPR_REGS]))
@@ -4641,8 +4641,8 @@ gcn_md_reorg (void)
       back[oldest].insn = insn;
       back[oldest].unit = iunit;
       back[oldest].delayeduse = idelayeduse;
-      COPY_HARD_REG_SET (back[oldest].writes, iwrites);
-      COPY_HARD_REG_SET (back[oldest].reads, ireads);
+      back[oldest].writes = iwrites;
+      back[oldest].reads = ireads;
       back[oldest].age = 0;
       oldest = (oldest + 1) % max_waits;
 
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 3768c8b..ca69656 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -2965,7 +2965,7 @@ ia64_compute_frame_size (HOST_WIDE_INT size)
   current_frame_info.spill_cfa_off = pretend_args_size - 16;
   current_frame_info.spill_size = spill_size;
   current_frame_info.extra_spill_size = extra_spill_size;
-  COPY_HARD_REG_SET (current_frame_info.mask, mask);
+  current_frame_info.mask = mask;
   current_frame_info.n_spilled = n_spilled;
   current_frame_info.initialized = reload_completed;
 }
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index ace00e0..4e18287 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -2152,7 +2152,7 @@ m32c_register_move_cost (machine_mode mode, reg_class_t from,
   HARD_REG_SET cc;
 
 /* FIXME: pick real values, but not 2 for now.  */
-  COPY_HARD_REG_SET (cc, reg_class_contents[(int) from]);
+  cc = reg_class_contents[from];
   IOR_HARD_REG_SET (cc, reg_class_contents[(int) to]);
 
   if (mode == QImode
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 70f3e5c..fd69511 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -6555,7 +6555,7 @@ m68k_conditional_register_usage (void)
   HARD_REG_SET x;
   if (!TARGET_HARD_FLOAT)
     {
-      COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);
+      x = reg_class_contents[FP_REGS];
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
         if (TEST_HARD_REG_BIT (x, i))
 	  fixed_regs[i] = call_used_regs[i] = 1;
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c5389d2..7150a79 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -12975,7 +12975,7 @@ mips_class_max_nregs (enum reg_class rclass, machine_mode mode)
   HARD_REG_SET left;
 
   size = 0x8000;
-  COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
+  left = reg_class_contents[rclass];
   if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
     {
       if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode))
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 62a1b27..2d3b94b 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -2213,7 +2213,7 @@ pdp11_conditional_register_usage (void)
   HARD_REG_SET x;
   if (!TARGET_FPU)
     {
-      COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]);
+      x = reg_class_contents[FPU_REGS];
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )
        if (TEST_HARD_REG_BIT (x, i))
 	fixed_regs[i] = call_used_regs[i] = 1;
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e044c6e..8193c6b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -21107,9 +21107,9 @@ rs6000_register_move_cost (machine_mode mode,
      Do this first so we give best-case answers for union classes
      containing both gprs and vsx regs.  */
   HARD_REG_SET to_vsx, from_vsx;
-  COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
+  to_vsx = reg_class_contents[to];
   AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
-  COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
+  from_vsx = reg_class_contents[from];
   AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
   if (!hard_reg_set_empty_p (to_vsx)
       && !hard_reg_set_empty_p (from_vsx)
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 04c56aa..d1af580 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -6708,7 +6708,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
 	  if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0)
 	    {
 	      HARD_REG_SET temps;
-	      COPY_HARD_REG_SET (temps, call_used_reg_set);
+	      temps = call_used_reg_set;
 	      AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
 	      if (epilogue_p > 0)
 		{
@@ -6743,7 +6743,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
 	    {
 	      HARD_REG_SET temps;
 
-	      COPY_HARD_REG_SET (temps, *live_regs_mask);
+	      temps = *live_regs_mask;
 	      CLEAR_HARD_REG_BIT (temps, REGNO (reg));
 	      temp = scavenge_reg (&temps);
 	    }