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authorDavid Edelsohn <edelsohn@mhpcc.edu>1998-09-18 20:55:00 +0000
committerDavid Edelsohn <dje@gcc.gnu.org>1998-09-18 16:55:00 -0400
commit5accd82209963c5d048e6096311e9b40b48efd15 (patch)
tree69eef37b4ea439c3a864ceebed52c671f519c116 /gcc/config
parent735955227eeca4e60dad78f414b60e627e8cd207 (diff)
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toplev.c (rest_of_compilation): Set bct_p on second call to loop_optimize.
* toplev.c (rest_of_compilation): Set bct_p on second call to loop_optimize. * loop.c (loop_optimize, scan_loop, strength_reduce): New argument bct_p. (strength_reduce): Only call analyze_loop_iterations and insert_bct if bct_p set. (check_dbra_loop): Fix typo. (insert_bct): Use word_mode instead of SImode. (instrument_loop_bct): Likewise. Do not delete iteration count condition code generation insn. Initialize iteration count before loop start. * rtl.h (loop_optimize): Update prototype. * ginclude/va-ppc.h (va_arg): longlong types in overflow area are not doubleword aligned. * rs6000.c (optimization_options): New function. (secondary_reload_class): Only call true_regnum for PSEUDO_REGs. * rs6000.h (OPTIMIZATION_OPTIONS): Define. (REG_ALLOC_ORDER): Allocate highest numbered condition regsiters first; cr1 can be used for FP record condition insns. From-SVN: r22471
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/rs6000/rs6000.c46
-rw-r--r--gcc/config/rs6000/rs6000.h14
2 files changed, 51 insertions, 9 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a2b58fd..e5f199c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -347,6 +347,20 @@ rs6000_override_options (default_cpu)
SUBTARGET_OVERRIDE_OPTIONS;
#endif
}
+
+void
+optimization_options (level, size)
+ int level;
+ int size ATTRIBUTE_UNUSED;
+{
+#if 0
+#ifdef HAIFA
+ /* When optimizing, enable use of BCT instruction. */
+ if (level >= 1)
+ flag_branch_on_count_reg = 1;
+#endif
+#endif
+}
/* Do anything needed at the start of the asm file. */
@@ -1305,14 +1319,18 @@ function_arg_padding (mode, type)
Windows NT wants anything >= 8 bytes to be double word aligned.
- V.4 wants long longs to be double word aligned. */
+ V.4 wants long longs to be double word aligned.
+
+ FP emulation: double precision passed, returned, and same alignment
+ as long long. */
int
function_arg_boundary (mode, type)
enum machine_mode mode;
tree type;
{
- if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && mode == DImode)
+ if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
+ && ((mode == DImode) || (TARGET_SOFT_FLOAT && mode == DFmode)))
return 64;
if (DEFAULT_ABI != ABI_NT || TARGET_64BIT)
@@ -2188,10 +2206,7 @@ secondary_reload_class (class, mode, in)
enum machine_mode mode ATTRIBUTE_UNUSED;
rtx in;
{
- int regno = true_regnum (in);
-
- if (regno >= FIRST_PSEUDO_REGISTER)
- regno = -1;
+ int regno;
/* We can not copy a symbolic operand directly into anything other than
BASE_REGS for TARGET_ELF. So indicate that a register from BASE_REGS
@@ -2203,6 +2218,25 @@ secondary_reload_class (class, mode, in)
|| GET_CODE (in) == CONST))
return BASE_REGS;
+ if (GET_CODE (in) == REG)
+ {
+ regno = REGNO (in);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ {
+ regno = true_regnum (in);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ regno = -1;
+ }
+ }
+ else if (GET_CODE (in) == SUBREG)
+ {
+ regno = true_regnum (in);
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ regno = -1;
+ }
+ else
+ regno = -1;
+
/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
into anything. */
if (class == GENERAL_REGS || class == BASE_REGS
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9856abf..53c99d6 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -473,10 +473,17 @@ extern int rs6000_debug_arg; /* debug argument handling */
defined, is executed once just after all the command options have
been parsed.
+ Don't use this macro to turn on various extra optimizations for
+ `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
+
On the RS/6000 this is used to define the target cpu type. */
#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
+/* Define this to change the optimizations performed by default. */
+#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
+
+
/* Show we can debug even without a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
@@ -712,9 +719,10 @@ extern int rs6000_debug_arg; /* debug argument handling */
fp13 - fp2 (not saved; incoming fp arg registers)
fp1 (not saved; return value)
fp31 - fp14 (saved; order given to save least number)
- cr1, cr6, cr7 (not saved or special)
+ cr7, cr6 (not saved or special)
+ cr1 (not saved, but used for FP operations)
cr0 (not saved, but used for arithmetic operations)
- cr2, cr3, cr4 (saved)
+ cr4, cr3, cr2 (saved)
r0 (not saved; cannot be base reg)
r9 (not saved; best for TImode)
r11, r10, r8-r4 (not saved; highest used first to make less conflict)
@@ -732,7 +740,7 @@ extern int rs6000_debug_arg; /* debug argument handling */
33, \
63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
50, 49, 48, 47, 46, \
- 69, 74, 75, 68, 70, 71, 72, \
+ 75, 74, 69, 68, 72, 71, 70, \
0, \
9, 11, 10, 8, 7, 6, 5, 4, \
3, \