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| author | Bob Wilson <bob.wilson@acm.org> | 2003-05-20 23:39:09 +0000 |
|---|---|---|
| committer | Bob Wilson <bwilson@gcc.gnu.org> | 2003-05-20 23:39:09 +0000 |
| commit | 6c2e8d1cf9a162d34da692f0ee29489519ecb965 (patch) | |
| tree | 41b9cfbfb022947aee605600998237f181167ce8 /gcc/config/xtensa/xtensa.md | |
| parent | 69cf7a5532a0e6e9e3fd4e94bda72521706b10f3 (diff) | |
| download | gcc-6c2e8d1cf9a162d34da692f0ee29489519ecb965.zip gcc-6c2e8d1cf9a162d34da692f0ee29489519ecb965.tar.gz gcc-6c2e8d1cf9a162d34da692f0ee29489519ecb965.tar.bz2 | |
lib1funcs.asm: Avoid use of .Lfe* in .size directives.
* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
(do_abs, do_addx2, do_addx4, do_addx8): New assembler macros.
(__mulsi3): Use do_addx* instead of ADDX* instructions. Formatting.
(nsau): Rename to do_nsau. Provide alternate version for use when
the NSAU instruction is available.
(__udivsi3, __divsi3, __umodsi3, __modsi3): Use do_nsau macro.
(__divsi3, __modsi3): Use do_abs macro instead of ABS instruction.
* config/xtensa/xtensa-config.h: Update comments to match binutils.
(XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX): Define.
* config/xtensa/xtensa.h (MASK_ABS, MASK_ADDX): Define.
(TARGET_ABS, TARGET_ADDX): Define.
(TARGET_DEFAULT): Conditionally add MASK_ABS and MASK_ADDX.
(TARGET_SWITCHES): Add "abs", "no-abs", "addx", and "no-addx".
* config/xtensa/xtensa.md (*addx2, *addx4, *addx8, *subx2, *subx4,
*subx8): Set predicate condition to TARGET_ADDX.
(abssi2): Set predicate condition to TARGET_ABS.
* doc/invoke.texi (Option Summary): Document new "-mabs", "-mno-abs",
"-maddx", and "-mno-addx" options.
(Xtensa Options): Likewise. Also tag some opcode names with @code.
From-SVN: r67044
Diffstat (limited to 'gcc/config/xtensa/xtensa.md')
| -rw-r--r-- | gcc/config/xtensa/xtensa.md | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index aa5896e..626e4c7 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -163,7 +163,7 @@ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 2)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "addx2\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -174,7 +174,7 @@ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 4)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "addx4\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -185,7 +185,7 @@ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 8)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "addx8\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -257,7 +257,7 @@ (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 2)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "subx2\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -268,7 +268,7 @@ (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 4)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "subx4\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -279,7 +279,7 @@ (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 8)) (match_operand:SI 2 "register_operand" "r")))] - "" + "TARGET_ADDX" "subx8\\t%0, %1, %2" [(set_attr "type" "arith") (set_attr "mode" "SI") @@ -518,7 +518,7 @@ (define_insn "abssi2" [(set (match_operand:SI 0 "register_operand" "=a") (abs:SI (match_operand:SI 1 "register_operand" "r")))] - "" + "TARGET_ABS" "abs\\t%0, %1" [(set_attr "type" "arith") (set_attr "mode" "SI") |