[MIPS] Prevent MSA branches from being put into delay slots

 This patch tightens the instruction definitions to make sure
 that MSA branch instructions cannot be put into delay slots and have their
 delay slots eligible for being filled. Also, MSA *div*3 patterns use MSA
 branches for zero checks but are not marked as being multi instruction and
 thus could be put into delay slots. This patch fixes that.

gcc/ChangeLog:

2019-11-19  Zoran Jovanovic <zoran.jovanovic@mips.com>
		Dragan Mladjenovic  <dmladjenovic@wavecomp.com>

	* config/mips/mips-msa.md (msa_<msabr>_<msafmt_f>, msa_<msabr>_v_<msafmt_f>):
	Mark as not having "likely" version.
	* config/mips/mips.md (insn_count): The simd_div instruction with
	TARGET_CHECK_ZERO_DIV consists of 3 instructions.
	(can_delay): Exclude simd_branch.
	(defile_delay *): Add simd_branch instructions.
	They have one regular delay slot.

gcc/testsuite/ChangeLog:

2019-11-19  Dragan Mladjenovic  <dmladjenovic@wavecomp.com>

	* gcc.target/mips/msa-ds.c: New test.

From-SVN: r278458

0 files changed, 0 insertions, 0 deletions