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| author | Ian Lance Taylor <iant@golang.org> | 2021-10-27 08:47:25 -0700 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2021-10-27 08:47:25 -0700 |
| commit | a6d3012b274f38b20e2a57162106f625746af6c6 (patch) | |
| tree | 09ff8b13eb8ff7594c27dc8812efbf696dc97484 /gcc/config/sparc | |
| parent | cd2fd5facb5e1882d3f338ed456ae9536f7c0593 (diff) | |
| parent | 99b1021d21e5812ed01221d8fca8e8a32488a934 (diff) | |
| download | gcc-a6d3012b274f38b20e2a57162106f625746af6c6.zip gcc-a6d3012b274f38b20e2a57162106f625746af6c6.tar.gz gcc-a6d3012b274f38b20e2a57162106f625746af6c6.tar.bz2 | |
Merge from trunk revision 99b1021d21e5812ed01221d8fca8e8a32488a934.
Diffstat (limited to 'gcc/config/sparc')
| -rw-r--r-- | gcc/config/sparc/sparc-modes.def | 3 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.c | 12 |
2 files changed, 9 insertions, 6 deletions
diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def index 5cc4743..057c093 100644 --- a/gcc/config/sparc/sparc-modes.def +++ b/gcc/config/sparc/sparc-modes.def @@ -23,6 +23,9 @@ along with GCC; see the file COPYING3. If not see /* 128-bit floating point */ FLOAT_MODE (TF, 16, ieee_quad_format); +/* We need a 32-byte mode to return structures in the 64-bit ABI. */ +INT_MODE (OI, 32); + /* Add any extra modes needed to represent the condition code. We have a CCNZ mode which is used for implicit comparisons with zero when diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 6bc6f0a..ca91be4 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1859,7 +1859,7 @@ sparc_option_override (void) } /* Set the default CPU if no -mcpu option was specified. */ - if (!global_options_set.x_sparc_cpu_and_features) + if (!OPTION_SET_P (sparc_cpu_and_features)) { for (def = &cpu_default[0]; def->cpu != -1; ++def) if (def->cpu == TARGET_CPU_DEFAULT) @@ -1869,7 +1869,7 @@ sparc_option_override (void) } /* Set the default CPU if no -mtune option was specified. */ - if (!global_options_set.x_sparc_cpu) + if (!OPTION_SET_P (sparc_cpu)) sparc_cpu = sparc_cpu_and_features; cpu = &cpu_table[(int) sparc_cpu_and_features]; @@ -1975,7 +1975,7 @@ sparc_option_override (void) dump_target_flags ("Final target_flags", target_flags); /* Set the code model if no -mcmodel option was specified. */ - if (global_options_set.x_sparc_code_model) + if (OPTION_SET_P (sparc_code_model)) { if (TARGET_ARCH32) error ("%<-mcmodel=%> is not supported in 32-bit mode"); @@ -1989,7 +1989,7 @@ sparc_option_override (void) } /* Set the memory model if no -mmemory-model option was specified. */ - if (!global_options_set.x_sparc_memory_model) + if (!OPTION_SET_P (sparc_memory_model)) { /* Choose the memory model for the operating system. */ enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL; @@ -2177,12 +2177,12 @@ sparc_option_override (void) /* Disable save slot sharing for call-clobbered registers by default. The IRA sharing algorithm works on single registers only and this pessimizes for double floating-point registers. */ - if (!global_options_set.x_flag_ira_share_save_slots) + if (!OPTION_SET_P (flag_ira_share_save_slots)) flag_ira_share_save_slots = 0; /* Only enable REE by default in 64-bit mode where it helps to eliminate redundant 32-to-64-bit extensions. */ - if (!global_options_set.x_flag_ree && TARGET_ARCH32) + if (!OPTION_SET_P (flag_ree) && TARGET_ARCH32) flag_ree = 0; /* Do various machine dependent initializations. */ |