sparc.c (reg_or_0_operand, [...]): Delete.

	* config/sparc/sparc.c (reg_or_0_operand, const1_operand,
	fp_zero_operand, fp_register_operand, intreg_operand,
	fcc_reg_operand, fcc0_reg_operand, icc_or_fcc_reg_operand,
	call_operand, call_operand_address, tgd_symbolic_operand,
	tld_symbolic_operand, tie_symbolic_operand, tle_symbolic_operand,
	symbolic_operand, symbolic_memory_operand, label_ref_operand,
	sp64_medium_pic_operand, data_segment_operand,
	text_segment_operand, splittable_symbolic_memory_operand,
	reg_or_nonsymb_mem_operand, splittable_immediate_memory_operand,
	eq_or_neq, normal_comp_operator, noov_compare_op,
	noov_compare64_op, v9_regcmp_op, extend_op, cc_arithop,
	cc_arithopn, arith_operand, arith_4096_operand, arith_add_operand,
	const64_operand, const64_high_operand, arith11_operand,
	arith10_operand, arith_double_operand, arith_double_4096_operand,
	arith_double_add_operand, arith11_double_operand,
	arith10_double_operand, small_int, small_int_or_double,
	uns_small_int, uns_arith_operand, clobbered_register,
	input_operand, compare_operand): Delete.
	(sparc_emit_set_const32): Use predicates in assertion.  Remove special
	code for TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64.
	(sparc_emit_set_const64): Call gcc_unreachable if H_B_P_W_I == 32.
	(GEN_HIGHINT64, GEN_INT64): Delete.
	(sparc_emit_set_safe_HIGH64, gen_safe_SET64, gen_safe_OR64,
	gen_safe_XOR64): Adjust for above deletion.
	(sparc_emit_set_const64): Support only H_B_P_W_I == 64 and CONST_INTs.
	Use 'unsigned HOST_WIDE_INT' instead of 'long' for bitmask.
	(legitimate_constant_p): Use const_zero_operand instead.
	(sparc_extra_constraint_check): Likewise.
	* config/sparc/sparc.h (CONST_DOUBLE_OK_FOR_LETTER_P): Remove 'O'.
	(PREFERRED_RELOAD_CLASS): Use const_zero_operand.
	(PREDICATE_CODES): Delete.
	* config/sparc/sparc.md: Include predicates.md.
	(All patterns): Adjust for new predicate names.
	(cmpdi, cmpdi_sp64): Use arith_operand predicate.
	(movhi_const64_special, movsi_const64_special): Add 'K' constraint.
	(movdi): Use general_operand predicate.
	(movdi_sp64_dbl): Delete.
	(movdi_const64_special): Add 'N' constraint.
	(movdicc): Use arith10_operand predicate.
	(movdi_cc_sp64, movdi_cc_sp64_trunc): Use arith11_operand predicate.
	(movdi_cc_reg_sp64): Use arith10_operand predicate.
	(movdi_cc_reg_sp64_trunc): Delete.
	(cmp_zero_extract, cmp_zero_extract_sp64): Use small_int_operand.
	(adddi3_insn_sp32, addx, cmp_cc_plus, cmp_ccx_plus, cmp_cc_plus_set,
	cmp_ccx_plus_set): Use register_operand predicate.
	(adddi3_sp64, cmp_ccx_plus_set): Use arith_operand predicate.
	(subdi3_sp32): Delete.
	(subdi3_insn_sp32): Change to define_insn_and_split.
	(subdi3_sp64, cmp_minus_ccx, cmp_minus_ccx_set): Use arith_operand.
	(muldi3, muldi3_sp64, muldi3_v8plus): Likewise.
	(smulsi3_highpart_v8plus, const_smulsi3_highpart_v8plus,
	umulsi3_highpart_v8plus, const_umulsi3_highpart_v8plus): Use
	small_int_operand predicate.
	(divdi3, udivdi3): Use arith_operand predicate.
	(udivsi3, udivsi3_sp32, udivsi3_sp64): Use nonimmediate_operand.
	(and<V64I>3_sp64, ior<V64I>3_sp64, xor<V64I:mode>3_sp64,
	xor_not_<V64I:mode>_sp64) : Use arith_operand predicate.
	(xordi3_sp64_dbl): Delete.
	(cmp_ccx_arith_op, cmp_ccx_arith_op_set, cmp_ccx_xor_not,
	cmp_ccx_xor_not_set, cmp_ccx_arith_op_not, cmp_ccx_arith_op_not_set,
	cmp_ccx_neg, cmp_ccx_set_neg, one_cmpl<V64I>2_sp64, cmp_ccx_not,
	cmp_ccx_set_not): Use arith_operand predicate.
	(ashrsi3_extend2, lshrsi3_extend2 et al.): Use small_int_operand.
	* config/sparc/predicates.md: New file.

From-SVN: r98494

1 files changed, 22 insertions, 64 deletions

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 9e7ea08..7241691 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1189,8 +1189,8 @@ extern char leaf_reg_remap[];
     : (C) == 'c' ? FPCC_REGS			\
     : NO_REGS))
 
-/* The letters I, J, K, L and M in a register constraint string
-   can be used to stand for particular ranges of immediate operands.
+/* The letters I, J, K, L, M, N, O, P in a register constraint string
+   can be used to stand for particular ranges of CONST_INTs.
    This macro defines what the ranges are.
    C is the letter, and VALUE is a constant value.
    Return 1 if VALUE is in the range specified by C.
@@ -1201,20 +1201,32 @@ extern char leaf_reg_remap[];
    `L' is used for the range of constants supported by the movcc insns.
    `M' is used for the range of constants supported by the movrcc insns.
    `N' is like K, but for constants wider than 32 bits.
-   `O' is used for the range which is just 4096.  */
+   `O' is used for the range which is just 4096.
+   `P' is free.  */
 
+/* Predicates for 10-bit, 11-bit and 13-bit signed constants.  */
 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
-/* 10 and 11 bit immediates are only used for a few specific insns.
+
+/* 10- and 11-bit immediates are only used for a few specific insns.
    SMALL_INT is used throughout the port so we continue to use it.  */
 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
-/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
-					(INTVAL (X), SImode)))
+
+/* Predicate for constants that can be loaded with a sethi instruction.
+   This is the general, 64-bit aware, bitwise version that ensures that
+   only constants whose representation fits in the mask
+
+     0x00000000fffffc00
+
+   are accepted.  It will reject, for example, negative SImode constants
+   on 64-bit hosts, so correct handling is to mask the value beforehand
+   according to the mode of the instruction.  */
 #define SPARC_SETHI_P(X) \
   (((unsigned HOST_WIDE_INT) (X) \
     & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
+
+/* Version of the above predicate for SImode constants and below.  */
 #define SPARC_SETHI32_P(X) \
   (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
 
@@ -1228,13 +1240,12 @@ extern char leaf_reg_remap[];
    : (C) == 'O' ? (VALUE) == 4096			\
    : 0)
 
-/* Similar, but for floating constants, and defining letters G and H.
+/* Similar, but for CONST_DOUBLEs, and defining letters G and H.
    Here VALUE is the CONST_DOUBLE rtx itself.  */
 
 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)	\
-  ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE))	\
+  ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE))	\
    : (C) == 'H' ? arith_double_operand (VALUE, DImode)		\
-   : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode)	\
    : 0)
 
 /* Given an rtx X being reloaded into a reg required to be
@@ -1257,7 +1268,7 @@ extern char leaf_reg_remap[];
        || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT	\
 	   && ! TARGET_FPU)				\
        || (GET_MODE (X) == TFmode			\
-	   && ! fp_zero_operand (X, TFmode)))		\
+	   && ! const_zero_operand (X, TFmode)))	\
       ? NO_REGS						\
       : (!FP_REG_CLASS_P (CLASS)			\
          && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)	\
@@ -2449,58 +2460,5 @@ extern int sparc_indent_opcode;
 #define TARGET_SUN_TLS TARGET_TLS
 #define TARGET_GNU_TLS 0
 
-/* Define the codes that are matched by predicates in sparc.c.  */
-
-#define PREDICATE_CODES							\
-{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},		\
-{"const1_operand", {CONST_INT}},					\
-{"fp_zero_operand", {CONST_DOUBLE}},					\
-{"fp_register_operand", {SUBREG, REG}},					\
-{"intreg_operand", {SUBREG, REG}},					\
-{"fcc_reg_operand", {REG}},						\
-{"fcc0_reg_operand", {REG}},						\
-{"icc_or_fcc_reg_operand", {REG}},					\
-{"call_operand", {MEM}},						\
-{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE,	\
-	SUBREG, REG, PLUS, LO_SUM, CONST_INT}},				\
-{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},			\
-{"symbolic_memory_operand", {SUBREG, MEM}},				\
-{"label_ref_operand", {LABEL_REF}},					\
-{"sp64_medium_pic_operand", {CONST}},					\
-{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},			\
-{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},		\
-{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},			\
-{"splittable_symbolic_memory_operand", {MEM}},				\
-{"splittable_immediate_memory_operand", {MEM}},				\
-{"eq_or_neq", {EQ, NE}},						\
-{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},			\
-{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
-{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
-{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},				\
-{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},				\
-{"cc_arithop", {AND, IOR, XOR}},					\
-{"cc_arithopn", {AND, IOR}},						\
-{"arith_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith_add_operand", {SUBREG, REG, CONST_INT}},			\
-{"arith11_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith10_operand", {SUBREG, REG, CONST_INT}},				\
-{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
-{"small_int", {CONST_INT}},						\
-{"small_int_or_double", {CONST_INT, CONST_DOUBLE}},			\
-{"uns_small_int", {CONST_INT}},						\
-{"uns_arith_operand", {SUBREG, REG, CONST_INT}},			\
-{"clobbered_register", {REG}},						\
-{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
-{"compare_operand", {SUBREG, REG, ZERO_EXTRACT}},			\
-{"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
-{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},			\
-{"tgd_symbolic_operand", {SYMBOL_REF}},					\
-{"tld_symbolic_operand", {SYMBOL_REF}},					\
-{"tie_symbolic_operand", {SYMBOL_REF}},					\
-{"tle_symbolic_operand", {SYMBOL_REF}},
-
 /* The number of Pmode words for the setjmp buffer.  */
 #define JMP_BUF_SIZE 12