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| author | David S. Miller <davem@davemloft.net> | 2007-10-19 04:29:38 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2007-10-18 21:29:38 -0700 |
| commit | 9eeaed6ec41bb97d84e38fc81339e36b0598a442 (patch) | |
| tree | a29ad799a69b10144515b4f308ac4ae353fabdf7 /gcc/config/sparc/sol2.h | |
| parent | f41899f6cadaee6ab5b8a82cfad27ddf1d7c9a44 (diff) | |
| download | gcc-9eeaed6ec41bb97d84e38fc81339e36b0598a442.zip gcc-9eeaed6ec41bb97d84e38fc81339e36b0598a442.tar.gz gcc-9eeaed6ec41bb97d84e38fc81339e36b0598a442.tar.bz2 | |
Add Niagara-2 support.
2007-10-18 David S. Miller <davem@davemloft.net>
Add Niagara-2 support.
* doc/invoke.texi: Document -m{cpu,tune}=niagara2.
* config.gcc: Add niagara2 to cpu and tune lists for sparc.
* config/sparc/sparc.md (sparc_cpu_attr): Add niagara2.
(include): Add inclusion of niagara2.md
* config/sparc/sparc.c (niagara2_costs): New.
(sparc_override_options): Add niagara2 entry to cpu_default[]
and cpu_table[]. Set align_functions to 32 on Niagara2. Use
niagara2_costs when PROCESSOR_NIAGARA2. Handle Niagara2 for
PARAM_SIMULTANEOUS_PREFETCHES and PARAM_L1_CACHE_LINE_SIZE.
(sparc_initialize_trampoline): Handle niagara2 like niagara.
(sparc64_initialize_trampoline): Likewise.
(sparc_use_sched_lookahead): Likewise.
(sparc_issue_rate): Likewise.
* config/sparc/sol2-bi.h: Handle TARGET_CPU_niagara2 and
mcpu=niagara2
* config/sparc/sparc.h (TARGET_CPU_niagara2): Define.
({CPP,ASM}_CPU64_DEFAULT_SPEC): Set appropriately for
TARGET_CPU_niagara2.
(PROCESSOR_NIAGARA2): New.
(REGISTER_MOVE_COST): Handle PROCESSOR_NIAGARA2.
(BRANCH_COST): Likewise.
* config/sparc/linux64.h: Handle TARGET_CPU_niagara2.
* config/sparc/sol2.h: Likewise.
* config/sparc/niagara2.md: New file.
From-SVN: r129472
Diffstat (limited to 'gcc/config/sparc/sol2.h')
| -rw-r--r-- | gcc/config/sparc/sol2.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 43ab324..1890ce9 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -45,12 +45,18 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb" +#endif + #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "\ %{mcpu=v9:-xarch=v8plus} \ %{mcpu=ultrasparc:-xarch=v8plusa} \ %{mcpu=ultrasparc3:-xarch=v8plusb} \ %{mcpu=niagara:-xarch=v8plusb} \ +%{mcpu=niagara2:-xarch=v8plusb} \ %{!mcpu*:%(asm_cpu_default)} \ " |