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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2016-04-03 12:50:54 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2016-04-03 12:50:54 +0000 |
| commit | 6cc6ed50e2510031f5f3aa4fc066c67d046d3f0d (patch) | |
| tree | 0f5bfb80150be0b576ac3d522b85309d4797ece2 /gcc/config/sh | |
| parent | 34d40e88a9c177dff4c6c30a642fd80efd0209b4 (diff) | |
| download | gcc-6cc6ed50e2510031f5f3aa4fc066c67d046d3f0d.zip gcc-6cc6ed50e2510031f5f3aa4fc066c67d046d3f0d.tar.gz gcc-6cc6ed50e2510031f5f3aa4fc066c67d046d3f0d.tar.bz2 | |
re PR target/70416 ([SH]: error: 'asm' operand requires impossible reload when building ruby2.3)
gcc/
PR target/70416
PR target/67391
* config/sh/sh.md (*addsi3): Allow pattern when reload_in_progress is
set, but not for SP_REG operands.
gcc/testsuite/
PR target/70416
PR target/67391
* gcc.target/sh/torture/pr70416.c: New.
From-SVN: r234702
Diffstat (limited to 'gcc/config/sh')
| -rw-r--r-- | gcc/config/sh/sh.md | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index c0a9249c..0bb0f2b 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2242,14 +2242,23 @@ [(set_attr "type" "arith")]) ;; Old reload might generate add insns directly (not through the expander) for -;; the memory address of complex insns like atomic insns when reloading. +;; address register calculations when reloading, in which case it won't try +;; the addsi_scr pattern. Because reload will sometimes try to validate +;; the generated insns and their constraints, this pattern must be +;; recognizable during and after reload. However, when reload generates +;; address register calculations for the stack pointer, we don't allow this +;; pattern. This will make reload prefer using indexed @(reg + reg) address +;; modes when the displacement of a @(disp + reg) doesn't fit. (define_insn_and_split "*addsi3" [(set (match_operand:SI 0 "arith_reg_dest" "=r") (plus:SI (match_operand:SI 1 "arith_reg_operand" "r") (match_operand:SI 2 "arith_or_int_operand" "rn")))] "TARGET_SH1 && !sh_lra_p () - && reload_completed - && !reg_overlap_mentioned_p (operands[0], operands[1])" + && (reload_completed || reload_in_progress) + && !reg_overlap_mentioned_p (operands[0], operands[1]) + && (!reload_in_progress + || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG) + && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))" "#" "&& 1" [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] |