config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.

	* config.gcc (sh*-*-*): Define SUPPORT_* macros to 1.
	* config/sh/sh.h: Update mask names throughout.
	(target_flags, ISIZE_BIT, DALIGN_BIT, SH1_BIT, SH2_BIT, SH3_BIT)
	(SH_E_BIT, HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, SH4A_BIT, FMOVD_BIT)
	(SH5_BIT, SPACE_BIT, BIGTABLE_BIT, RELAX_BIT, USERMODE_BIT)
	(HITACHI_BIT, NOMACSAVE_BIT, PREFERGOT_BIT, PADSTRUCT_BIT)
	(LITTLE_ENDIAN_BIT, IEEE_BIT, SAVE_ALL_TR_BIT, HARD_SH2A_BIT)
	(HARD_SH2A_DOUBLE_BIT, INDEXED_ADDRESS_BIT, PT_FIXED_BIT)
	(INVALID_SYMBOLS_BIT, ADJUST_UNROLL_BIT, TARGET_DUMPISIZE)
	(TARGET_ALIGN_DOUBLE, TARGET_SH1, TARGET_SH2, TARGET_SH3)
	(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH5, TARGET_FMOVD)
	(TARGET_IEEE, TARGET_SMALLCODE, TARGET_BIGTABLE, TARGET_RELAX)
	(TARGET_HITACHI, TARGET_NOMACSAVE, TARGET_PADSTRUCT)
	(TARGET_LITTLE_ENDIAN, TARGET_USERMODE, TARGET_PREFERGOT)
	(TARGET_SAVE_ALL_TARGET_REGS, TARGET_ALLOW_INDEXED_ADDRESS)
	(TARGET_PT_FIXED, TARGET_INVALID_SYMBOLS, TARGET_ADJUST_UNROLL)
	(TARGET_SWITCH_SH1, TARGET_SWITCH_SH2, TARGET_SWITCH_SH2E)
	(TARGET_SWITCH_SH2A, TARGET_SWITCH_SH2A_SINGLE_ONLY)
	(TARGET_SWITCH_SH2A_SINGLE, TARGET_SWITCH_SH2A_NOFPU)
	(TARGET_SWITCH_SH3, TARGET_SWITCH_SH3E, TARGET_SWITCH_SH4_SINGLE_ONLY)
	(TARGET_SWITCH_SH4_SINGLE, TARGET_SWITCH_SH4_NOFPU, TARGET_SWITCH_SH4)
	(TARGET_SWITCH_SH4A, TARGET_SWITCH_SH4A_SINGLE_ONLY)
	(TARGET_SWITCH_SH4A_SINGLE, TARGET_SWITCH_SH4A_NOFPU)
	(TARGET_SWITCH_SH4AL, TARGET_SWITCH_SH5_64MEDIA)
	(TARGET_SWITCH_SH5_64MEDIA_NOFPU, TARGET_SWITCHES_SH5_32MEDIA)
	(TARGET_SWITCHES_SH5_32MEDIA_NOFPU, TARGET_SWITCH_SH5_32_ANY_EXTRA)
	(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA, TARGET_SWITCHES)
	(SUBTARGET_SWITCHES): Delete.
	(TARGET_SH2E, TARGET_SH2A, TARGET_SH2A_SINGLE, TARGET_SH2A_DOUBLE)
	(TARGET_SH3E, TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARVARD)
	(TARGET_FPU_DOUBLE, TARGET_SH4A_ARCH, TARGET_SHMEDIA32)
	(TARGET_SHMEDIA64): Redefine using other TARGET_* macros.
	(TARGET_SH4): Undefine options.h definition and check MASK_SH1 as well.
	(SUPPORT_SH1, SUPPORT_SH2E, SUPPORT_SH4, SUPPORT_SH4_SINGLE)
	(SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Make numeric.
	(SUPPORT_SH2): Define to 1 if SUPPORT_SH1.
	(SUPPORT_SH3): Likewise SUPPORT_SH2.
	(SUPPORT_SH4_NOFPU): Likewise SUPPORT_SH3.
	(SUPPORT_SH4A_NOFPU, SUPPORT_SH4AL, SUPPORT_SH2A_NOFPU): Likewise
	SUPPORT_SH4_NOFPU.
	(SUPPORT_SH3E): Likewise SUPPORT_SH2E.
	(SUPPORT_SH4_SINGLE_ONLY, SUPPORT_SH4A_SINGLE_ONLY)
	(SUPPORT_SH2A_SINGLE_ONLY): Likewise SUPPORT_SH3E.
	(SUPPORT_SH4A): Likewise SUPPORT_SH4.
	(SUPPORT_SH4A_SINGLE): Likewise SUPPORT_SH4_SINGLE.
	(SUPPORT_SH5_32MEDIA): Likewise SUPPORT_SH5_COMPACT.
	(SUPPORT_SH5_32MEDIA_NOFPU): Likewise SUPPORT_SH5_COMPACT_NOFPU.
	(SUPPORT_ANY_SH5_32MEDIA, SUPPORT_ANY_SH5_64MEDIA)
	(SUPPORT_ANY_SH5): New macros.
	(TARGET_NONE): Replace with...
	(MASK_ARCH): ...this new macro.
	* config/sh/elf.h: Update mask names
	* config/sh/linux.h: Likewise.
	* config/sh/little.h: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/symbian-pre.h: Likewise.
	* config/sh/sh.c (sh_handle_option): New function.
	(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
	(calc_live_regs): Use MASK_FPU_SINGLE instead of FPU_SINGLE_BIT.
	(sh_target_switches, target_switches): Delete.
	(sh_pch_valid_p): Check for specific differences in the target_flags
	settings.
	(sh_init_cumulative_args): Use MASK_HITACHI instead of HITACHI_BIT.
	* config/sh/sh.opt: New file.

From-SVN: r99916

1 files changed, 214 insertions, 0 deletions

diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
new file mode 100644
index 0000000..c3c659f
--- /dev/null
+++ b/gcc/config/sh/sh.opt
@@ -0,0 +1,214 @@
+; Options for the SH port of the compiler.
+
+; Copyright (C) 2005 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING.  If not, write to the Free
+; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+; 02111-1307, USA.
+
+;; Used for various architecture options.
+Mask(SH_E)
+
+;; Set if the default precision of th FPU is single.
+Mask(FPU_SINGLE)
+
+;; Set if we should generate code using type 2A insns.
+Mask(HARD_SH2A)
+
+;; Set if we should generate code using type 2A DF insns.
+Mask(HARD_SH2A_DOUBLE)
+
+;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
+Mask(HARD_SH4)
+
+;; Set if we should generate code for a SH5 CPU (either ISA).
+Mask(SH5)
+
+;; Set if we should save all target registers.
+Mask(SAVE_ALL_TARGET_REGS)
+
+m1
+Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
+Generate SH1 code
+
+m2
+Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
+Generate SH2 code
+
+m2a
+Target RejectNegative Condition(SUPPORT_SH2A)
+Generate SH2a code
+
+m2a-nofpu
+Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
+Generate SH2a FPU-less code
+
+m2a-single
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE)
+Generate default single-precision SH2a code
+
+m2a-single-only
+Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY)
+Generate only single-precision SH2a code
+
+m2e
+Target RejectNegative Condition(SUPPORT_SH2E)
+Generate SH2e code
+
+m3
+Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
+Generate SH3 code
+
+m3e
+Target RejectNegative Condition(SUPPORT_SH3E)
+Generate SH3e code
+
+m4
+Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
+Generate SH4 code
+
+m4-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
+Generate SH4 FPU-less code
+
+m4-single
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
+Generate default single-precision SH4 code
+
+m4-single-only
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
+Generate only single-precision SH4 code
+
+m4a
+Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
+Generate SH4a code
+
+m4a-nofpu
+Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
+Generate SH4a FPU-less code
+
+m4a-single
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
+Generate default single-precision SH4a code
+
+m4a-single-only
+Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
+Generate only single-precision SH4a code
+
+m4al
+Target RejectNegative Condition(SUPPORT_SH4AL)
+Generate SH4al-dsp code
+
+m5-32media
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate 32-bit SHmedia code
+
+m5-32media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate 32-bit FPU-less SHmedia code
+
+m5-64media
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
+Generate 64-bit SHmedia code
+
+m5-64media-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
+Generate 64-bit FPU-less SHmedia code
+
+m5-compact
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
+Generate SHcompact code
+
+m5-compact-nofpu
+Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
+Generate FPU-less SHcompact code
+
+madjust-unroll
+Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
+Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
+
+mb
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Generate code in big endian mode
+
+mbigtable
+Target Report RejectNegative Mask(BIGTABLE)
+Generate 32-bit offsets in switch tables
+
+mdalign
+Target Report RejectNegative Mask(ALIGN_DOUBLE)
+Align doubles at 64-bit boundaries
+
+mfmovd
+Target RejectNegative Mask(FMOVD) Undocumented
+
+mhitachi
+Target Report RejectNegative Mask(HITACHI)
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mieee
+Target Report Mask(IEEE)
+Increase the IEEE compliance for floating-point code
+
+mindexed-addressing
+Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
+Enable the use of the indexed addressing mode for SHmedia32/SHcompact
+
+minvalid-symbols
+Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
+Assume symbols might be invalid
+
+misize
+Target Report RejectNegative Mask(DUMPISIZE)
+Annotate assembler instructions with estimated addresses
+
+ml
+Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Generate code in little endian mode
+
+mnomacsave
+Target Report RejectNegative Mask(NOMACSAVE)
+Mark MAC register as call-clobbered
+
+;; ??? This option is not useful, but is retained in case there are people
+;; who are still relying on it.  It may be deleted in the future.
+mpadstruct
+Target Report RejectNegative Mask(PADSTRUCT)
+Make structs a multiple of 4 bytes (warning: ABI altered)
+
+mprefergot
+Target Report RejectNegative Mask(PREFERGOT)
+Emit function-calls using global offset table when generating PIC
+
+mpt-fixed
+Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
+Assume pt* instructions won't trap
+
+mrelax
+Target Report RejectNegative Mask(RELAX)
+Shorten address references during linking
+
+mrenesas
+Target Mask(HITACHI) MaskExists
+Follow Renesas (formerly Hitachi) / SuperH calling conventions
+
+mspace
+Target Report RejectNegative Mask(SMALLCODE)
+Deprecated. Use -Os instead
+
+musermode
+Target Report RejectNegative Mask(USERMODE)
+Generate library function call to invalidate instruction cache entries after fixing trampoline