crt1.asm: Fix #ifdef indent.

gcc:

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>

	* config/sh/crt1.asm: Fix #ifdef indent.

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>
	Merged from STMicroelectronics sources:
	2006-10-06  Andrew Stubbs  <andrew.stubbs@st.com>
	  * config/sh/crt1.asm (vbr_600): Add missing #if.
	2006-08-03  J"orn Rennecke  <joern.rennecke@st.com>
	  * sh.opt (mfused-madd): New option.
	  * sh.md (mac_media, macsf3): Make conditional on TARGET_FMAC.
	2006-07-04  Andrew Stubbs  <andrew.stubbs@st.com>
	  * config/sh/crt1.asm (vbr_start): Move to new section .test.vbr.
	  Remove pointless handler at VBR+0.
	  (vbr_200, vbr_300, vbr_500): Remove pointless handler.
	  (vbr_600): Save and restore mach and macl, fpul and fpscr and fr0 to
	  fr7. Make sure the timer handler is called with the correct FPU
	  precision setting, according to the ABI.
	2006-06-14  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/sh.opt (m2a-single, m2a-single-only): Fix Condition.
	  * config/sh/sh.h (SUPPORT_SH2A_NOFPU): Fix condition.
	  (SUPPORT_SH2A_SINGLE_ONLY, SUPPORT_SH2A_SINGLE_ONLY): Likewise.
	2006-06-09  J"orn Rennecke <joern.rennecke@st.com>
	  * sh.md (cmpgeusi_t): Change into define_insn_and_split.  Accept
	  zero as second operand.
	2006-04-28  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
	  Fixed some bugs related to negative values, in particular -0
	  and overflow at -0x80000000.
	  * config/sh/divcost-analysis: Added sh4-300 figures.
	2006-04-27  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/t-sh (MULTILIB_MATCHES): Add -m4-300* / -m4-340 options.
	2006-04-26  J"orn Rennecke <joern.rennecke@st.com>
	  * config/sh/t-sh (OPT_EXTRA_PARTS): Add libgcc-4-300.a.
	  ($(T)div_table-4-300.o, $(T)libgcc-4-300.a): New rules.
	  * config/sh/divtab-sh4-300.c, config/sh/lib1funcs-4-300.asm:
	New files.
	  * config/sh/embed-elf.h (LIBGCC_SPEC): Use -lgcc-4-300 for -m4-300* /
	  -m4-340.
	2006-04-24  J"orn Rennecke <joern.rennecke@st.com>
	  SH4-300 scheduling description & fixes to SH4-[12]00 description:
	  * sh.md: New instruction types: fstore, movi8, fpscr_toggle, gp_mac,
	  mac_mem, mem_mac, dfp_mul, fp_cmp.
	  (insn_class, dfp_comp, any_fp_comp): Update.
	  (push_fpul, movsf_ie, fpu_switch, toggle_sz, toggle_pr): Update type.
	  (cmpgtsf_t, "cmpeqsf_t, cmpgtsf_t_i4, cmpeqsf_t_i4): Likewise.
	  (muldf3_i): Likewise.
	  (movsi_i): Split rI08 alternative into two separate alternatives.
	  Update type.
	  (movsi_ie, movsi_i_lowpart): Likewise.
	  (movqi_i): Split ri alternative into two separate alternatives.
	  Update type.
	  * sh1.md (sh1_load_store, sh1_fp): Update.
	  * sh4.md (sh4_store, sh4_mac_gp, fp_arith, fp_double_arith): Update.
	  (mac_mem, sh4_fpscr_toggle): New insn_reservations.
	  * sh4a.md (sh4a_mov, sh4a_load, sh4a_store, sh4a_fp_arith): Update.
	  (sh4a_fp_double_arith): Likewise.
	  * sh4-300.md: New file.
	  * sh.c (sh_handle_option): Handle m4-300* options.
	  (sh_adjust_cost): Fix latency of auto-increments.
	  Handle SH4-300 differently than other SH4s.  Check for new insn types.
	  * sh.h (OVERRIDE_OPTIONS): Initilize sh_branch_cost if it has not
	  been set by an option.
	  * sh.opt (m4-300, m4-100-nofpu, m4-200-nofpu): New options.
	  (m4-300-nofpu, -m4-340, m4-300-single, m4-300-single-only): Likewise.
	  (mbranch-cost=): Likewise.
	  * superh.h (STARTFILE_SPEC): Take -m4-340 into account.

	  * sh.md (mulsf3): Remove special expansion code.
	  (mulsf3_ie): Now a define_insn_and_split.
	  (macsf3): Allow for TARGET_SH4.

	  * sh.md (cbranchsi4, cbranchdi4, cbranchdi4_i): New patterns.
	  * sh.c (prepare_cbranch_operands, expand_cbranchsi4): New functions.
	  (expand_cbranchdi4): Likewise.
	  (sh_rtx_costs): Give lower cost for certain CONST_INT values and for
	  CONST_DOUBLE if the outer code is COMPARE.
	  * sh.h (OPTIMIZATION_OPTIONS): If not optimizing for size, set
	  TARGET_CBRANCHDI4 and TARGET_EXPAND_CBRANCHDI4.
	  (OVERRIDE_OPTIONS): For TARGET_SHMEDIA, clear TARGET_CBRANCHDI4.
	  (LEGITIMATE_CONSTANT_P): Also allow DImode and VOIDmode CONST_DOUBLEs.
	  Remove redundant fp_{zero,one}_operand checks.
	  * sh.opt (mcbranchdi, mexpand-cbranchdi, mcmpeqdi): New options.
	  * sh-protos.h (prepare_cbranch_operands, expand_cbranchsi4): Declare.
	  (expand_cbranchdi4): Likewise.
	2006-04-20  J"orn Rennecke <joern.rennecke@st.com>
	  * sh.h (LOCAL_ALIGNMENT): Use DATA_ALIGNMENT.

gcc/testsuite:

2006-11-03  J"orn Rennecke  <joern.rennecke@st.com>

	* testsuite/gcc.c-torture/execute/arith-rand-ll.c:
	Also test for bogus rest sign.

From-SVN: r118458

1 files changed, 54 insertions, 3 deletions

diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index 7f9a87e..161fdd8 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -57,11 +57,11 @@ Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
 Generate SH2a FPU-less code
 
 m2a-single
-Target RejectNegative Condition (SUPPORT_SH2A_SINGLE)
+Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
 Generate default single-precision SH2a code
 
 m2a-single-only
-Target RejectNegative Condition (SUPPORT_SH2A_SINGLE_ONLY)
+Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
 Generate only single-precision SH2a code
 
 m2e
@@ -88,10 +88,33 @@ m4-200
 Target RejectNegative Condition(SUPPORT_SH4)
 Generate SH4-200 code
 
+;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
+;; pipeline - irrespective of ABI.
+m4-300
+Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
+Generate SH4-300 code
+
 m4-nofpu
 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
 Generate SH4 FPU-less code
 
+m4-100-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
+Generate SH4-100 FPU-less code
+
+m4-200-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
+Generate SH4-200 FPU-less code
+
+m4-300-nofpu
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
+Generate SH4-300 FPU-less code
+
+m4-340
+Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
+Generate code for SH4 340 series (MMU/FPU-less)
+;; passes -isa=sh4-nommu-nofpu to the assembler.
+
 m4-400
 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
 Generate code for SH4 400 series (MMU/FPU-less)
@@ -114,6 +137,10 @@ m4-200-single
 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
 Generate default single-precision SH4-200 code
 
+m4-300-single
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
+Generate default single-precision SH4-300 code
+
 m4-single-only
 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
 Generate only single-precision SH4 code
@@ -126,6 +153,10 @@ m4-200-single-only
 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
 Generate only single-precision SH4-200 code
 
+m4-300-single-only
+Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
+Generate only single-precision SH4-300 code
+
 m4a
 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
 Generate SH4a code
@@ -182,6 +213,22 @@ mbigtable
 Target Report RejectNegative Mask(BIGTABLE)
 Generate 32-bit offsets in switch tables
 
+mbranch-cost=
+Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
+Cost to assume for a branch insn
+
+mcbranchdi
+Target Var(TARGET_CBRANCHDI4)
+Enable cbranchdi4 pattern
+
+mexpand-cbranchdi
+Target Var(TARGET_EXPAND_CBRANCHDI4)
+Expand cbranchdi4 pattern early into separate comparisons and branches.
+
+mcmpeqdi
+Target Var(TARGET_CMPEQDI_T)
+Emit cmpeqdi_t pattern even when -mcbranchdi and -mexpand-cbranchdi are in effect.
+
 mcut2-workaround
 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
 Enable SH5 cut2 workaround
@@ -192,7 +239,7 @@ Align doubles at 64-bit boundaries
 
 mdiv=
 Target RejectNegative Joined Var(sh_div_str) Init("")
-Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp call-div1 call-fp call-table
+Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
 
 mdivsi3_libfunc=
 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
@@ -201,6 +248,10 @@ Specify name for 32 bit signed division function
 mfmovd
 Target RejectNegative Mask(FMOVD) Undocumented
 
+mfused-madd
+Target Var(TARGET_FMAC)
+Enable the use of the fused floating point multiply-accumulate operation
+
 mgettrcost=
 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
 Cost to assume for gettr insn