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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2016-05-04 07:14:11 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2016-05-04 07:14:11 +0000 |
| commit | da5b1ec120cd4f8e68ff9f83f52a93f3a15bfb74 (patch) | |
| tree | b83fc185cc0166a1c0a9e4730902267830baed4e /gcc/config/sh/sh.md | |
| parent | e07ab2feaf8f83bfab64ef0746b4fb8ee65033d3 (diff) | |
| download | gcc-da5b1ec120cd4f8e68ff9f83f52a93f3a15bfb74.zip gcc-da5b1ec120cd4f8e68ff9f83f52a93f3a15bfb74.tar.gz gcc-da5b1ec120cd4f8e68ff9f83f52a93f3a15bfb74.tar.bz2 | |
predicates (post_inc_mem, [...]): New predicates.
gcc/
* config/sh/predicates (post_inc_mem, pre_dec_mem): New predicates.
* config/sh/sh-protos.h (sh_find_set_of_reg): Return null result if
result.set_rtx is null instead of aborting.
* config/sh/sh.h (USE_LOAD_POST_INCREMENT, USE_STORE_PRE_DECREMENT):
Always enable.
(USE_LOAD_PRE_DECREMENT, USE_STORE_POST_INCREMENT): Enable for SH2A.
* config/sh/sh.md (*extend<mode>si2_predec, *mov<mode>_load_predec,
*mov<mode>_store_postinc): New patterns.
From-SVN: r235859
Diffstat (limited to 'gcc/config/sh/sh.md')
| -rw-r--r-- | gcc/config/sh/sh.md | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 2d9502b..2a8fbc8 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -4820,6 +4820,15 @@ [(set_attr "type" "load") (set_attr "length" "2,2,4")]) +;; The pre-dec and post-inc mems must be captured by the '<' and '>' +;; constraints, otherwise wrong code might get generated. +(define_insn "*extend<mode>si2_predec" + [(set (match_operand:SI 0 "arith_reg_dest" "=z") + (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))] + "TARGET_SH2A" + "mov.<bw> %1,%0" + [(set_attr "type" "load")]) + ;; The *_snd patterns will take care of other QImode/HImode addressing ;; modes than displacement addressing. They must be defined _after_ the ;; displacement addressing patterns. Otherwise the displacement addressing @@ -5261,6 +5270,22 @@ prepare_move_operands (operands, <MODE>mode); }) +;; The pre-dec and post-inc mems must be captured by the '<' and '>' +;; constraints, otherwise wrong code might get generated. +(define_insn "*mov<mode>_load_predec" + [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z") + (match_operand:QIHISI 1 "pre_dec_mem" "<"))] + "TARGET_SH2A" + "mov.<bwl> %1,%0" + [(set_attr "type" "load")]) + +(define_insn "*mov<mode>_store_postinc" + [(set (match_operand:QIHISI 0 "post_inc_mem" "=>") + (match_operand:QIHISI 1 "arith_reg_operand" "z"))] + "TARGET_SH2A" + "mov.<bwl> %1,%0" + [(set_attr "type" "store")]) + ;; Specifying the displacement addressing load / store patterns separately ;; before the generic movqi / movhi pattern allows controlling the order ;; in which load / store insns are selected in a more fine grained way. |