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authorOleg Endo <olegendo@gcc.gnu.org>2016-06-04 06:08:33 +0000
committerOleg Endo <olegendo@gcc.gnu.org>2016-06-04 06:08:33 +0000
commitc389d3496ad217dbce58cc90c7cc7c7d31b40d81 (patch)
tree74a8b350552d28cacb1da3da852e03ab9a1d07f1 /gcc/config/sh/sh.c
parent4624e9cd754a68b8dbd7fe7d75ef4882626649c6 (diff)
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Avoid potential slient wrong-code with reg+reg addr. modes on SH.
gcc/ * config/sh/sh.c (sh_print_operand_address): Don't use hardcoded 'r0' for reg+reg addressing mode. From-SVN: r237088
Diffstat (limited to 'gcc/config/sh/sh.c')
-rw-r--r--gcc/config/sh/sh.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 2bd917a..74327aa 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1038,8 +1038,16 @@ sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
int base_num = true_regnum (base);
int index_num = true_regnum (index);
- fprintf (stream, "@(r0,%s)",
- reg_names[MAX (base_num, index_num)]);
+ /* If base or index is R0, make sure that it comes first.
+ Usually one of them will be R0, but the order might be wrong.
+ If neither base nor index are R0 it's an error and we just
+ pass it on to the assembler. This avoids silent wrong code
+ bugs. */
+ if (base_num == 0 && index_num != 0)
+ std::swap (base_num, index_num);
+
+ fprintf (stream, "@(%s,%s)", reg_names[index_num],
+ reg_names[base_num]);
break;
}