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authorVladimir Makarov <vmakarov@redhat.com>2011-03-28 01:53:24 +0000
committerVladimir Makarov <vmakarov@gcc.gnu.org>2011-03-28 01:53:24 +0000
commit99710245becabdfa97984d1f68a01f9876124417 (patch)
tree761665b37aeeeb5eb4e3f9b4770772ea49679cc0 /gcc/config/score
parent0854e22029b6d45bc67140bf5d5493ee5c9294ef (diff)
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re PR bootstrap/48307 (Bootstrap failure)
2011-03-27 Vladimir Makarov <vmakarov@redhat.com> PR bootstrap/48307 Revert the previous patch. From-SVN: r171589
Diffstat (limited to 'gcc/config/score')
-rw-r--r--gcc/config/score/score.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h
index c66e0e9..4554e26 100644
--- a/gcc/config/score/score.h
+++ b/gcc/config/score/score.h
@@ -390,6 +390,18 @@ enum reg_class
also contains the register. */
#define REGNO_REG_CLASS(REGNO) (enum reg_class) score_reg_class (REGNO)
+/* The following macro defines cover classes for Integrated Register
+ Allocator. Cover classes is a set of non-intersected register
+ classes covering all hard registers used for register allocation
+ purpose. Any move between two registers of a cover class should be
+ cheaper than load or store of the registers. The macro value is
+ array of register classes with LIM_REG_CLASSES used as the end
+ marker. */
+#define IRA_COVER_CLASSES \
+{ \
+ G32_REGS, CE_REGS, SP_REGS, LIM_REG_CLASSES \
+}
+
/* A macro whose definition is the name of the class to which a
valid base register must belong. A base register is one used in
an address which is the register value plus a displacement. */