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| author | Jerry DeLisle <jvdelisle@gcc.gnu.org> | 2025-09-02 15:58:26 -0700 |
|---|---|---|
| committer | Jerry DeLisle <jvdelisle@gcc.gnu.org> | 2025-09-02 15:58:26 -0700 |
| commit | 071b4126c613881f4cb25b4e5c39032964827f88 (patch) | |
| tree | 7ed805786566918630d1d617b1ed8f7310f5fd8e /gcc/config/s390/vector.md | |
| parent | 845d23f3ea08ba873197c275a8857eee7edad996 (diff) | |
| parent | caa1c2f42691d68af4d894a5c3e700ecd2dba080 (diff) | |
| download | gcc-devel/gfortran-test.zip gcc-devel/gfortran-test.tar.gz gcc-devel/gfortran-test.tar.bz2 | |
Merge branch 'master' into gfortran-testdevel/gfortran-test
Diffstat (limited to 'gcc/config/s390/vector.md')
| -rw-r--r-- | gcc/config/s390/vector.md | 84 |
1 files changed, 36 insertions, 48 deletions
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 12bbeb6..745634e 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -501,54 +501,6 @@ SIL,SIL,RI,RI,RRE,RRE,RIL,RR,RXY,RXY,RIL")]) -; Instructions vlgvb, vlgvh, vlgvf zero all remaining bits of a GPR, i.e., -; an implicit zero extend is done. - -(define_insn "*movdi<mode>_zero_extend_A" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (match_operand:SINT 1 "register_operand" "v")))] - "TARGET_VX" - "vlgv<bhfgq>\t%0,%v1,0" - [(set_attr "op_type" "VRS")]) - -(define_insn "*movsi<mode>_zero_extend_A" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (match_operand:HQI 1 "register_operand" "v")))] - "TARGET_VX" - "vlgv<bhfgq>\t%0,%v1,0" - [(set_attr "op_type" "VRS")]) - -(define_mode_iterator VLGV_DI [V1QI V2QI V4QI V8QI V16QI - V1HI V2HI V4HI V8HI - V1SI V2SI V4SI]) -(define_insn "*movdi<mode>_zero_extend_B" - [(set (match_operand:DI 0 "register_operand" "=d") - (zero_extend:DI (vec_select:<non_vec> - (match_operand:VLGV_DI 1 "register_operand" "v") - (parallel [(match_operand:SI 2 "const_int_operand" "n")]))))] - "TARGET_VX" -{ - operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1)); - return "vlgv<bhfgq>\t%0,%v1,%Y2"; -} - [(set_attr "op_type" "VRS") - (set_attr "mnemonic" "vlgv<bhfgq>")]) - -(define_mode_iterator VLGV_SI [V1QI V2QI V4QI V8QI V16QI - V1HI V2HI V4HI V8HI]) -(define_insn "*movsi<mode>_zero_extend_B" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (vec_select:<non_vec> - (match_operand:VLGV_SI 1 "register_operand" "v") - (parallel [(match_operand:SI 2 "const_int_operand" "n")]))))] - "TARGET_VX" -{ - operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1)); - return "vlgv<bhfgq>\t%0,%v1,%Y2"; -} - [(set_attr "op_type" "VRS") - (set_attr "mnemonic" "vlgv<bhfgq>")]) - ; vec_load_lanes? ; vec_store_lanes? @@ -763,6 +715,42 @@ DONE; }) +; Instructions vlgvb, vlgvh, vlgvf zero all remaining bits of a GPR, i.e., +; an implicit zero extend is done. + +(define_mode_iterator VLGV_DI [V1QI V2QI V4QI V8QI V16QI + V1HI V2HI V4HI V8HI + V1SI V2SI V4SI]) +(define_insn "*vec_extract<mode>_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=d") + (zero_extend:DI (vec_select:<non_vec> + (match_operand:VLGV_DI 1 "register_operand" "v") + (parallel [(match_operand:SI 2 "nonmemory_operand" "an")]))))] + "TARGET_VX" +{ + if (CONST_INT_P (operands[2])) + operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1)); + return "vlgv<bhfgq>\t%0,%v1,%Y2"; +} + [(set_attr "op_type" "VRS") + (set_attr "mnemonic" "vlgv<bhfgq>")]) + +(define_mode_iterator VLGV_SI [V1QI V2QI V4QI V8QI V16QI + V1HI V2HI V4HI V8HI]) +(define_insn "*vec_extract<mode>_zero_extend" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI (vec_select:<non_vec> + (match_operand:VLGV_SI 1 "register_operand" "v") + (parallel [(match_operand:SI 2 "nonmemory_operand" "an")]))))] + "TARGET_VX" +{ + if (CONST_INT_P (operands[2])) + operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1)); + return "vlgv<bhfgq>\t%0,%v1,%Y2"; +} + [(set_attr "op_type" "VRS") + (set_attr "mnemonic" "vlgv<bhfgq>")]) + (define_insn "*vec_vllezlf<mode>" [(set (match_operand:V_HW_4 0 "register_operand" "=v") (vec_concat:V_HW_4 |