rs6000.h (processor_type): Add PPC440.

	* config/rs6000/rs6000.h (processor_type): Add PPC440.
	* config/rs6000/rs6000.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE,
	TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD,
	TARGET_SCHED_VARIABLE_ISSUE): Define.
	(rs6000_use_dfa_pipeline_interface): New function.
	(rs6000_multipass_dfa_lookahead): New Function.
	(rs6000_variable_issue): New function.
	(rs6000_adjust_cost): Add CMP and DELAYED_CR types.
	(rs6000_issue_rate): Add PPC440.
	* config/rs6000/rs6000.md (unspec list): Correct typo.
	(attr "type"): Add load_ext, load_ext_u, load_ext_ux, load_u,
	store_ux, store_u, fpload_ux, fpload_u, fpstore_ux, fpstore_u,
	cmp, delayed_cr, mfcr, mtcr.
	(automata_option): Set "ndfa".
	(extendMMNN2): Update attributes.
	(movcc_internal1): Discourage move to non-cr0.  Update
	attributes.
	(movMM_update): Update attributes.
	(cmpMM_internal): Update attributes.
	(sCC CR materialization): Update attributes.
	(branch patterns): Do not discourage non-cr0.
	(cr logical patterns): Prefer destructive register allocation.
	Update attributes.
	(movesi_from_cr): Update attribute.
	(mtcrf_operation): Update attribute.
	(mtcrfsi): Update attribute.
	* config/rs6000/40x.md: New file.
	* config/rs6000/603.md: New file.
	* config/rs6000/6xx.md: New file.
	* config/rs6000/7450.md: New file.
	* config/rs6000/7xx.md: New file.
	* config/rs6000/mpc.md: New file.
	* config/rs6000/power4.md: New file.
	* config/rs6000/rios1.md: New file.
	* config/rs6000/rios2.md: New file.
	* config/rs6000/rs64.md: New file.
	[Some DFA descriptions based on work by Michael Hayes]

From-SVN: r62943

1 files changed, 103 insertions, 0 deletions

diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
new file mode 100644
index 0000000..e304094
--- /dev/null
+++ b/gcc/config/rs6000/rs64.md
@@ -0,0 +1,103 @@
+(define_automaton "rs64,rs64fp,rs64other")
+(define_cpu_unit "iu_rs64" "rs64")
+(define_cpu_unit "mciu_rs64" "rs64")
+(define_cpu_unit "fpu_rs64" "rs64fp")
+(define_cpu_unit "lsu_rs64,bpu_rs64" "rs64other")
+
+;; RS64a 64-bit IU, LSU, FPU, BPU
+
+(define_insn_reservation "rs64a-load" 2
+  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
+       (eq_attr "cpu" "rs64a"))
+  "lsu_rs64")
+
+(define_insn_reservation "rs64a-store" 1
+  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
+       (eq_attr "cpu" "rs64a"))
+  "lsu_rs64")
+
+(define_insn_reservation "rs64a-fpload" 3
+  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
+       (eq_attr "cpu" "rs64a"))
+  "lsu_rs64")
+
+(define_insn_reservation "rs64a-integer" 1
+  (and (eq_attr "type" "integer")
+       (eq_attr "cpu" "rs64a"))
+  "iu_rs64")
+
+(define_insn_reservation "rs64a-imul" 20
+  (and (eq_attr "type" "imul")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*13")
+
+(define_insn_reservation "rs64a-imul2" 12
+  (and (eq_attr "type" "imul2")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*5")
+
+(define_insn_reservation "rs64a-imul3" 8
+  (and (eq_attr "type" "imul3")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*2")
+
+(define_insn_reservation "rs64a-lmul" 34
+  (and (eq_attr "type" "lmul")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*34")
+
+(define_insn_reservation "rs64a-idiv" 66
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*66")
+
+(define_insn_reservation "rs64a-ldiv" 66
+  (and (eq_attr "type" "ldiv")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64*66")
+
+(define_insn_reservation "rs64a-compare" 3
+  (and (eq_attr "type" "compare,delayed_compare")
+       (eq_attr "cpu" "rs64a"))
+  "iu_rs64,nothing,bpu_rs64")
+
+(define_insn_reservation "rs64a-fpcompare" 5
+  (and (eq_attr "type" "fpcompare")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64,fpu_rs64,bpu_rs64")
+
+(define_insn_reservation "rs64a-fp" 4
+  (and (eq_attr "type" "fp,dmul")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64,fpu_rs64")
+
+(define_insn_reservation "rs64a-sdiv" 31
+  (and (eq_attr "type" "sdiv,ddiv")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64,fpu_rs64*31")
+
+(define_insn_reservation "rs64a-sqrt" 49
+  (and (eq_attr "type" "ssqrt,dsqrt")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64,fpu_rs64*49")
+
+(define_insn_reservation "rs64a-mfcr" 2
+  (and (eq_attr "type" "mfcr")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64")
+
+(define_insn_reservation "rs64a-mtcr" 3
+  (and (eq_attr "type" "mtcr")
+       (eq_attr "cpu" "rs64a"))
+  "mciu_rs64")
+
+(define_insn_reservation "rs64a-mtjmpr" 5
+  (and (eq_attr "type" "mtjmpr")
+       (eq_attr "cpu" "rs64a"))
+  "bpu_rs64")
+
+(define_insn_reservation "rs64a-jmpreg" 1
+  (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr")
+       (eq_attr "cpu" "rs64a"))
+  "bpu_rs64")
+