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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-04-12 19:25:56 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-04-12 19:25:56 +0000 |
| commit | 20b9851c46d589a350b81ddb00db9a8cc424f048 (patch) | |
| tree | d43ead551f5fd243b64878a8c51bad5b5ea3871b /gcc/config/rs6000/rs6000.md | |
| parent | 2b2f52bccfd2f83ff0ed5e33baabd9f9266132f3 (diff) | |
| download | gcc-20b9851c46d589a350b81ddb00db9a8cc424f048.zip gcc-20b9851c46d589a350b81ddb00db9a8cc424f048.tar.gz gcc-20b9851c46d589a350b81ddb00db9a8cc424f048.tar.bz2 | |
re PR middle-end/70680 (OpenMP SIMD linear variable privatized too eagerly)
[gcc]
2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70680
* config/rs6000/rs6000.md (ieee_128bit_vsx_neg<mode>2_internal):
Do not use "=" constraint on an input constraint.
(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
(ieee_128bit_vsx_nabs<mode>2): Correct splitter so that it
generates (neg (abs ...)) instead of (abs ...).
[gcc/testsuite]
2016-04-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70680
* gcc.target/powerpc/pr70640.c: New test.
From-SVN: r234910
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ef1dea8..849b19a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7261,7 +7261,7 @@ (define_insn "*ieee_128bit_vsx_neg<mode>2_internal" [(set (match_operand:IEEE128 0 "register_operand" "=wa") (neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) - (use (match_operand:V16QI 2 "register_operand" "=v"))] + (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlxor %x0,%x1,%x2" [(set_attr "type" "vecsimple")]) @@ -7290,7 +7290,7 @@ (define_insn "*ieee_128bit_vsx_abs<mode>2_internal" [(set (match_operand:IEEE128 0 "register_operand" "=wa") (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) - (use (match_operand:V16QI 2 "register_operand" "=v"))] + (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlandc %x0,%x1,%x2" [(set_attr "type" "vecsimple")]) @@ -7306,7 +7306,7 @@ "#" "&& 1" [(parallel [(set (match_dup 0) - (abs:IEEE128 (match_dup 1))) + (neg:IEEE128 (abs:IEEE128 (match_dup 1)))) (use (match_dup 2))])] { if (GET_CODE (operands[2]) == SCRATCH) @@ -7323,7 +7323,7 @@ (neg:IEEE128 (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))) - (use (match_operand:V16QI 2 "register_operand" "=v"))] + (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlor %x0,%x1,%x2" [(set_attr "type" "vecsimple")]) |