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author | Ilia Diachkov <ilia.diachkov@optimitech.com> | 2019-07-23 01:29:34 +0000 |
---|---|---|
committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-07-22 18:29:34 -0700 |
commit | ffbb9818b0efd04bff65c372e3e9444fae634363 (patch) | |
tree | 76e6f330d40b40313cb182a14bd72177b0e8abe1 /gcc/config/riscv | |
parent | 1d46067b347ab1814de3cdd7f620f5c8ca73232a (diff) | |
download | gcc-ffbb9818b0efd04bff65c372e3e9444fae634363.zip gcc-ffbb9818b0efd04bff65c372e3e9444fae634363.tar.gz gcc-ffbb9818b0efd04bff65c372e3e9444fae634363.tar.bz2 |
RISC-V: Add -malign-data= option.
gcc/
Ilia Diachkov <ilia.diachkov@optimitech.com>
* config/riscv/riscv-opts.h (struct riscv_align_data): New.
* config/riscv/riscv.c (riscv_constant_alignment): Use
riscv_align_data_type.
* config/riscv/riscv.h (RISCV_EXPAND_ALIGNMENT): New.
(DATA_ALIGNMENT): Use RISCV_EXPAND_ALIGNMENT.
(LOCAL_ALIGNMENT): Use RISCV_EXPAND_ALIGNMENT.
* config/riscv/riscv.opt (malign-data): New.
* doc/invoke.texi (RISC-V Options): Document -malign-data=.
From-SVN: r273714
Diffstat (limited to 'gcc/config/riscv')
-rw-r--r-- | gcc/config/riscv/riscv-opts.h | 5 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.c | 3 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.h | 17 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.opt | 14 |
4 files changed, 32 insertions, 7 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index f3031f2..d00fbe2 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -46,4 +46,9 @@ enum riscv_microarchitecture_type { }; extern enum riscv_microarchitecture_type riscv_microarchitecture; +enum riscv_align_data { + riscv_align_data_type_xlen, + riscv_align_data_type_natural +}; + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 8ac09f2..e274f1b 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -4904,7 +4904,8 @@ riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass) static HOST_WIDE_INT riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) { - if (TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) + if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) + && (riscv_align_data_type == riscv_align_data_type_xlen)) return MAX (align, BITS_PER_WORD); return align; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 4509d73..5fc9be8 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -168,6 +168,13 @@ along with GCC; see the file COPYING3. If not see mode that should actually be used. We allow pairs of registers. */ #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) +/* DATA_ALIGNMENT and LOCAL_ALIGNMENT common definition. */ +#define RISCV_EXPAND_ALIGNMENT(COND, TYPE, ALIGN) \ + (((COND) && ((ALIGN) < BITS_PER_WORD) \ + && (TREE_CODE (TYPE) == ARRAY_TYPE \ + || TREE_CODE (TYPE) == UNION_TYPE \ + || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) + /* If defined, a C expression to compute the alignment for a static variable. TYPE is the data type, and ALIGN is the alignment that the object would ordinarily have. The value of this macro is used @@ -180,18 +187,16 @@ along with GCC; see the file COPYING3. If not see cause character arrays to be word-aligned so that `strcpy' calls that copy constants to character arrays can be done inline. */ -#define DATA_ALIGNMENT(TYPE, ALIGN) \ - ((((ALIGN) < BITS_PER_WORD) \ - && (TREE_CODE (TYPE) == ARRAY_TYPE \ - || TREE_CODE (TYPE) == UNION_TYPE \ - || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + RISCV_EXPAND_ALIGNMENT (riscv_align_data_type == riscv_align_data_type_xlen, \ + TYPE, ALIGN) /* We need this for the same reason as DATA_ALIGNMENT, namely to cause character arrays to be word-aligned so that `strcpy' calls that copy constants to character arrays can be done inline, and 'strcmp' can be optimised to use word loads. */ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ - DATA_ALIGNMENT (TYPE, ALIGN) + RISCV_EXPAND_ALIGNMENT (true, TYPE, ALIGN) /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 3b25f9a..7f0c35e 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -131,3 +131,17 @@ Mask(RVE) mriscv-attribute Target Report Var(riscv_emit_attribute_p) Init(-1) Emit RISC-V ELF attribute. + +malign-data= +Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_xlen) +Use the given data alignment. + +Enum +Name(riscv_align_data) Type(enum riscv_align_data) +Known data alignment choices (for use with the -malign-data= option): + +EnumValue +Enum(riscv_align_data) String(xlen) Value(riscv_align_data_type_xlen) + +EnumValue +Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural) |