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| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-04-05 09:46:37 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-05-02 13:08:03 -0700 |
| commit | d199d2e56da2379004e7e0457150409c0c99d3e6 (patch) | |
| tree | 8ca8443b6efb35e193d43c14d8b066b339f49d34 /gcc/config/riscv/sync.md | |
| parent | 4990cf84c460f064d6281d0813f20b0ef20c7448 (diff) | |
| download | gcc-d199d2e56da2379004e7e0457150409c0c99d3e6.zip gcc-d199d2e56da2379004e7e0457150409c0c99d3e6.tar.gz gcc-d199d2e56da2379004e7e0457150409c0c99d3e6.tar.bz2 | |
RISC-V: Enforce atomic compare_exchange SEQ_CST
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
pair.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diffstat (limited to 'gcc/config/riscv/sync.md')
| -rw-r--r-- | gcc/config/riscv/sync.md | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 0c83ef0..5620d6f 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -297,9 +297,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr.<amo>.aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc.<amo>.rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap<mode>" [(match_operand:SI 0 "register_operand" "") ;; bool output |