haifa-sched.c: Convert to target hooks.

	* haifa-sched.c: Convert to target hooks.  Macros replaced
	are ISSUE_RATE, ADJUST_COST, ADJUST_PRIORITY, MD_SCHED_INIT,
	MD_SCHED_REORDER, MD_SCHED_REORDER2, MD_SCHED_VARIABLE_ISSUE,
	MD_SCHED_FINISH, and HAVE_cycle_display.
	* target-def.h (TARGET_SCHED_ADJUST_COST,
	TARGET_SCHED_ADJUST_PRIORITY, TARGET_SCHED_ISSUE_RATE,
	TARGET_SCHED_VARIABLE_ISSUE, TARGET_SCHED_INIT,
	TARGET_SCHED_FINISH, TARGET_SCHED_REORDER,
	TARGET_SCHED_REORDER2, TARGET_SCHED_CYCLE_DISPLAY):
	New hook #defines to be overridden.
	(TARGET_SCHED): Bring them all together.
	(TARGET_INITIALIZER): Update.
	* target.h: Don't forward declare struct rtx_def.  Use 'rtx'
	instead of 'struct rtx_def *' throughout.
	(struct sched): New set of hooks for the scheduler.
	* Makefile.in (haifa-sched.o): Depend on target.h.
	* doc/tm.texi: Document the new scheduler hooks, together in
	their own section, instead of scattered around.
	Fix a bunch of underfull/overfull hboxes.

	* a29k.h, alpha.h, arm.h, c4x.h, convex.h, d30v.h, i386.h,
	ia64.h, m32r.h, m88k.h, mips.h, pa.h, rs6000.h, s390.h, sh.h,
	sparc.h: Don't define any of the old scheduler macros.

	* a29k.c, alpha.c, arm.c, c4x.c, convex.c, d30v.c, i386.c,
	ia64.c, m32r.c, m88k.c, mips.c, pa.c, rs6000.c, s390.c, sh.c,
	sparc.c: Create hook functions from code extracted from
	corresponding target header, or make existing hooks static, as
	appropriate.  Set the appropriate entries in targetm.

	* alpha-protos.h, arm-protos.h, c4x-protos.h, d30v-protos.h,
	i386-protos.h, ia64-protos.h, m32r-protos.h, pa-protos.h,
	rs6000-protos.h, s390-protos.h, sparc-protos.h:
	Remove prototypes for functions which are now static.

	* d30v.h, d30v.c, m32r.h, m32r.c: Remove #ifdef HAIFA and
	related gunk; the Haifa scheduler is now the only choice.

From-SVN: r45009

1 files changed, 65 insertions, 1 deletions

diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 5517f99..85183ff 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -69,6 +69,9 @@ static rtx store_reg PARAMS ((int, int, int));
 static rtx load_reg PARAMS ((int, int, int));
 static rtx set_reg_plus_d PARAMS ((int, int, int));
 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
+static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
+static int pa_adjust_priority PARAMS ((rtx, int));
+static int pa_issue_rate PARAMS ((void));
 
 /* Save the operands last given to a compare for use when we
    generate a scc or bcc insn.  */
@@ -115,6 +118,13 @@ int n_deferred_plabels = 0;
 #undef TARGET_ASM_FUNCTION_EPILOGUE
 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
 
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST pa_adjust_cost
+#undef TARGET_SCHED_ADJUST_PRIORITY
+#define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE pa_issue_rate
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 void
@@ -3591,7 +3601,7 @@ gen_cmp_fp (code, operand0, operand1)
 /* Adjust the cost of a scheduling dependency.  Return the new cost of
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
-int
+static int
 pa_adjust_cost (insn, link, dep_insn, cost)
      rtx insn;
      rtx link;
@@ -3829,6 +3839,60 @@ pa_adjust_cost (insn, link, dep_insn, cost)
     abort ();
 }
 
+/* Adjust scheduling priorities.  We use this to try and keep addil
+   and the next use of %r1 close together.  */
+static int
+pa_adjust_priority (insn, priority)
+     rtx insn;
+     int priority;
+{
+  rtx set = single_set (insn);
+  rtx src, dest;
+  if (set)
+    {
+      src = SET_SRC (set);
+      dest = SET_DEST (set);
+      if (GET_CODE (src) == LO_SUM
+	  && symbolic_operand (XEXP (src, 1), VOIDmode)
+	  && ! read_only_operand (XEXP (src, 1), VOIDmode))
+	priority >>= 3;
+
+      else if (GET_CODE (src) == MEM
+	       && GET_CODE (XEXP (src, 0)) == LO_SUM
+	       && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
+	       && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
+	priority >>= 1;
+
+      else if (GET_CODE (dest) == MEM
+	       && GET_CODE (XEXP (dest, 0)) == LO_SUM
+	       && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
+	       && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
+	priority >>= 3;
+    }
+  return priority;
+}
+
+/* The 700 can only issue a single insn at a time.
+   The 7XXX processors can issue two insns at a time.
+   The 8000 can issue 4 insns at a time.  */
+static int
+pa_issue_rate ()
+{
+  switch (pa_cpu)
+    {
+    case PROCESSOR_700:		return 1;
+    case PROCESSOR_7100:	return 2;
+    case PROCESSOR_7100LC:	return 2;
+    case PROCESSOR_7200:	return 2;
+    case PROCESSOR_8000:	return 4;
+
+    default:
+      abort ();
+    }
+}
+
+
+
 /* Return any length adjustment needed by INSN which already has its length
    computed as LENGTH.   Return zero if no adjustment is necessary.