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| author | Stafford Horne <shorne@gmail.com> | 2019-07-21 20:58:54 +0000 |
|---|---|---|
| committer | Stafford Horne <shorne@gcc.gnu.org> | 2019-07-21 20:58:54 +0000 |
| commit | 2e92185a033ec94d3dbaf22577110883db1474a1 (patch) | |
| tree | fc6aa93cd23671359f287d9ce587e2737dba0552 /gcc/config/or1k | |
| parent | 48df93911ab1b71a533934419c320fe9102b5ec1 (diff) | |
| download | gcc-2e92185a033ec94d3dbaf22577110883db1474a1.zip gcc-2e92185a033ec94d3dbaf22577110883db1474a1.tar.gz gcc-2e92185a033ec94d3dbaf22577110883db1474a1.tar.bz2 | |
or1k: Fix code quality for volatile memory loads
Volatile memory does not match the memory_operand predicate. This
causes extra extend/mask instructions instructions when reading
from volatile memory. On OpenRISC loading volatile memory can be
treated the same as regular memory loads which supports combined
sign/zero extends. Fixing this eliminates the need for extra
extend/mask instructions.
This also adds a test provided by Richard Selvaggi which uncovered the
issue while we were looking into another issue.
gcc/ChangeLog:
PR target/90363
* config/or1k/or1k.md (zero_extend<mode>si2): Update predicate.
(extend<mode>si2): Update predicate.
* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
(reg_or_mem_operand): New.
gcc/testsuite/ChangeLog:
PR target/90363
* gcc.target/or1k/swap-1.c: New test.
* gcc.target/or1k/swap-2.c: New test.
From-SVN: r273647
Diffstat (limited to 'gcc/config/or1k')
| -rw-r--r-- | gcc/config/or1k/or1k.md | 6 | ||||
| -rw-r--r-- | gcc/config/or1k/predicates.md | 18 |
2 files changed, 21 insertions, 3 deletions
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 2dad51c..757d899 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -328,11 +328,11 @@ ;; Sign Extending ;; ------------------------------------------------------------------------- -;; Zero extension can always be done with AND and an extending load. +;; Zero extension can always be done with AND or an extending load. (define_insn "zero_extend<mode>si2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "" "@ l.andi\t%0, %1, <zext_andi> @@ -344,7 +344,7 @@ (define_insn "extend<mode>si2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "TARGET_SEXT" "@ l.ext<ldst>s\t%0, %1 diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index 879236b..dad1c5d 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -82,3 +82,21 @@ (define_predicate "equality_comparison_operator" (match_code "ne,eq")) + +;; Borrowed from rs6000 +;; Return true if the operand is in volatile memory. Note that during the +;; RTL generation phase, memory_operand does not return TRUE for volatile +;; memory references. So this function allows us to recognize volatile +;; references where it's safe. +(define_predicate "volatile_mem_operand" + (and (match_code "mem") + (match_test "MEM_VOLATILE_P (op)") + (if_then_else (match_test "reload_completed") + (match_operand 0 "memory_operand") + (match_test "memory_address_p (mode, XEXP (op, 0))")))) + +;; Return true if the operand is a register or memory; including volatile +;; memory. +(define_predicate "reg_or_mem_operand" + (ior (match_operand 0 "nonimmediate_operand") + (match_operand 0 "volatile_mem_operand"))) |