or1k: Add mrori option, fix option docs

gcc/ChangeLog:

	* config.gcc (or1k*-*-*): Add mrori and mror to validation.
	* doc/invoke.texi (OpenRISC Options): Add mrori option, rewrite all
	documenation to be more clear.
	* config/or1k/elf.opt (mboard=, mnewlib): Rewrite documentation to be
	more clear.
	* config/or1k/or1k.opt (mrori): New option.
	(mhard-div, msoft-div, mhard-mul, msoft-mul, mcmov, mror, msext,
	msfimm, mshftimm): Rewrite documentation to be more clear.
	* config/or1k/or1k.md (insn_support): Add ror and rori.
	(enabled): Add conditions for ror and rori.
	(rotrsi3): Replace condition for shftimm with ror and rori.

gcc/testsuite/ChangeLog:

	* gcc.target/or1k/ror-4.c: New file.
	* gcc.target/or1k/shftimm-1.c: Update test from rotate to shift
	as the shftimm option no longer controls rotate.

From-SVN: r273649

4 files changed, 51 insertions, 32 deletions

diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt
index 641b6dd..2d4d187 100644
--- a/gcc/config/or1k/elf.opt
+++ b/gcc/config/or1k/elf.opt
@@ -25,9 +25,9 @@
 
 mboard=
 Target RejectNegative Joined
-Configure board specific runtime.
+Configure the newlib board specific runtime.  The default is or1ksim.
 
 mnewlib
 Target RejectNegative
-For compatibility, it's always newlib for elf now.
-
+This option is ignored; it is provided for compatibility purposes only.  This
+used to select linker and preprocessor options for use with newlib.
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 757d899..0faa0fa 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -63,7 +63,7 @@
   "alu,st,ld,control,multi"
   (const_string "alu"))
 
-(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string "class1"))
+(define_attr "insn_support" "class1,sext,sfimm,shftimm,ror,rori" (const_string "class1"))
 
 (define_attr "enabled" ""
   (cond [(eq_attr "insn_support" "class1") (const_int 1)
@@ -72,7 +72,11 @@
 	 (and (eq_attr "insn_support" "sfimm")
 	      (ne (symbol_ref "TARGET_SFIMM") (const_int 0))) (const_int 1)
 	 (and (eq_attr "insn_support" "shftimm")
-	      (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)]
+	      (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)
+	 (and (eq_attr "insn_support" "ror")
+	      (ne (symbol_ref "TARGET_ROR") (const_int 0))) (const_int 1)
+	 (and (eq_attr "insn_support" "rori")
+	      (ne (symbol_ref "TARGET_RORI") (const_int 0))) (const_int 1)]
 	(const_int 0)))
 
 ;; Describe a user's asm statement.
@@ -178,12 +182,12 @@
 (define_insn "rotrsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(rotatert:SI (match_operand:SI 1 "register_operand"  "r,r")
-		  (match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
-  "TARGET_ROR"
+		     (match_operand:SI 2 "ror_reg_or_u6_operand" "r,n")))]
+  "TARGET_ROR || TARGET_RORI"
   "@
    l.ror\t%0, %1, %2
    l.rori\t%0, %1, %2"
-  [(set_attr "insn_support" "*,shftimm")])
+  [(set_attr "insn_support" "ror,rori")])
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
index 7bdbd84..c2f64c5 100644
--- a/gcc/config/or1k/or1k.opt
+++ b/gcc/config/or1k/or1k.opt
@@ -21,47 +21,55 @@
 ; See the GCC internals manual (options.texi) for a description of
 ; this file's format.
 
-; Please try to keep this file in ASCII collating order.
-
 mhard-div
 Target RejectNegative InverseMask(SOFT_DIV)
-Use hardware divide instructions, use -msoft-div for emulation.
+Enable generation of hardware divide (l.div, l.divu) instructions.  This is the
+default; use -msoft-div to override.
+
+msoft-div
+Target RejectNegative Mask(SOFT_DIV)
+Enable generation of binaries which use functions from libgcc to perform divide
+operations.  The default is -mhard-div.
 
 mhard-mul
 Target RejectNegative InverseMask(SOFT_MUL).
-Use hardware multiply instructions, use -msoft-mul for emulation.
+Enable generation of hardware multiply instructions (l.mul, l.muli) instructions.
+This is the default; use -msoft-mul to override.
+
+msoft-mul
+Target RejectNegative Mask(SOFT_MUL).
+Enable generation of binaries which use functions from libgcc to perform
+multiply operations. The default is -mhard-mul.
 
 mcmov
 Target RejectNegative Mask(CMOV)
-Allows generation of binaries which use the l.cmov instruction.  If your target
-does not support this the compiler will generate the equivalent using set and
-branch.
+Enable generation of conditional move (l.cmov) instructions.  By default the
+equivalent will be generated using using set and branch.
 
 mror
 Target RejectNegative Mask(ROR)
-Allows generation of binaries which use the l.rori instructions.
+Enable generation of rotate right (l.ror) instructions.  By default functions
+from libgcc are used to perform rotate right operations.
+
+mrori
+Target RejectNegative Mask(RORI)
+Enable generation of rotate right with immediate (l.rori) instructions.  By
+default functions from libgcc are used to perform rotate right with immediate
+operations.
 
 msext
 Target RejectNegative Mask(SEXT)
-Allows generation of binaries which use sign-extension instructions.  If your
-target does not support this the compiler will use memory loads to perform sign
-extension.
+Enable generation of sign extension (l.ext*) instructions.  By default memory
+loads are used to perform sign extension.
 
 msfimm
 Target RejectNegative Mask(SFIMM)
-Allows generation of binaries which use l.sf*i instructions.  If your target
-does not support this the compiler will generate instructions to store the
-immediate to a register first.
+Enable generation of compare and set flag with immediate (l.sf*i) instructions.
+By default extra instructions will be generated to store the immediate to a
+register first.
 
 mshftimm
 Target RejectNegative Mask(SHFTIMM)
-Allows generation of binaries which support shifts and rotate instructions
-supporting immediate arguments, for example l.rori.
-
-msoft-div
-Target RejectNegative Mask(SOFT_DIV)
-Use divide emulation.
-
-msoft-mul
-Target RejectNegative Mask(SOFT_MUL).
-Use multiply emulation.
+Enable generation of shift with immediate (l.srai, l.srli, l.slli) instructions.
+By default extra instructions will be generated to store the immediate to a
+register first.
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index dad1c5d..5e97bf4 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -53,6 +53,13 @@
     (match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767")
     (match_operand 0 "register_operand")))
 
+(define_predicate "ror_reg_or_u6_operand"
+  (if_then_else (match_code "const_int")
+    (and (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f")
+	 (match_test "TARGET_RORI"))
+    (and (match_operand 0 "register_operand")
+	 (match_test "TARGET_ROR"))))
+
 (define_predicate "call_insn_operand"
   (ior (match_code "symbol_ref")
        (match_operand 0 "register_operand")))