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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2014-05-28 19:49:18 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2014-05-28 19:49:18 +0000 |
| commit | 73f793e3bb4e0a2bd04536f8bbc861c34cfec945 (patch) | |
| tree | 18194c4ebc03529b7414e609111af0e8e670d580 /gcc/config/nds32/nds32.md | |
| parent | 5a7555ab101f5796bc51f9175552d7c77f79754b (diff) | |
| download | gcc-73f793e3bb4e0a2bd04536f8bbc861c34cfec945.zip gcc-73f793e3bb4e0a2bd04536f8bbc861c34cfec945.tar.gz gcc-73f793e3bb4e0a2bd04536f8bbc861c34cfec945.tar.bz2 | |
md.texi: Document that the % constraint character must be at the beginning of the string.
gcc/
* doc/md.texi: Document that the % constraint character must
be at the beginning of the string.
* genoutput.c (validate_insn_alternatives): Check that '=',
'+' and '%' only appear at the beginning of a constraint.
* ira.c (commutative_constraint_p): Delete.
(ira_get_dup_out_num): Expect the '%' commutativity marker to be
at the start of the string.
* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
duplicate '='s.
* config/arm/neon.md (bicdi3_neon): Likewise.
* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
(slt_si, sltu_si): Likewise.
* config/vax/vax.md (sbcdi3): Likewise.
* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
(mul64): Move '%' to beginning of constraint.
* config/arm/arm.md (*xordi3_insn): Likewise.
* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
(xorsi3): Likewise.
From-SVN: r211031
Diffstat (limited to 'gcc/config/nds32/nds32.md')
| -rw-r--r-- | gcc/config/nds32/nds32.md | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 0402cad..da3a97a 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -261,7 +261,7 @@ (define_insn "add<mode>3" [(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") - (plus:QIHISI (match_operand:QIHISI 1 "register_operand" " 0, l, 0, l, %0, l, 0, k, r, r") + (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))] "" { @@ -382,9 +382,9 @@ ;; Multiplication instructions. (define_insn "mulsi3" - [(set (match_operand:SI 0 "register_operand" "= w, r") - (mult:SI (match_operand:SI 1 "register_operand" " %0, r") - (match_operand:SI 2 "register_operand" " w, r")))] + [(set (match_operand:SI 0 "register_operand" "=w, r") + (mult:SI (match_operand:SI 1 "register_operand" "%0, r") + (match_operand:SI 2 "register_operand" " w, r")))] "" "@ mul33\t%0, %2 @@ -489,9 +489,9 @@ ) (define_insn "andsi3" - [(set (match_operand:SI 0 "register_operand" "= w, r, l, l, l, l, l, l, r, r, r, r, r") - (and:SI (match_operand:SI 1 "register_operand" " %0, r, l, l, l, l, 0, 0, r, r, r, r, r") - (match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))] + [(set (match_operand:SI 0 "register_operand" "=w, r, l, l, l, l, l, l, r, r, r, r, r") + (and:SI (match_operand:SI 1 "register_operand" "%0, r, l, l, l, l, 0, 0, r, r, r, r, r") + (match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))] "" { HOST_WIDE_INT mask = INTVAL (operands[2]); @@ -585,9 +585,9 @@ ;; For V3/V3M ISA, we have 'or33' instruction. ;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2. (define_insn "iorsi3" - [(set (match_operand:SI 0 "register_operand" "= w, r, r, r") - (ior:SI (match_operand:SI 1 "register_operand" " %0, r, r, r") - (match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))] + [(set (match_operand:SI 0 "register_operand" "=w, r, r, r") + (ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r") + (match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))] "" { int one_position; @@ -645,9 +645,9 @@ ;; For V3/V3M ISA, we have 'xor33' instruction. ;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2. (define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "= w, r, r, r") - (xor:SI (match_operand:SI 1 "register_operand" " %0, r, r, r") - (match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))] + [(set (match_operand:SI 0 "register_operand" "=w, r, r, r") + (xor:SI (match_operand:SI 1 "register_operand" "%0, r, r, r") + (match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))] "" { int one_position; |