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| author | Steve Ellcey <sellcey@mips.com> | 2014-01-27 22:38:42 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2014-01-27 22:38:42 +0000 |
| commit | a33fc7fe6c3f8c329c682877b1a7937a45d993dd (patch) | |
| tree | ed13b9b72950d17b817128567b457b3f811b139e /gcc/config/mips | |
| parent | 64688189487d5ca17892ef04d703b5b52b8810a3 (diff) | |
| download | gcc-a33fc7fe6c3f8c329c682877b1a7937a45d993dd.zip gcc-a33fc7fe6c3f8c329c682877b1a7937a45d993dd.tar.gz gcc-a33fc7fe6c3f8c329c682877b1a7937a45d993dd.tar.bz2 | |
mips-common.c (TARGET_DEFAULT_TARGET_FLAGS): Remove TARGET_FP_EXCEPTIONS_DEFAULT and MASK_FUSED_MADD.
2014-01-27 Steve Ellcey <sellcey@mips.com>
* common/config/mips/mips-common.c (TARGET_DEFAULT_TARGET_FLAGS):
Remove TARGET_FP_EXCEPTIONS_DEFAULT and MASK_FUSED_MADD.
* config/mips/mips.c (mips_option_override): Change setting
of TARGET_DSP.
* config/mips/mips.h (TARGET_FP_EXCEPTIONS_DEFAULT): Remove.
* config/mips/mips.opt (DSP, DSPR2, FP_EXCEPTIONS, FUSED_MADD,
MIPS3D) Change from Mask to Var.
From-SVN: r207154
Diffstat (limited to 'gcc/config/mips')
| -rw-r--r-- | gcc/config/mips/mips.c | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.opt | 12 |
3 files changed, 8 insertions, 12 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 5bad0f8..59c0b26 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -17084,9 +17084,9 @@ mips_option_override (void) mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; } - /* If TARGET_DSPR2, enable MASK_DSP. */ + /* If TARGET_DSPR2, enable TARGET_DSP. */ if (TARGET_DSPR2) - target_flags |= MASK_DSP; + TARGET_DSP = true; /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index bc9d301..150cf0c 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -588,10 +588,6 @@ struct mips_cpu_info { #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN #endif -#ifndef TARGET_FP_EXCEPTIONS_DEFAULT -#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS -#endif - #ifdef IN_LIBGCC2 #undef TARGET_64BIT /* Make this compile time constant for libgcc2 */ diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 877ec59..be551a7 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -116,11 +116,11 @@ Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations mdsp -Target Report Mask(DSP) +Target Report Var(TARGET_DSP) Use MIPS-DSP instructions mdspr2 -Target Report Mask(DSPR2) +Target Report Var(TARGET_DSPR2) Use MIPS-DSP REV 2 instructions mdebug @@ -190,7 +190,7 @@ Target Report Var(TARGET_4300_MUL_FIX) Work around an early 4300 hardware bug mfp-exceptions -Target Report Mask(FP_EXCEPTIONS) +Target Report Var(TARGET_FP_EXCEPTIONS) Init(1) FP exceptions are enabled mfp32 @@ -206,7 +206,7 @@ Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC) -mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines mfused-madd -Target Report Mask(FUSED_MADD) +Target Report Var(TARGET_FUSED_MADD) Init(1) Generate floating-point multiply-add instructions mabs= @@ -264,7 +264,7 @@ Target Report RejectNegative Mask(MIPS16) Generate MIPS16 code mips3d -Target Report RejectNegative Mask(MIPS3D) +Target Report RejectNegative Var(TARGET_MIPS3D) Use MIPS-3D instructions mllsc @@ -324,7 +324,7 @@ Target Report RejectNegative InverseMask(MIPS16) Generate normal-mode code mno-mips3d -Target Report RejectNegative InverseMask(MIPS3D) +Target Report RejectNegative Var(TARGET_MIPS3D, 0) Do not use MIPS-3D instructions mpaired-single |